README
1Overview
2--------
3The LS1028A Reference Design (RDB) is a high-performance computing,
4evaluation, and development platform that supports ARM SoC LS1028A and its
5derivatives.
6
7LS1028A SoC Overview
8--------------------------------------
9Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
10
11RDB Default Switch Settings (1: ON; 0: OFF)
12-------------------------------------------
13For XSPI NOR boot (default)
14SW2: 1111_1000
15SW3: 1111_0000
16SW5: 0011_1001
17
18For SD Boot
19SW2: 1000_1000
20SW3: 1111_0000
21SW5: 0011_1001
22
23For eMMC Boot
24SW2: 1001_1000
25SW3: 1111_0000
26SW5: 0011_1001
27
28LS1028ARDB board Overview
29-------------------------
30Processor
31 Two Arm Cortex- A72 processor cores:
32 - Based on 64-bit ARMv8 architecture
33 - Up to 1.3 GHz operation
34 - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
35 data cache
36 - Arranged as a single cluster of two cores sharing a single 1 MB L2
37 cache
38DDR memory
39 - Five onboard 1G x8 discrete memory modules (Four data byte lanes
40 ECC)
41 - 32-bit data and 4-bit ECC
42 - One chip select
43 - Data transfer rates of up to 1.6 GT/s
44 - Single-bit error correction and double-bit error detection ECC (4-bit
45 check word across 32-bit data)
46High-speed serial ports(SerDes)
47 - Lane 0: Supports one 1 GbE RJ45 SGMII, connected through the
48 Qualcomm AR8033 PHY
49 - Lane 1: Supports four 1.25 GbE RJ45 QSGMII, each connected
50 through the NXP F104S8A PHY
51 - Lane 2: Connects to one PCIe M.2 Key-E slot to support PCIe Gen3
52 (8 Gbit/s) cards
53 - Lane 3: Connects to one PCIe M.2 Key-E slot or one SATA M.2 Key-B
54 slot through a register mux to support either PCIe Gen 3 (8 Gbit/s) or
55 SATA Gen 3 cards (6 Gbit/s) at a time
56eSDHC
57 - eSDHC1, eSDHC2
58SPI
59 - Connects to two mikroBUS sockets to support mikro-click modules,
60 such as Bluetooth 4.0, 2.4 GHz IEEE 802.15.4 radio transceiver, near
61 field communications (NFC) controller
62Octal SPI (XSPI)
63 - One 256 MB onboard XSPI serial NOR flash memory
64 - One 512 MB onboard XSPI serial NAND flash memory
65 - Supports a QSPI emulator for offboard QSPI emulation
66I2C
67 - All system devices are accessed via I2C1, which is multiplexed on
68 I2C multiplexer PCA9848 to isolate address conflicts and reduce
69 capacitive load
70 - I2C1 is used for EEPROMs, RTC, INA220 current-power sensor,
71 thermal monitor, PCIe/SATA M.2 connectors and mikro-click modules
72 1 and 2
73CAN
74 - The two CAN DB9 ports can support CAN FD fast phase at data rates of
75 up to 5 Mbit/s
76Serial audio interface(SAI)
77 - Audio codec SGTL5000 provides headphone and audio LINEOUT for
78 stereo speakers
79 - IEEE1588 interface to support audio on SAI4
80
81QDS Default Switch Settings (1: ON; 0: OFF)
82-------------------------------------------
83For SD Boot
84SW1 : 1000_0000
85SW2 : 1110_0110
86SW3 : 0000_0010
87SW4 : 0000_0000
88SW5 : 0000_0000
89SW6 : 0000_0000
90SW7 : 1111_0011
91SW8 : 1110_0000
92SW9 : 1000_0001
93SW10: 1110_0000
94
95For XSPI Boot
96SW1 : 1111_0000
97SW2 : 0000_0110
98SW3 : 0000_0010
99SW4 : 0000_0000
100SW5 : 0110_0000
101SW6 : 0101_0000
102SW7 : 1111_0011
103SW8 : 1110_0000
104SW9 : 1000_0000
105SW10: 1110_0000
106
107LS1028AQDS board Overview
108-------------------------
109Processor
110 Two Arm Cortex- A72 processor cores:
111 - Based on 64-bit ARMv8 architecture
112 - Up to 1.3 GHz operation
113 - Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
114 data cache
115 - Arranged as a single cluster of two cores sharing a single 1 MB L2
116 cache
117DDR memory
118 - Supports data rates of up to 1.6 GT/s for both, DDR4 and DDR3L
119 - Supports a single- or dual-ranked SODIMM or UDIMM connector
120 - 32-bit data and 4-bit ECC
121 - Supports x8/x16 devices
122 - Supports ECC error detection and correction
123 - 1.35 V or 1.2 V DDR power supply, with automatic tracking of VTT, to
124 all devices in case of DDR3L or DDR4, respectively. Power can
125 switch to 1.35 V or 1.2 V, based on the switch settings for DDR3L or
126 DDR4 devices, respectively
127SerDes (Serializer/Deserializer)
128 - Four-lane (0-3) SerDes:
129 - Lane 0: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 10
130 Gbit SXGMII, 1 Gbit SGMII
131 - Lane 1: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
132 SGMII, 10 Gbit QXGMII, 5 Gbit QSGMII, 1 Gbit SGMII
133 - Lane 2: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
134 SGMII
135 - Lane 3: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
136 SGMII, SATA 2.0/3.0
137 - Four slots on SerDes lanes support PCIe Gen1/2/3, 1 Gbit SGMII
138 add-in cards
139 - Lane 1 connects to a 2x10 connector with SFP+ through a retimer;
140 lane 2 (TX lines) connects to an SMA connector
141 Lane 3 connects to 1x7 header to support SATA devices
142eSDHC
143 - eSDHC1, eSDHC2
144SPI
145 - SPI1 and SPI2 support three onboard SPI flash memory devices:
146 512 Mbit high-speed flash (with speed of up to 108/54 MHz)
147 memory for storage
148 4 Mbit low-speed flash memory (with speed of up to 40 MHz)
149 64 Mbit high-speed flash memory (with speed of up to 104/80
150 MHz)
151 - SPI3 supports one onboard 64 Mbit SPI flash memory (with speed of
152 up to 104/80 MHz)
153 - All memories operate at 1.8 V
154 - A header is provided on SPI1 to test SPI slave mode
155I2C
156 - LS1028A supports eight I2C controllers
157Serial audio interface(SAI)
158 Two SAI ports with audio codec SGTL5000:
159 - Include stereo LINEIN with support for external analog input
160 - Provide headphone and line output
161Display
162 - DisplayPort connector to connect the DP data to a 4K display device
163 (computer monitor)
164 - eDP connector to connect the DP data to a 4K display panel
165