1 /*
2 * Copyright 2018-2019 NXP
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <hang.h>
9 #include <init.h>
10 #include <log.h>
11 #include <spl.h>
12 #include <asm/global_data.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/imx8mp_pins.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/gpio.h>
18 #include <asm/mach-imx/iomux-v3.h>
19 #include <asm/mach-imx/mxc_i2c.h>
20 #include <asm/arch/ddr.h>
21 #include <power/pmic.h>
22 #include <power/pca9450.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
spl_board_boot_device(enum boot_device boot_dev_spl)26 int spl_board_boot_device(enum boot_device boot_dev_spl)
27 {
28 return BOOT_DEVICE_BOOTROM;
29 }
30
spl_dram_init(void)31 void spl_dram_init(void)
32 {
33 ddr_init(&dram_timing);
34 }
35
spl_board_init(void)36 void spl_board_init(void)
37 {
38 /*
39 * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
40 * not allow to change it. Should set the clock after PMIC
41 * setting done. Default is 400Mhz (system_pll1_800m with div = 2)
42 * set by ROM for ND VDD_SOC
43 */
44 clock_enable(CCGR_GIC, 0);
45 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5));
46 clock_enable(CCGR_GIC, 1);
47
48 puts("Normal Boot\n");
49 }
50
51 #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
52 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
53 struct i2c_pads_info i2c_pad_info1 = {
54 .scl = {
55 .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
56 .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
57 .gp = IMX_GPIO_NR(5, 14),
58 },
59 .sda = {
60 .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
61 .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
62 .gp = IMX_GPIO_NR(5, 15),
63 },
64 };
65
66 #ifdef CONFIG_POWER
67 #define I2C_PMIC 0
power_init_board(void)68 int power_init_board(void)
69 {
70 struct pmic *p;
71 int ret;
72
73 ret = power_pca9450_init(I2C_PMIC, 0x25);
74 if (ret)
75 printf("power init failed");
76 p = pmic_get("PCA9450");
77 pmic_probe(p);
78
79 /* BUCKxOUT_DVS0/1 control BUCK123 output */
80 pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
81
82 /*
83 * increase VDD_SOC to typical value 0.95V before first
84 * DRAM access, set DVS1 to 0.85v for suspend.
85 * Enable DVS control through PMIC_STBY_REQ and
86 * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
87 */
88 #ifdef CONFIG_IMX8M_VDD_SOC_850MV
89 /* set DVS0 to 0.85v for special case*/
90 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14);
91 #else
92 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
93 #endif
94 pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
95 pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
96
97 /* Kernel uses OD/OD freq for SOC */
98 /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
99 pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
100
101 /* set WDOG_B_CFG to cold reset */
102 pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
103
104 return 0;
105 }
106 #endif
107
108 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)109 int board_fit_config_name_match(const char *name)
110 {
111 /* Just empty function now - can't decide what to choose */
112 debug("%s: %s\n", __func__, name);
113
114 return 0;
115 }
116 #endif
117
118 /* Do not use BSS area in this phase */
board_init_f(ulong dummy)119 void board_init_f(ulong dummy)
120 {
121 int ret;
122
123 arch_cpu_init();
124
125 init_uart_clk(1);
126
127 board_early_init_f();
128
129 ret = spl_early_init();
130 if (ret) {
131 debug("spl_init() failed: %d\n", ret);
132 hang();
133 }
134
135 preloader_console_init();
136
137 enable_tzc380();
138
139 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
140
141 power_init_board();
142
143 /* DDR initialization */
144 spl_dram_init();
145 }
146