1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2005
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
6 */
7
8 #include <init.h>
9 #include <asm/mmu.h>
10 #include <asm/io.h>
11 #include <common.h>
12 #include <mpc83xx.h>
13 #include <pci.h>
14 #include <i2c.h>
15 #include <asm/fsl_i2c.h>
16 #include <linux/delay.h>
17
18 static struct pci_region pci1_regions[] = {
19 {
20 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
21 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
22 size: CONFIG_SYS_PCI1_MEM_SIZE,
23 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
24 },
25 {
26 bus_start: CONFIG_SYS_PCI1_IO_BASE,
27 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
28 size: CONFIG_SYS_PCI1_IO_SIZE,
29 flags: PCI_REGION_IO
30 },
31 {
32 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
33 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
34 size: CONFIG_SYS_PCI1_MMIO_SIZE,
35 flags: PCI_REGION_MEM
36 },
37 };
38
39 /*
40 * pci_init_board()
41 *
42 * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since
43 * per TQM834x design physical connections to external devices (PCI sockets)
44 * are routed only to the PCI1 we do not account for the second one - this code
45 * supports PCI1 module only. Should support for the PCI2 be required in the
46 * future it needs a separate pci_controller structure (above) and handling -
47 * please refer to other boards' implementation for dual PCI host controllers,
48 * for example board/Marvell/db64360/pci.c, pci_init_board()
49 *
50 */
51 void
pci_init_board(void)52 pci_init_board(void)
53 {
54 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
55 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
56 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
57 struct pci_region *reg[] = { pci1_regions };
58 u32 reg32;
59
60 /*
61 * Configure PCI controller and PCI_CLK_OUTPUT
62 *
63 * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one
64 * line actually used for clocking all external PCI devices in TQM83xx.
65 * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for
66 * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7
67 * are known to hang the board; this issue is under investigation
68 * (13 oct 05)
69 */
70 reg32 = OCCR_PCICOE1;
71 #if 0
72 /* enabling all PCI_CLK_OUTPUT lines HANGS the board... */
73 reg32 = 0xff000000;
74 #endif
75 if (clk->spmr & SPMR_CKID) {
76 /* PCI Clock is half CONFIG_SYS_CLK_FREQ so need to set up OCCR
77 * fields accordingly */
78 reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR);
79
80 reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \
81 | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \
82 | OCCR_PCICD6 | OCCR_PCICD7);
83 }
84
85 clk->occr = reg32;
86 udelay(2000);
87
88 /* Configure PCI Local Access Windows */
89 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
90 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
91
92 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
93 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
94
95 udelay(2000);
96
97 mpc83xx_pci_init(1, reg);
98 }
99