1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * (C) Copyright 2019, Xilinx, Inc,
4 * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
5 */
6
7 #include <common.h>
8 #include <cpu_func.h>
9 #include <log.h>
10 #include <asm/arch/sys_proto.h>
11 #include <memalign.h>
12 #include <versalpl.h>
13 #include <zynqmp_firmware.h>
14 #include <asm/cache.h>
15
versal_align_dma_buffer(ulong * buf,u32 len)16 static ulong versal_align_dma_buffer(ulong *buf, u32 len)
17 {
18 ulong *new_buf;
19
20 if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
21 new_buf = (ulong *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
22 memcpy(new_buf, buf, len);
23 buf = new_buf;
24 }
25
26 return (ulong)buf;
27 }
28
versal_load(xilinx_desc * desc,const void * buf,size_t bsize,bitstream_type bstype)29 static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
30 bitstream_type bstype)
31 {
32 ulong bin_buf;
33 int ret;
34 u32 buf_lo, buf_hi;
35 u32 ret_payload[PAYLOAD_ARG_CNT];
36
37 bin_buf = versal_align_dma_buffer((ulong *)buf, bsize);
38
39 debug("%s called!\n", __func__);
40 flush_dcache_range(bin_buf, bin_buf + bsize);
41
42 buf_lo = lower_32_bits(bin_buf);
43 buf_hi = upper_32_bits(bin_buf);
44
45 ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
46 buf_hi, 0, ret_payload);
47 if (ret)
48 printf("PL FPGA LOAD failed with err: 0x%08x\n", ret);
49
50 return ret;
51 }
52
53 struct xilinx_fpga_op versal_op = {
54 .load = versal_load,
55 };
56