1 /*
2 * Basic I2C functions
3 *
4 * Copyright (c) 2004 Texas Instruments
5 *
6 * This package is free software; you can redistribute it and/or
7 * modify it under the terms of the license found in the file
8 * named COPYING that should have accompanied this file.
9 *
10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 * Author: Jian Zhang jzhang@ti.com, Texas Instruments
15 *
16 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
17 * Rewritten to fit into the current U-Boot framework
18 *
19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
20 *
21 * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions
22 * New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
23 * (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
24 * OMAPs and derivatives as well. The only anticipated exception would
25 * be the OMAP2420, which shall require driver modification.
26 * - Rewritten i2c_read to operate correctly with all types of chips
27 * (old function could not read consistent data from some I2C slaves).
28 * - Optimized i2c_write.
29 * - New i2c_probe, performs write access vs read. The old probe could
30 * hang the system under certain conditions (e.g. unconfigured pads).
31 * - The read/write/probe functions try to identify unconfigured bus.
32 * - Status functions now read irqstatus_raw as per TRM guidelines
33 * (except for OMAP243X and OMAP34XX).
34 * - Driver now supports up to I2C5 (OMAP5).
35 *
36 * Copyright (c) 2014 Hannes Schmelzer <oe5hpm@oevsv.at>, B&R
37 * - Added support for set_speed
38 *
39 */
40
41 #include <common.h>
42 #include <dm.h>
43 #include <i2c.h>
44 #include <log.h>
45 #include <linux/delay.h>
46
47 #include <asm/io.h>
48 #include <asm/omap_i2c.h>
49
50 /*
51 * Provide access to architecture-specific I2C header files for platforms
52 * that are NOT yet solely relying on CONFIG_DM_I2C, CONFIG_OF_CONTROL, and
53 * the defaults provided in 'omap24xx_i2c.h' for all U-Boot stages where I2C
54 * access is desired.
55 */
56 #ifndef CONFIG_ARCH_K3
57 #include <asm/arch/i2c.h>
58 #endif
59
60 #include "omap24xx_i2c.h"
61
62 #define I2C_TIMEOUT 1000
63
64 /* Absolutely safe for status update at 100 kHz I2C: */
65 #define I2C_WAIT 200
66
67 enum {
68 OMAP_I2C_REV_REG = 0, /* Only on IP V1 (OMAP34XX) */
69 OMAP_I2C_IE_REG, /* Only on IP V1 (OMAP34XX) */
70 OMAP_I2C_STAT_REG,
71 OMAP_I2C_WE_REG,
72 OMAP_I2C_SYSS_REG,
73 OMAP_I2C_BUF_REG,
74 OMAP_I2C_CNT_REG,
75 OMAP_I2C_DATA_REG,
76 OMAP_I2C_SYSC_REG,
77 OMAP_I2C_CON_REG,
78 OMAP_I2C_OA_REG,
79 OMAP_I2C_SA_REG,
80 OMAP_I2C_PSC_REG,
81 OMAP_I2C_SCLL_REG,
82 OMAP_I2C_SCLH_REG,
83 OMAP_I2C_SYSTEST_REG,
84 OMAP_I2C_BUFSTAT_REG,
85 /* Only on IP V2 (OMAP4430, etc.) */
86 OMAP_I2C_IP_V2_REVNB_LO,
87 OMAP_I2C_IP_V2_REVNB_HI,
88 OMAP_I2C_IP_V2_IRQSTATUS_RAW,
89 OMAP_I2C_IP_V2_IRQENABLE_SET,
90 OMAP_I2C_IP_V2_IRQENABLE_CLR,
91 };
92
93 static const u8 __maybe_unused reg_map_ip_v1[] = {
94 [OMAP_I2C_REV_REG] = 0x00,
95 [OMAP_I2C_IE_REG] = 0x04,
96 [OMAP_I2C_STAT_REG] = 0x08,
97 [OMAP_I2C_WE_REG] = 0x0c,
98 [OMAP_I2C_SYSS_REG] = 0x10,
99 [OMAP_I2C_BUF_REG] = 0x14,
100 [OMAP_I2C_CNT_REG] = 0x18,
101 [OMAP_I2C_DATA_REG] = 0x1c,
102 [OMAP_I2C_SYSC_REG] = 0x20,
103 [OMAP_I2C_CON_REG] = 0x24,
104 [OMAP_I2C_OA_REG] = 0x28,
105 [OMAP_I2C_SA_REG] = 0x2c,
106 [OMAP_I2C_PSC_REG] = 0x30,
107 [OMAP_I2C_SCLL_REG] = 0x34,
108 [OMAP_I2C_SCLH_REG] = 0x38,
109 [OMAP_I2C_SYSTEST_REG] = 0x3c,
110 [OMAP_I2C_BUFSTAT_REG] = 0x40,
111 };
112
113 static const u8 __maybe_unused reg_map_ip_v2[] = {
114 [OMAP_I2C_STAT_REG] = 0x28,
115 [OMAP_I2C_WE_REG] = 0x34,
116 [OMAP_I2C_SYSS_REG] = 0x90,
117 [OMAP_I2C_BUF_REG] = 0x94,
118 [OMAP_I2C_CNT_REG] = 0x98,
119 [OMAP_I2C_DATA_REG] = 0x9c,
120 [OMAP_I2C_SYSC_REG] = 0x10,
121 [OMAP_I2C_CON_REG] = 0xa4,
122 [OMAP_I2C_OA_REG] = 0xa8,
123 [OMAP_I2C_SA_REG] = 0xac,
124 [OMAP_I2C_PSC_REG] = 0xb0,
125 [OMAP_I2C_SCLL_REG] = 0xb4,
126 [OMAP_I2C_SCLH_REG] = 0xb8,
127 [OMAP_I2C_SYSTEST_REG] = 0xbc,
128 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
129 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
130 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
131 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
132 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
133 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
134 };
135
136 struct omap_i2c {
137 struct udevice *clk;
138 int ip_rev;
139 struct i2c *regs;
140 unsigned int speed;
141 int waitdelay;
142 int clk_id;
143 };
144
omap_i2c_get_ip_reg_map(int ip_rev)145 static inline const u8 *omap_i2c_get_ip_reg_map(int ip_rev)
146 {
147 switch (ip_rev) {
148 case OMAP_I2C_REV_V1:
149 return reg_map_ip_v1;
150 case OMAP_I2C_REV_V2:
151 /* Fall through... */
152 default:
153 return reg_map_ip_v2;
154 }
155 }
156
omap_i2c_write_reg(void __iomem * base,int ip_rev,u16 val,int reg)157 static inline void omap_i2c_write_reg(void __iomem *base, int ip_rev,
158 u16 val, int reg)
159 {
160 writew(val, base + omap_i2c_get_ip_reg_map(ip_rev)[reg]);
161 }
162
omap_i2c_read_reg(void __iomem * base,int ip_rev,int reg)163 static inline u16 omap_i2c_read_reg(void __iomem *base, int ip_rev, int reg)
164 {
165 return readw(base + omap_i2c_get_ip_reg_map(ip_rev)[reg]);
166 }
167
omap24_i2c_findpsc(u32 * pscl,u32 * psch,uint speed)168 static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
169 {
170 unsigned long internal_clk = 0, fclk;
171 unsigned int prescaler;
172
173 /*
174 * This method is only called for Standard and Fast Mode speeds
175 *
176 * For some TI SoCs it is explicitly written in TRM (e,g, SPRUHZ6G,
177 * page 5685, Table 24-7)
178 * that the internal I2C clock (after prescaler) should be between
179 * 7-12 MHz (at least for Fast Mode (FS)).
180 *
181 * Such approach is used in v4.9 Linux kernel in:
182 * ./drivers/i2c/busses/i2c-omap.c (omap_i2c_init function).
183 */
184
185 speed /= 1000; /* convert speed to kHz */
186
187 if (speed > 100)
188 internal_clk = 9600;
189 else
190 internal_clk = 4000;
191
192 fclk = I2C_IP_CLK / 1000;
193 prescaler = fclk / internal_clk;
194 prescaler = prescaler - 1;
195
196 if (speed > 100) {
197 unsigned long scl;
198
199 /* Fast mode */
200 scl = internal_clk / speed;
201 *pscl = scl - (scl / 3) - I2C_FASTSPEED_SCLL_TRIM;
202 *psch = (scl / 3) - I2C_FASTSPEED_SCLH_TRIM;
203 } else {
204 /* Standard mode */
205 *pscl = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLL_TRIM;
206 *psch = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLH_TRIM;
207 }
208
209 debug("%s: speed [kHz]: %d psc: 0x%x sscl: 0x%x ssch: 0x%x\n",
210 __func__, speed, prescaler, *pscl, *psch);
211
212 if (*pscl <= 0 || *psch <= 0 || prescaler <= 0)
213 return -EINVAL;
214
215 return prescaler;
216 }
217
218 /*
219 * Wait for the bus to be free by checking the Bus Busy (BB)
220 * bit to become clear
221 */
wait_for_bb(void __iomem * i2c_base,int ip_rev,int waitdelay)222 static int wait_for_bb(void __iomem *i2c_base, int ip_rev, int waitdelay)
223 {
224 int timeout = I2C_TIMEOUT;
225 int irq_stat_reg;
226 u16 stat;
227
228 irq_stat_reg = (ip_rev == OMAP_I2C_REV_V1) ?
229 OMAP_I2C_STAT_REG : OMAP_I2C_IP_V2_IRQSTATUS_RAW;
230
231 /* clear current interrupts */
232 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
233
234 while ((stat = omap_i2c_read_reg(i2c_base, ip_rev, irq_stat_reg) &
235 I2C_STAT_BB) && timeout--) {
236 omap_i2c_write_reg(i2c_base, ip_rev, stat, OMAP_I2C_STAT_REG);
237 udelay(waitdelay);
238 }
239
240 if (timeout <= 0) {
241 printf("Timed out in %s: status=%04x\n", __func__, stat);
242 return 1;
243 }
244
245 /* clear delayed stuff */
246 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
247 return 0;
248 }
249
250 /*
251 * Wait for the I2C controller to complete current action
252 * and update status
253 */
wait_for_event(void __iomem * i2c_base,int ip_rev,int waitdelay)254 static u16 wait_for_event(void __iomem *i2c_base, int ip_rev, int waitdelay)
255 {
256 u16 status;
257 int timeout = I2C_TIMEOUT;
258 int irq_stat_reg;
259
260 irq_stat_reg = (ip_rev == OMAP_I2C_REV_V1) ?
261 OMAP_I2C_STAT_REG : OMAP_I2C_IP_V2_IRQSTATUS_RAW;
262 do {
263 udelay(waitdelay);
264 status = omap_i2c_read_reg(i2c_base, ip_rev, irq_stat_reg);
265 } while (!(status &
266 (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
267 I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
268 I2C_STAT_AL)) && timeout--);
269
270 if (timeout <= 0) {
271 printf("Timed out in %s: status=%04x\n", __func__, status);
272 /*
273 * If status is still 0 here, probably the bus pads have
274 * not been configured for I2C, and/or pull-ups are missing.
275 */
276 printf("Check if pads/pull-ups of bus are properly configured\n");
277 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
278 status = 0;
279 }
280
281 return status;
282 }
283
flush_fifo(void __iomem * i2c_base,int ip_rev)284 static void flush_fifo(void __iomem *i2c_base, int ip_rev)
285 {
286 u16 stat;
287
288 /*
289 * note: if you try and read data when its not there or ready
290 * you get a bus error
291 */
292 while (1) {
293 stat = omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_STAT_REG);
294 if (stat == I2C_STAT_RRDY) {
295 omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_DATA_REG);
296 omap_i2c_write_reg(i2c_base, ip_rev,
297 I2C_STAT_RRDY, OMAP_I2C_STAT_REG);
298 udelay(1000);
299 } else
300 break;
301 }
302 }
303
__omap24_i2c_setspeed(void __iomem * i2c_base,int ip_rev,uint speed,int * waitdelay)304 static int __omap24_i2c_setspeed(void __iomem *i2c_base, int ip_rev, uint speed,
305 int *waitdelay)
306 {
307 int psc, fsscll = 0, fssclh = 0;
308 int hsscll = 0, hssclh = 0;
309 u32 scll = 0, sclh = 0;
310
311 if (speed >= I2C_SPEED_HIGH_RATE) {
312 /* High speed */
313 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
314 psc -= 1;
315 if (psc < I2C_PSC_MIN) {
316 printf("Error : I2C unsupported prescaler %d\n", psc);
317 return -1;
318 }
319
320 /* For first phase of HS mode */
321 fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
322
323 fssclh = fsscll;
324
325 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
326 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
327 if (((fsscll < 0) || (fssclh < 0)) ||
328 ((fsscll > 255) || (fssclh > 255))) {
329 puts("Error : I2C initializing first phase clock\n");
330 return -1;
331 }
332
333 /* For second phase of HS mode */
334 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
335
336 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
337 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
338 if (((fsscll < 0) || (fssclh < 0)) ||
339 ((fsscll > 255) || (fssclh > 255))) {
340 puts("Error : I2C initializing second phase clock\n");
341 return -1;
342 }
343
344 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
345 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
346
347 } else {
348 /* Standard and fast speed */
349 psc = omap24_i2c_findpsc(&scll, &sclh, speed);
350 if (0 > psc) {
351 puts("Error : I2C initializing clock\n");
352 return -1;
353 }
354 }
355
356 /* wait for 20 clkperiods */
357 *waitdelay = (10000000 / speed) * 2;
358
359 omap_i2c_write_reg(i2c_base, ip_rev, 0, OMAP_I2C_CON_REG);
360 omap_i2c_write_reg(i2c_base, ip_rev, psc, OMAP_I2C_PSC_REG);
361 omap_i2c_write_reg(i2c_base, ip_rev, scll, OMAP_I2C_SCLL_REG);
362 omap_i2c_write_reg(i2c_base, ip_rev, sclh, OMAP_I2C_SCLH_REG);
363 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN, OMAP_I2C_CON_REG);
364
365 /* clear all pending status */
366 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
367
368 return 0;
369 }
370
omap24_i2c_deblock(void __iomem * i2c_base,int ip_rev)371 static void omap24_i2c_deblock(void __iomem *i2c_base, int ip_rev)
372 {
373 int i;
374 u16 systest;
375 u16 orgsystest;
376
377 /* set test mode ST_EN = 1 */
378 orgsystest = omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_SYSTEST_REG);
379 systest = orgsystest;
380
381 /* enable testmode */
382 systest |= I2C_SYSTEST_ST_EN;
383 omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
384 systest &= ~I2C_SYSTEST_TMODE_MASK;
385 systest |= 3 << I2C_SYSTEST_TMODE_SHIFT;
386 omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
387
388 /* set SCL, SDA = 1 */
389 systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
390 omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
391 udelay(10);
392
393 /* toggle scl 9 clocks */
394 for (i = 0; i < 9; i++) {
395 /* SCL = 0 */
396 systest &= ~I2C_SYSTEST_SCL_O;
397 omap_i2c_write_reg(i2c_base, ip_rev,
398 systest, OMAP_I2C_SYSTEST_REG);
399 udelay(10);
400 /* SCL = 1 */
401 systest |= I2C_SYSTEST_SCL_O;
402 omap_i2c_write_reg(i2c_base, ip_rev,
403 systest, OMAP_I2C_SYSTEST_REG);
404 udelay(10);
405 }
406
407 /* send stop */
408 systest &= ~I2C_SYSTEST_SDA_O;
409 omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
410 udelay(10);
411 systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
412 omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
413 udelay(10);
414
415 /* restore original mode */
416 omap_i2c_write_reg(i2c_base, ip_rev, orgsystest, OMAP_I2C_SYSTEST_REG);
417 }
418
__omap24_i2c_init(void __iomem * i2c_base,int ip_rev,int speed,int slaveadd,int * waitdelay)419 static void __omap24_i2c_init(void __iomem *i2c_base, int ip_rev, int speed,
420 int slaveadd, int *waitdelay)
421 {
422 int timeout = I2C_TIMEOUT;
423 int deblock = 1;
424
425 retry:
426 if (omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_CON_REG) &
427 I2C_CON_EN) {
428 omap_i2c_write_reg(i2c_base, ip_rev, 0, OMAP_I2C_CON_REG);
429 udelay(50000);
430 }
431
432 /* for ES2 after soft reset */
433 omap_i2c_write_reg(i2c_base, ip_rev, 0x2, OMAP_I2C_SYSC_REG);
434 udelay(1000);
435
436 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN, OMAP_I2C_CON_REG);
437 while (!(omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_SYSS_REG) &
438 I2C_SYSS_RDONE) && timeout--) {
439 if (timeout <= 0) {
440 puts("ERROR: Timeout in soft-reset\n");
441 return;
442 }
443 udelay(1000);
444 }
445
446 if (__omap24_i2c_setspeed(i2c_base, ip_rev, speed, waitdelay)) {
447 printf("ERROR: failed to setup I2C bus-speed!\n");
448 return;
449 }
450
451 /* own address */
452 omap_i2c_write_reg(i2c_base, ip_rev, slaveadd, OMAP_I2C_OA_REG);
453
454 if (ip_rev == OMAP_I2C_REV_V1) {
455 /*
456 * Have to enable interrupts for OMAP2/3, these IPs don't have
457 * an 'irqstatus_raw' register and we shall have to poll 'stat'
458 */
459 omap_i2c_write_reg(i2c_base, ip_rev, I2C_IE_XRDY_IE |
460 I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
461 I2C_IE_NACK_IE | I2C_IE_AL_IE,
462 OMAP_I2C_IE_REG);
463 }
464
465 udelay(1000);
466 flush_fifo(i2c_base, ip_rev);
467 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
468
469 /* Handle possible failed I2C state */
470 if (wait_for_bb(i2c_base, ip_rev, *waitdelay))
471 if (deblock == 1) {
472 omap24_i2c_deblock(i2c_base, ip_rev);
473 deblock = 0;
474 goto retry;
475 }
476 }
477
478 /*
479 * i2c_probe: Use write access. Allows to identify addresses that are
480 * write-only (like the config register of dual-port EEPROMs)
481 */
__omap24_i2c_probe(void __iomem * i2c_base,int ip_rev,int waitdelay,uchar chip)482 static int __omap24_i2c_probe(void __iomem *i2c_base, int ip_rev, int waitdelay,
483 uchar chip)
484 {
485 u16 status;
486 int res = 1; /* default = fail */
487
488 if (chip == omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_OA_REG))
489 return res;
490
491 /* Wait until bus is free */
492 if (wait_for_bb(i2c_base, ip_rev, waitdelay))
493 return res;
494
495 /* No data transfer, slave addr only */
496 omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG);
497
498 /* Stop bit needed here */
499 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
500 I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP,
501 OMAP_I2C_CON_REG);
502
503 status = wait_for_event(i2c_base, ip_rev, waitdelay);
504
505 if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
506 /*
507 * With current high-level command implementation, notifying
508 * the user shall flood the console with 127 messages. If
509 * silent exit is desired upon unconfigured bus, remove the
510 * following 'if' section:
511 */
512 if (status == I2C_STAT_XRDY)
513 printf("i2c_probe: pads on bus probably not configured (status=0x%x)\n",
514 status);
515
516 goto pr_exit;
517 }
518
519 /* Check for ACK (!NAK) */
520 if (!(status & I2C_STAT_NACK)) {
521 res = 0; /* Device found */
522 udelay(waitdelay);/* Required by AM335X in SPL */
523 /* Abort transfer (force idle state) */
524 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_MST | I2C_CON_TRX,
525 OMAP_I2C_CON_REG); /* Reset */
526 udelay(1000);
527 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
528 I2C_CON_TRX | I2C_CON_STP,
529 OMAP_I2C_CON_REG); /* STP */
530 }
531
532 pr_exit:
533 flush_fifo(i2c_base, ip_rev);
534 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
535 return res;
536 }
537
538 /*
539 * i2c_read: Function now uses a single I2C read transaction with bulk transfer
540 * of the requested number of bytes (note that the 'i2c md' command
541 * limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is
542 * defined in the board config header, this transaction shall be with
543 * Repeated Start (Sr) between the address and data phases; otherwise
544 * Stop-Start (P-S) shall be used (some I2C chips do require a P-S).
545 * The address (reg offset) may be 0, 1 or 2 bytes long.
546 * Function now reads correctly from chips that return more than one
547 * byte of data per addressed register (like TI temperature sensors),
548 * or that do not need a register address at all (such as some clock
549 * distributors).
550 */
__omap24_i2c_read(void __iomem * i2c_base,int ip_rev,int waitdelay,uchar chip,uint addr,int alen,uchar * buffer,int len)551 static int __omap24_i2c_read(void __iomem *i2c_base, int ip_rev, int waitdelay,
552 uchar chip, uint addr, int alen, uchar *buffer,
553 int len)
554 {
555 int i2c_error = 0;
556 u16 status;
557
558 if (alen < 0) {
559 puts("I2C read: addr len < 0\n");
560 return 1;
561 }
562
563 if (len < 0) {
564 puts("I2C read: data len < 0\n");
565 return 1;
566 }
567
568 if (buffer == NULL) {
569 puts("I2C read: NULL pointer passed\n");
570 return 1;
571 }
572
573 if (alen > 2) {
574 printf("I2C read: addr len %d not supported\n", alen);
575 return 1;
576 }
577
578 if (addr + len > (1 << 16)) {
579 puts("I2C read: address out of range\n");
580 return 1;
581 }
582
583 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
584 /*
585 * EEPROM chips that implement "address overflow" are ones
586 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
587 * address and the extra bits end up in the "chip address"
588 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
589 * four 256 byte chips.
590 *
591 * Note that we consider the length of the address field to
592 * still be one byte because the extra address bits are
593 * hidden in the chip address.
594 */
595 if (alen > 0)
596 chip |= ((addr >> (alen * 8)) &
597 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
598 #endif
599
600 /* Wait until bus not busy */
601 if (wait_for_bb(i2c_base, ip_rev, waitdelay))
602 return 1;
603
604 /* Zero, one or two bytes reg address (offset) */
605 omap_i2c_write_reg(i2c_base, ip_rev, alen, OMAP_I2C_CNT_REG);
606 /* Set slave address */
607 omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG);
608
609 if (alen) {
610 /* Must write reg offset first */
611 #ifdef CONFIG_I2C_REPEATED_START
612 /* No stop bit, use Repeated Start (Sr) */
613 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
614 I2C_CON_STT | I2C_CON_TRX, OMAP_I2C_CON_REG);
615 #else
616 /* Stop - Start (P-S) */
617 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
618 I2C_CON_STT | I2C_CON_STP | I2C_CON_TRX,
619 OMAP_I2C_CON_REG);
620 #endif
621 /* Send register offset */
622 while (1) {
623 status = wait_for_event(i2c_base, ip_rev, waitdelay);
624 /* Try to identify bus that is not padconf'd for I2C */
625 if (status == I2C_STAT_XRDY) {
626 i2c_error = 2;
627 printf("i2c_read (addr phase): pads on bus probably not configured (status=0x%x)\n",
628 status);
629 goto rd_exit;
630 }
631 if (status == 0 || (status & I2C_STAT_NACK)) {
632 i2c_error = 1;
633 printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
634 status);
635 goto rd_exit;
636 }
637 if (alen) {
638 if (status & I2C_STAT_XRDY) {
639 u8 addr_byte;
640 alen--;
641 addr_byte = (addr >> (8 * alen)) & 0xff;
642 omap_i2c_write_reg(i2c_base, ip_rev,
643 addr_byte,
644 OMAP_I2C_DATA_REG);
645 omap_i2c_write_reg(i2c_base, ip_rev,
646 I2C_STAT_XRDY,
647 OMAP_I2C_STAT_REG);
648 }
649 }
650 if (status & I2C_STAT_ARDY) {
651 omap_i2c_write_reg(i2c_base, ip_rev,
652 I2C_STAT_ARDY,
653 OMAP_I2C_STAT_REG);
654 break;
655 }
656 }
657 }
658
659 /* Set slave address */
660 omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG);
661 /* Read len bytes from slave */
662 omap_i2c_write_reg(i2c_base, ip_rev, len, OMAP_I2C_CNT_REG);
663 /* Need stop bit here */
664 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
665 I2C_CON_STT | I2C_CON_STP, OMAP_I2C_CON_REG);
666
667 /* Receive data */
668 while (1) {
669 status = wait_for_event(i2c_base, ip_rev, waitdelay);
670 /*
671 * Try to identify bus that is not padconf'd for I2C. This
672 * state could be left over from previous transactions if
673 * the address phase is skipped due to alen=0.
674 */
675 if (status == I2C_STAT_XRDY) {
676 i2c_error = 2;
677 printf("i2c_read (data phase): pads on bus probably not configured (status=0x%x)\n",
678 status);
679 goto rd_exit;
680 }
681 if (status == 0 || (status & I2C_STAT_NACK)) {
682 i2c_error = 1;
683 goto rd_exit;
684 }
685 if (status & I2C_STAT_RRDY) {
686 *buffer++ = omap_i2c_read_reg(i2c_base, ip_rev,
687 OMAP_I2C_DATA_REG);
688 omap_i2c_write_reg(i2c_base, ip_rev,
689 I2C_STAT_RRDY, OMAP_I2C_STAT_REG);
690 }
691 if (status & I2C_STAT_ARDY) {
692 omap_i2c_write_reg(i2c_base, ip_rev,
693 I2C_STAT_ARDY, OMAP_I2C_STAT_REG);
694 break;
695 }
696 }
697
698 rd_exit:
699 flush_fifo(i2c_base, ip_rev);
700 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
701 return i2c_error;
702 }
703
704 /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
__omap24_i2c_write(void __iomem * i2c_base,int ip_rev,int waitdelay,uchar chip,uint addr,int alen,uchar * buffer,int len)705 static int __omap24_i2c_write(void __iomem *i2c_base, int ip_rev, int waitdelay,
706 uchar chip, uint addr, int alen, uchar *buffer,
707 int len)
708 {
709 int i;
710 u16 status;
711 int i2c_error = 0;
712 int timeout = I2C_TIMEOUT;
713
714 if (alen < 0) {
715 puts("I2C write: addr len < 0\n");
716 return 1;
717 }
718
719 if (len < 0) {
720 puts("I2C write: data len < 0\n");
721 return 1;
722 }
723
724 if (buffer == NULL) {
725 puts("I2C write: NULL pointer passed\n");
726 return 1;
727 }
728
729 if (alen > 2) {
730 printf("I2C write: addr len %d not supported\n", alen);
731 return 1;
732 }
733
734 if (addr + len > (1 << 16)) {
735 printf("I2C write: address 0x%x + 0x%x out of range\n",
736 addr, len);
737 return 1;
738 }
739
740 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
741 /*
742 * EEPROM chips that implement "address overflow" are ones
743 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
744 * address and the extra bits end up in the "chip address"
745 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
746 * four 256 byte chips.
747 *
748 * Note that we consider the length of the address field to
749 * still be one byte because the extra address bits are
750 * hidden in the chip address.
751 */
752 if (alen > 0)
753 chip |= ((addr >> (alen * 8)) &
754 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
755 #endif
756
757 /* Wait until bus not busy */
758 if (wait_for_bb(i2c_base, ip_rev, waitdelay))
759 return 1;
760
761 /* Start address phase - will write regoffset + len bytes data */
762 omap_i2c_write_reg(i2c_base, ip_rev, alen + len, OMAP_I2C_CNT_REG);
763 /* Set slave address */
764 omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG);
765 /* Stop bit needed here */
766 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
767 I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP,
768 OMAP_I2C_CON_REG);
769
770 while (alen) {
771 /* Must write reg offset (one or two bytes) */
772 status = wait_for_event(i2c_base, ip_rev, waitdelay);
773 /* Try to identify bus that is not padconf'd for I2C */
774 if (status == I2C_STAT_XRDY) {
775 i2c_error = 2;
776 printf("i2c_write: pads on bus probably not configured (status=0x%x)\n",
777 status);
778 goto wr_exit;
779 }
780 if (status == 0 || (status & I2C_STAT_NACK)) {
781 i2c_error = 1;
782 printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
783 status);
784 goto wr_exit;
785 }
786 if (status & I2C_STAT_XRDY) {
787 alen--;
788 omap_i2c_write_reg(i2c_base, ip_rev,
789 (addr >> (8 * alen)) & 0xff,
790 OMAP_I2C_DATA_REG);
791 omap_i2c_write_reg(i2c_base, ip_rev,
792 I2C_STAT_XRDY, OMAP_I2C_STAT_REG);
793 } else {
794 i2c_error = 1;
795 printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n",
796 status);
797 goto wr_exit;
798 }
799 }
800
801 /* Address phase is over, now write data */
802 for (i = 0; i < len; i++) {
803 status = wait_for_event(i2c_base, ip_rev, waitdelay);
804 if (status == 0 || (status & I2C_STAT_NACK)) {
805 i2c_error = 1;
806 printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
807 status);
808 goto wr_exit;
809 }
810 if (status & I2C_STAT_XRDY) {
811 omap_i2c_write_reg(i2c_base, ip_rev,
812 buffer[i], OMAP_I2C_DATA_REG);
813 omap_i2c_write_reg(i2c_base, ip_rev,
814 I2C_STAT_XRDY, OMAP_I2C_STAT_REG);
815 } else {
816 i2c_error = 1;
817 printf("i2c_write: bus not ready for data Tx (i=%d)\n",
818 i);
819 goto wr_exit;
820 }
821 }
822
823 /*
824 * poll ARDY bit for making sure that last byte really has been
825 * transferred on the bus.
826 */
827 do {
828 status = wait_for_event(i2c_base, ip_rev, waitdelay);
829 } while (!(status & I2C_STAT_ARDY) && timeout--);
830 if (timeout <= 0)
831 printf("i2c_write: timed out writig last byte!\n");
832
833 wr_exit:
834 flush_fifo(i2c_base, ip_rev);
835 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
836 return i2c_error;
837 }
838
839 #if !CONFIG_IS_ENABLED(DM_I2C)
840 /*
841 * The legacy I2C functions. These need to get removed once
842 * all users of this driver are converted to DM.
843 */
omap24_get_base(struct i2c_adapter * adap)844 static void __iomem *omap24_get_base(struct i2c_adapter *adap)
845 {
846 switch (adap->hwadapnr) {
847 case 0:
848 return (void __iomem *)I2C_BASE1;
849 break;
850 case 1:
851 return (void __iomem *)I2C_BASE2;
852 break;
853 #if (CONFIG_SYS_I2C_BUS_MAX > 2)
854 case 2:
855 return (void __iomem *)I2C_BASE3;
856 break;
857 #if (CONFIG_SYS_I2C_BUS_MAX > 3)
858 case 3:
859 return (void __iomem *)I2C_BASE4;
860 break;
861 #if (CONFIG_SYS_I2C_BUS_MAX > 4)
862 case 4:
863 return (void __iomem *)I2C_BASE5;
864 break;
865 #endif
866 #endif
867 #endif
868 default:
869 printf("wrong hwadapnr: %d\n", adap->hwadapnr);
870 break;
871 }
872
873 return NULL;
874 }
875
omap24_get_ip_rev(void)876 static int omap24_get_ip_rev(void)
877 {
878 #ifdef CONFIG_OMAP34XX
879 return OMAP_I2C_REV_V1;
880 #else
881 return OMAP_I2C_REV_V2;
882 #endif
883 }
884
omap24_i2c_read(struct i2c_adapter * adap,uchar chip,uint addr,int alen,uchar * buffer,int len)885 static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
886 int alen, uchar *buffer, int len)
887 {
888 void __iomem *i2c_base = omap24_get_base(adap);
889 int ip_rev = omap24_get_ip_rev();
890
891 return __omap24_i2c_read(i2c_base, ip_rev, adap->waitdelay, chip, addr,
892 alen, buffer, len);
893 }
894
omap24_i2c_write(struct i2c_adapter * adap,uchar chip,uint addr,int alen,uchar * buffer,int len)895 static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
896 int alen, uchar *buffer, int len)
897 {
898 void __iomem *i2c_base = omap24_get_base(adap);
899 int ip_rev = omap24_get_ip_rev();
900
901 return __omap24_i2c_write(i2c_base, ip_rev, adap->waitdelay, chip, addr,
902 alen, buffer, len);
903 }
904
omap24_i2c_setspeed(struct i2c_adapter * adap,uint speed)905 static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
906 {
907 void __iomem *i2c_base = omap24_get_base(adap);
908 int ip_rev = omap24_get_ip_rev();
909 int ret;
910
911 ret = __omap24_i2c_setspeed(i2c_base, ip_rev, speed, &adap->waitdelay);
912 if (ret) {
913 pr_err("%s: set i2c speed failed\n", __func__);
914 return ret;
915 }
916
917 adap->speed = speed;
918
919 return 0;
920 }
921
omap24_i2c_init(struct i2c_adapter * adap,int speed,int slaveadd)922 static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
923 {
924 void __iomem *i2c_base = omap24_get_base(adap);
925 int ip_rev = omap24_get_ip_rev();
926
927 return __omap24_i2c_init(i2c_base, ip_rev, speed, slaveadd,
928 &adap->waitdelay);
929 }
930
omap24_i2c_probe(struct i2c_adapter * adap,uchar chip)931 static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
932 {
933 void __iomem *i2c_base = omap24_get_base(adap);
934 int ip_rev = omap24_get_ip_rev();
935
936 return __omap24_i2c_probe(i2c_base, ip_rev, adap->waitdelay, chip);
937 }
938
939 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
940 #define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
941 #endif
942 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
943 #define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
944 #endif
945
946 U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
947 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
948 CONFIG_SYS_OMAP24_I2C_SPEED,
949 CONFIG_SYS_OMAP24_I2C_SLAVE,
950 0)
951 U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
952 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
953 CONFIG_SYS_OMAP24_I2C_SPEED1,
954 CONFIG_SYS_OMAP24_I2C_SLAVE1,
955 1)
956
957 #if (CONFIG_SYS_I2C_BUS_MAX > 2)
958 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
959 #define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
960 #endif
961 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
962 #define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
963 #endif
964
965 U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
966 omap24_i2c_read, omap24_i2c_write, NULL,
967 CONFIG_SYS_OMAP24_I2C_SPEED2,
968 CONFIG_SYS_OMAP24_I2C_SLAVE2,
969 2)
970 #if (CONFIG_SYS_I2C_BUS_MAX > 3)
971 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
972 #define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
973 #endif
974 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
975 #define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
976 #endif
977
978 U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
979 omap24_i2c_read, omap24_i2c_write, NULL,
980 CONFIG_SYS_OMAP24_I2C_SPEED3,
981 CONFIG_SYS_OMAP24_I2C_SLAVE3,
982 3)
983 #if (CONFIG_SYS_I2C_BUS_MAX > 4)
984 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
985 #define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
986 #endif
987 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
988 #define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
989 #endif
990
991 U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
992 omap24_i2c_read, omap24_i2c_write, NULL,
993 CONFIG_SYS_OMAP24_I2C_SPEED4,
994 CONFIG_SYS_OMAP24_I2C_SLAVE4,
995 4)
996 #endif
997 #endif
998 #endif
999
1000 #else /* CONFIG_DM_I2C */
1001
1002 static int omap_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
1003 {
1004 struct omap_i2c *priv = dev_get_priv(bus);
1005 int ret;
1006
1007 debug("i2c_xfer: %d messages\n", nmsgs);
1008 for (; nmsgs > 0; nmsgs--, msg++) {
1009 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
1010 if (msg->flags & I2C_M_RD) {
1011 ret = __omap24_i2c_read(priv->regs, priv->ip_rev,
1012 priv->waitdelay,
1013 msg->addr, 0, 0, msg->buf,
1014 msg->len);
1015 } else {
1016 ret = __omap24_i2c_write(priv->regs, priv->ip_rev,
1017 priv->waitdelay,
1018 msg->addr, 0, 0, msg->buf,
1019 msg->len);
1020 }
1021 if (ret) {
1022 debug("i2c_write: error sending\n");
1023 return -EREMOTEIO;
1024 }
1025 }
1026
1027 return 0;
1028 }
1029
1030 static int omap_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
1031 {
1032 struct omap_i2c *priv = dev_get_priv(bus);
1033
1034 priv->speed = speed;
1035
1036 return __omap24_i2c_setspeed(priv->regs, priv->ip_rev, speed,
1037 &priv->waitdelay);
1038 }
1039
1040 static int omap_i2c_probe_chip(struct udevice *bus, uint chip_addr,
1041 uint chip_flags)
1042 {
1043 struct omap_i2c *priv = dev_get_priv(bus);
1044
1045 return __omap24_i2c_probe(priv->regs, priv->ip_rev, priv->waitdelay,
1046 chip_addr);
1047 }
1048
1049 static int omap_i2c_probe(struct udevice *bus)
1050 {
1051 struct omap_i2c *priv = dev_get_priv(bus);
1052 struct omap_i2c_plat *plat = dev_get_plat(bus);
1053
1054 priv->speed = plat->speed;
1055 priv->regs = map_physmem(plat->base, sizeof(void *),
1056 MAP_NOCACHE);
1057 priv->ip_rev = plat->ip_rev;
1058
1059 __omap24_i2c_init(priv->regs, priv->ip_rev, priv->speed, 0,
1060 &priv->waitdelay);
1061
1062 return 0;
1063 }
1064
1065 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1066 static int omap_i2c_of_to_plat(struct udevice *bus)
1067 {
1068 struct omap_i2c_plat *plat = dev_get_plat(bus);
1069
1070 plat->base = dev_read_addr(bus);
1071 plat->speed = dev_read_u32_default(bus, "clock-frequency",
1072 I2C_SPEED_STANDARD_RATE);
1073 plat->ip_rev = dev_get_driver_data(bus);
1074
1075 return 0;
1076 }
1077
1078 static const struct udevice_id omap_i2c_ids[] = {
1079 { .compatible = "ti,omap3-i2c", .data = OMAP_I2C_REV_V1 },
1080 { .compatible = "ti,omap4-i2c", .data = OMAP_I2C_REV_V2 },
1081 { }
1082 };
1083 #endif
1084
1085 static const struct dm_i2c_ops omap_i2c_ops = {
1086 .xfer = omap_i2c_xfer,
1087 .probe_chip = omap_i2c_probe_chip,
1088 .set_bus_speed = omap_i2c_set_bus_speed,
1089 };
1090
1091 U_BOOT_DRIVER(i2c_omap) = {
1092 .name = "i2c_omap",
1093 .id = UCLASS_I2C,
1094 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
1095 .of_match = omap_i2c_ids,
1096 .of_to_plat = omap_i2c_of_to_plat,
1097 .plat_auto = sizeof(struct omap_i2c_plat),
1098 #endif
1099 .probe = omap_i2c_probe,
1100 .priv_auto = sizeof(struct omap_i2c),
1101 .ops = &omap_i2c_ops,
1102 #if !CONFIG_IS_ENABLED(OF_CONTROL)
1103 .flags = DM_FLAG_PRE_RELOC,
1104 #endif
1105 };
1106
1107 #endif /* CONFIG_DM_I2C */
1108