1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2012
4 * Konstantin Kozhevnikov, Cogent Embedded
5 *
6 * based on nand_spl_simple code
7 *
8 * (C) Copyright 2006-2008
9 * Stefan Roese, DENX Software Engineering, sr@denx.de.
10 */
11
12 #include <common.h>
13 #include <nand.h>
14 #include <asm/io.h>
15 #include <linux/delay.h>
16 #include <linux/mtd/nand_ecc.h>
17
18 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
19 static struct mtd_info *mtd;
20 static struct nand_chip nand_chip;
21
22 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
23 CONFIG_SYS_NAND_ECCSIZE)
24 #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
25
26
27 /*
28 * NAND command for large page NAND devices (2k)
29 */
nand_command(int block,int page,uint32_t offs,u8 cmd)30 static int nand_command(int block, int page, uint32_t offs,
31 u8 cmd)
32 {
33 struct nand_chip *this = mtd_to_nand(mtd);
34 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
35 void (*hwctrl)(struct mtd_info *mtd, int cmd,
36 unsigned int ctrl) = this->cmd_ctrl;
37
38 while (!this->dev_ready(mtd))
39 ;
40
41 /* Emulate NAND_CMD_READOOB */
42 if (cmd == NAND_CMD_READOOB) {
43 offs += CONFIG_SYS_NAND_PAGE_SIZE;
44 cmd = NAND_CMD_READ0;
45 }
46
47 /* Begin command latch cycle */
48 hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
49
50 if (cmd == NAND_CMD_RESET) {
51 hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
52
53 /*
54 * Apply this short delay always to ensure that we do wait
55 * tWB in any case on any machine.
56 */
57 ndelay(150);
58
59 while (!this->dev_ready(mtd))
60 ;
61 return 0;
62 }
63
64 /* Shift the offset from byte addressing to word addressing. */
65 if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
66 offs >>= 1;
67
68 /* Set ALE and clear CLE to start address cycle */
69 /* Column address */
70 hwctrl(mtd, offs & 0xff,
71 NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
72 hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
73 /* Row address */
74 if (cmd != NAND_CMD_RNDOUT) {
75 hwctrl(mtd, (page_addr & 0xff),
76 NAND_CTRL_ALE); /* A[19:12] */
77 hwctrl(mtd, ((page_addr >> 8) & 0xff),
78 NAND_CTRL_ALE); /* A[27:20] */
79 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
80 /* One more address cycle for devices > 128MiB */
81 hwctrl(mtd, (page_addr >> 16) & 0x0f,
82 NAND_CTRL_ALE); /* A[31:28] */
83 #endif
84 }
85
86 hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
87
88
89 /*
90 * Program and erase have their own busy handlers status, sequential
91 * in and status need no delay.
92 */
93 switch (cmd) {
94 case NAND_CMD_CACHEDPROG:
95 case NAND_CMD_PAGEPROG:
96 case NAND_CMD_ERASE1:
97 case NAND_CMD_ERASE2:
98 case NAND_CMD_SEQIN:
99 case NAND_CMD_RNDIN:
100 case NAND_CMD_STATUS:
101 return 0;
102
103 case NAND_CMD_RNDOUT:
104 /* No ready / busy check necessary */
105 hwctrl(mtd, NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
106 NAND_CTRL_CHANGE);
107 hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
108 return 0;
109
110 case NAND_CMD_READ0:
111 /* Latch in address */
112 hwctrl(mtd, NAND_CMD_READSTART,
113 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
114 hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
115 }
116
117 /*
118 * Apply this short delay always to ensure that we do wait tWB in
119 * any case on any machine.
120 */
121 ndelay(150);
122
123 while (!this->dev_ready(mtd))
124 ;
125
126 return 0;
127 }
128
nand_is_bad_block(int block)129 static int nand_is_bad_block(int block)
130 {
131 struct nand_chip *this = mtd_to_nand(mtd);
132
133 nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
134 NAND_CMD_READOOB);
135
136 /*
137 * Read one byte (or two if it's a 16 bit chip).
138 */
139 if (this->options & NAND_BUSWIDTH_16) {
140 if (readw(this->IO_ADDR_R) != 0xffff)
141 return 1;
142 } else {
143 if (readb(this->IO_ADDR_R) != 0xff)
144 return 1;
145 }
146
147 return 0;
148 }
149
nand_read_page(int block,int page,void * dst)150 static int nand_read_page(int block, int page, void *dst)
151 {
152 struct nand_chip *this = mtd_to_nand(mtd);
153 u_char ecc_calc[ECCTOTAL];
154 u_char ecc_code[ECCTOTAL];
155 u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
156 int i;
157 int eccsize = CONFIG_SYS_NAND_ECCSIZE;
158 int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
159 int eccsteps = ECCSTEPS;
160 uint8_t *p = dst;
161 uint32_t data_pos = 0;
162 uint8_t *oob = &oob_data[0] + nand_ecc_pos[0];
163 uint32_t oob_pos = eccsize * eccsteps + nand_ecc_pos[0];
164
165 nand_command(block, page, 0, NAND_CMD_READ0);
166
167 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
168 this->ecc.hwctl(mtd, NAND_ECC_READ);
169 nand_command(block, page, data_pos, NAND_CMD_RNDOUT);
170
171 this->read_buf(mtd, p, eccsize);
172
173 nand_command(block, page, oob_pos, NAND_CMD_RNDOUT);
174
175 this->read_buf(mtd, oob, eccbytes);
176 this->ecc.calculate(mtd, p, &ecc_calc[i]);
177
178 data_pos += eccsize;
179 oob_pos += eccbytes;
180 oob += eccbytes;
181 }
182
183 /* Pick the ECC bytes out of the oob data */
184 for (i = 0; i < ECCTOTAL; i++)
185 ecc_code[i] = oob_data[nand_ecc_pos[i]];
186
187 eccsteps = ECCSTEPS;
188 p = dst;
189
190 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
191 /* No chance to do something with the possible error message
192 * from correct_data(). We just hope that all possible errors
193 * are corrected by this routine.
194 */
195 this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
196 }
197
198 return 0;
199 }
200
201 /* nand_init() - initialize data to make nand usable by SPL */
nand_init(void)202 void nand_init(void)
203 {
204 /*
205 * Init board specific nand support
206 */
207 mtd = nand_to_mtd(&nand_chip);
208 nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
209 (void __iomem *)CONFIG_SYS_NAND_BASE;
210 board_nand_init(&nand_chip);
211
212 if (nand_chip.select_chip)
213 nand_chip.select_chip(mtd, 0);
214
215 /* NAND chip may require reset after power-on */
216 nand_command(0, 0, 0, NAND_CMD_RESET);
217 }
218
219 /* Unselect after operation */
nand_deselect(void)220 void nand_deselect(void)
221 {
222 if (nand_chip.select_chip)
223 nand_chip.select_chip(mtd, -1);
224 }
225
226 #include "nand_spl_loaders.c"
227