1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017, 2020-2021 NXP 4 */ 5 6 #ifndef __LS1088A_QDS_H 7 #define __LS1088A_QDS_H 8 9 #include "ls1088a_common.h" 10 11 12 #ifndef __ASSEMBLY__ 13 unsigned long get_board_sys_clk(void); 14 unsigned long get_board_ddr_clk(void); 15 #endif 16 17 #ifdef CONFIG_TFABOOT 18 #define CONFIG_MISC_INIT_R 19 #endif 20 21 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 22 #define CONFIG_QIXIS_I2C_ACCESS 23 #define SYS_NO_FLASH 24 25 #define CONFIG_SYS_CLK_FREQ 100000000 26 #define CONFIG_DDR_CLK_FREQ 100000000 27 #else 28 #define CONFIG_QIXIS_I2C_ACCESS 29 #if !CONFIG_IS_ENABLED(DM_I2C) 30 #define CONFIG_SYS_I2C_EARLY_INIT 31 #endif 32 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 33 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 34 #endif 35 36 #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) 37 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 38 39 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 40 41 #define CONFIG_DDR_SPD 42 #define CONFIG_DDR_ECC 43 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 44 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 45 #define SPD_EEPROM_ADDRESS 0x51 46 #define CONFIG_SYS_SPD_BUS_NUM 0 47 48 49 /* 50 * IFC Definitions 51 */ 52 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 53 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 54 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 55 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) 56 57 #define CONFIG_SYS_NOR0_CSPR \ 58 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 59 CSPR_PORT_SIZE_16 | \ 60 CSPR_MSEL_NOR | \ 61 CSPR_V) 62 #define CONFIG_SYS_NOR0_CSPR_EARLY \ 63 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ 64 CSPR_PORT_SIZE_16 | \ 65 CSPR_MSEL_NOR | \ 66 CSPR_V) 67 #define CONFIG_SYS_NOR1_CSPR \ 68 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ 69 CSPR_PORT_SIZE_16 | \ 70 CSPR_MSEL_NOR | \ 71 CSPR_V) 72 #define CONFIG_SYS_NOR1_CSPR_EARLY \ 73 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ 74 CSPR_PORT_SIZE_16 | \ 75 CSPR_MSEL_NOR | \ 76 CSPR_V) 77 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) 78 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 79 FTIM0_NOR_TEADC(0x5) | \ 80 FTIM0_NOR_TAVDS(0x6) | \ 81 FTIM0_NOR_TEAHC(0x5)) 82 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 83 FTIM1_NOR_TRAD_NOR(0x1a) | \ 84 FTIM1_NOR_TSEQRAD_NOR(0x13)) 85 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ 86 FTIM2_NOR_TCH(0x8) | \ 87 FTIM2_NOR_TWPH(0xe) | \ 88 FTIM2_NOR_TWP(0x1c)) 89 #define CONFIG_SYS_NOR_FTIM3 0x04000000 90 #define CONFIG_SYS_IFC_CCR 0x01000000 91 92 #ifndef SYS_NO_FLASH 93 #define CONFIG_SYS_FLASH_QUIET_TEST 94 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 95 96 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 97 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 98 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 99 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 100 101 #define CONFIG_SYS_FLASH_EMPTY_INFO 102 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ 103 CONFIG_SYS_FLASH_BASE + 0x40000000} 104 #endif 105 #endif 106 107 #define CONFIG_NAND_FSL_IFC 108 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 109 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 110 111 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 112 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 113 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 114 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 115 | CSPR_V) 116 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 117 118 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 119 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 120 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 121 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 122 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 123 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 124 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 125 126 #define CONFIG_SYS_NAND_ONFI_DETECTION 127 128 /* ONFI NAND Flash mode0 Timing Params */ 129 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 130 FTIM0_NAND_TWP(0x18) | \ 131 FTIM0_NAND_TWCHT(0x07) | \ 132 FTIM0_NAND_TWH(0x0a)) 133 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 134 FTIM1_NAND_TWBE(0x39) | \ 135 FTIM1_NAND_TRR(0x0e) | \ 136 FTIM1_NAND_TRP(0x18)) 137 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 138 FTIM2_NAND_TREH(0x0a) | \ 139 FTIM2_NAND_TWHRE(0x1e)) 140 #define CONFIG_SYS_NAND_FTIM3 0x0 141 142 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 143 #define CONFIG_SYS_MAX_NAND_DEVICE 1 144 #define CONFIG_MTD_NAND_VERIFY_WRITE 145 146 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 147 148 #define CONFIG_FSL_QIXIS 149 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 150 #define QIXIS_LBMAP_SWITCH 6 151 #define QIXIS_QMAP_MASK 0xe0 152 #define QIXIS_QMAP_SHIFT 5 153 #define QIXIS_LBMAP_MASK 0x0f 154 #define QIXIS_LBMAP_SHIFT 0 155 #define QIXIS_LBMAP_DFLTBANK 0x0e 156 #define QIXIS_LBMAP_ALTBANK 0x2e 157 #define QIXIS_LBMAP_SD 0x00 158 #define QIXIS_LBMAP_EMMC 0x00 159 #define QIXIS_LBMAP_IFC 0x00 160 #define QIXIS_LBMAP_SD_QSPI 0x0e 161 #define QIXIS_LBMAP_QSPI 0x0e 162 #define QIXIS_RCW_SRC_IFC 0x25 163 #define QIXIS_RCW_SRC_SD 0x40 164 #define QIXIS_RCW_SRC_EMMC 0x41 165 #define QIXIS_RCW_SRC_QSPI 0x62 166 #define QIXIS_RST_CTL_RESET 0x41 167 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 168 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 169 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 170 #define QIXIS_RST_FORCE_MEM 0x01 171 #define QIXIS_STAT_PRES1 0xb 172 #define QIXIS_SDID_MASK 0x07 173 #define QIXIS_ESDHC_NO_ADAPTER 0x7 174 175 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 176 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ 177 | CSPR_PORT_SIZE_8 \ 178 | CSPR_MSEL_GPCM \ 179 | CSPR_V) 180 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 181 | CSPR_PORT_SIZE_8 \ 182 | CSPR_MSEL_GPCM \ 183 | CSPR_V) 184 185 #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 186 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 187 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) 188 #else 189 #define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) 190 #endif 191 /* QIXIS Timing parameters*/ 192 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 193 FTIM0_GPCM_TEADC(0x0e) | \ 194 FTIM0_GPCM_TEAHC(0x0e)) 195 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 196 FTIM1_GPCM_TRAD(0x3f)) 197 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 198 FTIM2_GPCM_TCH(0xf) | \ 199 FTIM2_GPCM_TWP(0x3E)) 200 #define SYS_FPGA_CS_FTIM3 0x0 201 202 #ifdef CONFIG_TFABOOT 203 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 204 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 205 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 206 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 207 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 208 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 209 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 210 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 211 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 212 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 213 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 214 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 215 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 216 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 217 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 218 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 219 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 220 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 221 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 222 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 223 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 224 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 225 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 226 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 227 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 228 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 229 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 230 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 231 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 232 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL 233 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK 234 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 235 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 236 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 237 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 238 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 239 #else 240 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 241 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 242 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 243 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 244 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 245 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 246 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 247 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 248 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 249 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT 250 #define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR 251 #define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL 252 #define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK 253 #define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR 254 #define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 255 #define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 256 #define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 257 #define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 258 #else 259 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 260 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY 261 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR 262 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 263 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 264 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 265 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 266 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 267 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 268 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 269 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY 270 #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR 271 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY 272 #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK 273 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 274 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 275 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 276 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 277 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 278 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 279 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 280 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 281 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 282 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 283 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 284 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 285 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 286 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 287 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 288 #define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL 289 #define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK 290 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 291 #define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 292 #define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 293 #define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 294 #define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 295 #endif 296 #endif 297 298 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 299 300 /* 301 * I2C bus multiplexer 302 */ 303 #define I2C_MUX_PCA_ADDR_PRI 0x77 304 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 305 #define I2C_RETIMER_ADDR 0x18 306 #define I2C_RETIMER_ADDR2 0x19 307 #define I2C_MUX_CH_DEFAULT 0x8 308 #define I2C_MUX_CH5 0xD 309 310 #define I2C_MUX_CH_VOL_MONITOR 0xA 311 312 /* Voltage monitor on channel 2*/ 313 #define I2C_VOL_MONITOR_ADDR 0x63 314 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 315 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 316 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 317 #define I2C_SVDD_MONITOR_ADDR 0x4F 318 319 #define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv" 320 #define CONFIG_VID 321 322 /* The lowest and highest voltage allowed for LS1088AQDS */ 323 #define VDD_MV_MIN 819 324 #define VDD_MV_MAX 1212 325 326 #define CONFIG_VOL_MONITOR_LTC3882_SET 327 #define CONFIG_VOL_MONITOR_LTC3882_READ 328 329 #define PWM_CHANNEL0 0x0 330 331 /* 332 * RTC configuration 333 */ 334 #define RTC 335 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 336 337 /* EEPROM */ 338 #define CONFIG_ID_EEPROM 339 #define CONFIG_SYS_I2C_EEPROM_NXID 340 #define CONFIG_SYS_EEPROM_BUS_NUM 0 341 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 342 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 343 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 344 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 345 346 #ifdef CONFIG_FSL_DSPI 347 #define CONFIG_SPI_FLASH_STMICRO 348 #define CONFIG_SPI_FLASH_SST 349 #define CONFIG_SPI_FLASH_EON 350 #if !defined(CONFIG_TFABOOT) && \ 351 !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 352 #endif 353 #endif 354 355 #ifdef CONFIG_SPL_BUILD 356 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 357 #else 358 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 359 #endif 360 361 #define CONFIG_FSL_MEMAC 362 363 /* MMC */ 364 #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ 365 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) 366 367 #define COMMON_ENV \ 368 "kernelheader_addr_r=0x80200000\0" \ 369 "fdtheader_addr_r=0x80100000\0" \ 370 "kernel_addr_r=0x81000000\0" \ 371 "fdt_addr_r=0x90000000\0" \ 372 "load_addr=0xa0000000\0" 373 374 /* Initial environment variables */ 375 #ifdef CONFIG_NXP_ESBC 376 #undef CONFIG_EXTRA_ENV_SETTINGS 377 #define CONFIG_EXTRA_ENV_SETTINGS \ 378 COMMON_ENV \ 379 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 380 "loadaddr=0x90100000\0" \ 381 "kernel_addr=0x100000\0" \ 382 "ramdisk_addr=0x800000\0" \ 383 "ramdisk_size=0x2000000\0" \ 384 "fdt_high=0xa0000000\0" \ 385 "initrd_high=0xffffffffffffffff\0" \ 386 "kernel_start=0x1000000\0" \ 387 "kernel_load=0xa0000000\0" \ 388 "kernel_size=0x2800000\0" \ 389 "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \ 390 "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \ 391 "sf read 0xa0e00000 0xe00000 0x100000;" \ 392 "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;" \ 393 "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \ 394 "mcmemsize=0x70000000 \0" 395 #else /* if !(CONFIG_NXP_ESBC) */ 396 #ifdef CONFIG_TFABOOT 397 #define QSPI_MC_INIT_CMD \ 398 "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 399 "sf read 0x80100000 0xE00000 0x100000;" \ 400 "fsl_mc start mc 0x80000000 0x80100000\0" 401 #define SD_MC_INIT_CMD \ 402 "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 403 "mmc read 0x80100000 0x7000 0x800;" \ 404 "fsl_mc start mc 0x80000000 0x80100000\0" 405 #define IFC_MC_INIT_CMD \ 406 "fsl_mc start mc 0x580A00000 0x580E00000\0" 407 408 #undef CONFIG_EXTRA_ENV_SETTINGS 409 #define CONFIG_EXTRA_ENV_SETTINGS \ 410 COMMON_ENV \ 411 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 412 "loadaddr=0x90100000\0" \ 413 "kernel_addr=0x100000\0" \ 414 "kernel_addr_sd=0x800\0" \ 415 "ramdisk_addr=0x800000\0" \ 416 "ramdisk_size=0x2000000\0" \ 417 "fdt_high=0xa0000000\0" \ 418 "initrd_high=0xffffffffffffffff\0" \ 419 "kernel_start=0x1000000\0" \ 420 "kernel_start_sd=0x8000\0" \ 421 "kernel_load=0xa0000000\0" \ 422 "kernel_size=0x2800000\0" \ 423 "kernel_size_sd=0x14000\0" \ 424 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 425 "sf read 0x80100000 0xE00000 0x100000;" \ 426 "fsl_mc start mc 0x80000000 0x80100000\0" \ 427 "mcmemsize=0x70000000 \0" \ 428 "BOARD=ls1088aqds\0" \ 429 "scriptaddr=0x80000000\0" \ 430 "scripthdraddr=0x80080000\0" \ 431 BOOTENV \ 432 "boot_scripts=ls1088aqds_boot.scr\0" \ 433 "boot_script_hdr=hdr_ls1088aqds_bs.out\0" \ 434 "scan_dev_for_boot_part=" \ 435 "part list ${devtype} ${devnum} devplist; " \ 436 "env exists devplist || setenv devplist 1; " \ 437 "for distro_bootpart in ${devplist}; do " \ 438 "if fstype ${devtype} " \ 439 "${devnum}:${distro_bootpart} " \ 440 "bootfstype; then " \ 441 "run scan_dev_for_boot; " \ 442 "fi; " \ 443 "done\0" \ 444 "boot_a_script=" \ 445 "load ${devtype} ${devnum}:${distro_bootpart} " \ 446 "${scriptaddr} ${prefix}${script}; " \ 447 "env exists secureboot && load ${devtype} " \ 448 "${devnum}:${distro_bootpart} " \ 449 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\ 450 "env exists secureboot " \ 451 "&& esbc_validate ${scripthdraddr};" \ 452 "source ${scriptaddr}\0" \ 453 "qspi_bootcmd=echo Trying load from qspi..; " \ 454 "sf probe 0:0; " \ 455 "sf read 0x80001000 0xd00000 0x100000; " \ 456 "fsl_mc lazyapply dpl 0x80001000 && " \ 457 "sf read $kernel_load $kernel_start " \ 458 "$kernel_size && bootm $kernel_load#$BOARD\0" \ 459 "sd_bootcmd=echo Trying load from sd card..; " \ 460 "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\ 461 "fsl_mc lazyapply dpl 0x80001000 && " \ 462 "mmc read $kernel_load $kernel_start_sd " \ 463 "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \ 464 "nor_bootcmd=echo Trying load from nor..; " \ 465 "fsl_mc lazyapply dpl 0x580d00000 && " \ 466 "cp.b $kernel_start $kernel_load " \ 467 "$kernel_size && bootm $kernel_load#$BOARD\0" 468 #else 469 #if defined(CONFIG_QSPI_BOOT) 470 #undef CONFIG_EXTRA_ENV_SETTINGS 471 #define CONFIG_EXTRA_ENV_SETTINGS \ 472 COMMON_ENV \ 473 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 474 "loadaddr=0x90100000\0" \ 475 "kernel_addr=0x100000\0" \ 476 "ramdisk_addr=0x800000\0" \ 477 "ramdisk_size=0x2000000\0" \ 478 "fdt_high=0xa0000000\0" \ 479 "initrd_high=0xffffffffffffffff\0" \ 480 "kernel_start=0x1000000\0" \ 481 "kernel_load=0xa0000000\0" \ 482 "kernel_size=0x2800000\0" \ 483 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ 484 "sf read 0x80100000 0xE00000 0x100000;" \ 485 "fsl_mc start mc 0x80000000 0x80100000\0" \ 486 "mcmemsize=0x70000000 \0" 487 #elif defined(CONFIG_SD_BOOT) 488 #undef CONFIG_EXTRA_ENV_SETTINGS 489 #define CONFIG_EXTRA_ENV_SETTINGS \ 490 COMMON_ENV \ 491 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 492 "loadaddr=0x90100000\0" \ 493 "kernel_addr=0x800\0" \ 494 "ramdisk_addr=0x800000\0" \ 495 "ramdisk_size=0x2000000\0" \ 496 "fdt_high=0xa0000000\0" \ 497 "initrd_high=0xffffffffffffffff\0" \ 498 "kernel_start=0x8000\0" \ 499 "kernel_load=0xa0000000\0" \ 500 "kernel_size=0x14000\0" \ 501 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ 502 "mmc read 0x80100000 0x7000 0x800;" \ 503 "fsl_mc start mc 0x80000000 0x80100000\0" \ 504 "mcmemsize=0x70000000 \0" 505 #else /* NOR BOOT */ 506 #undef CONFIG_EXTRA_ENV_SETTINGS 507 #define CONFIG_EXTRA_ENV_SETTINGS \ 508 COMMON_ENV \ 509 "hwconfig=fsl_ddr:bank_intlv=auto\0" \ 510 "loadaddr=0x90100000\0" \ 511 "kernel_addr=0x100000\0" \ 512 "ramdisk_addr=0x800000\0" \ 513 "ramdisk_size=0x2000000\0" \ 514 "fdt_high=0xa0000000\0" \ 515 "initrd_high=0xffffffffffffffff\0" \ 516 "kernel_start=0x1000000\0" \ 517 "kernel_load=0xa0000000\0" \ 518 "kernel_size=0x2800000\0" \ 519 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \ 520 "mcmemsize=0x70000000 \0" 521 #endif 522 #endif /* CONFIG_TFABOOT */ 523 #endif /* CONFIG_NXP_ESBC */ 524 525 #ifdef CONFIG_TFABOOT 526 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ 527 "env exists secureboot && esbc_halt;;" 528 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ 529 "env exists secureboot && esbc_halt;;" 530 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ 531 "env exists secureboot && esbc_halt;;" 532 #endif 533 534 #ifdef CONFIG_FSL_MC_ENET 535 #define CONFIG_FSL_MEMAC 536 #define RGMII_PHY1_ADDR 0x1 537 #define RGMII_PHY2_ADDR 0x2 538 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 539 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d 540 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 541 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 542 543 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 544 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 545 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 546 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 547 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 548 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 549 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 550 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 551 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 552 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 553 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa 554 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb 555 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc 556 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd 557 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe 558 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf 559 560 #define CONFIG_ETHPRIME "DPMAC1@xgmii" 561 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 562 563 #endif 564 565 #define BOOT_TARGET_DEVICES(func) \ 566 func(USB, usb, 0) \ 567 func(MMC, mmc, 0) \ 568 func(SCSI, scsi, 0) \ 569 func(DHCP, dhcp, na) 570 #include <config_distro_bootcmd.h> 571 572 #include <asm/fsl_secure_boot.h> 573 574 #endif /* __LS1088A_QDS_H */ 575