1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <init.h>
9 #include <log.h>
10 #include <ram.h>
11 #include <asm/global_data.h>
12 #include <asm/io.h>
13 #include <asm/arch-rockchip/sdram.h>
14 #include <dm/uclass-internal.h>
15
16 DECLARE_GLOBAL_DATA_PTR;
17
18 #define TRUST_PARAMETER_OFFSET (34 * 1024 * 1024)
19
20 struct tos_parameter_t {
21 u32 version;
22 u32 checksum;
23 struct {
24 char name[8];
25 s64 phy_addr;
26 u32 size;
27 u32 flags;
28 } tee_mem;
29 struct {
30 char name[8];
31 s64 phy_addr;
32 u32 size;
33 u32 flags;
34 } drm_mem;
35 s64 reserve[8];
36 };
37
dram_init_banksize(void)38 int dram_init_banksize(void)
39 {
40 size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE),
41 (unsigned long)(gd->ram_top));
42
43 #ifdef CONFIG_ARM64
44 /* Reserve 0x200000 for ATF bl31 */
45 gd->bd->bi_dram[0].start = 0x200000;
46 gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
47 #else
48 #ifdef CONFIG_SPL_OPTEE
49 struct tos_parameter_t *tos_parameter;
50
51 tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE +
52 TRUST_PARAMETER_OFFSET);
53
54 if (tos_parameter->tee_mem.flags == 1) {
55 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
56 gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr
57 - CONFIG_SYS_SDRAM_BASE;
58 gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr +
59 tos_parameter->tee_mem.size;
60 gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
61 } else {
62 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
63 gd->bd->bi_dram[0].size = 0x8400000;
64 /* Reserve 32M for OPTEE with TA */
65 gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
66 + gd->bd->bi_dram[0].size + 0x2000000;
67 gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start;
68 }
69 #else
70 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
71 gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
72 #endif
73 #endif
74
75 return 0;
76 }
77
rockchip_sdram_size(phys_addr_t reg)78 size_t rockchip_sdram_size(phys_addr_t reg)
79 {
80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4;
81 size_t chipsize_mb = 0;
82 size_t size_mb = 0;
83 u32 ch;
84 u32 cs1_col = 0;
85 u32 bg = 0;
86 u32 dbw, dram_type;
87 u32 sys_reg2 = readl(reg);
88 u32 sys_reg3 = readl(reg + 4);
89 u32 ch_num = 1 + ((sys_reg2 >> SYS_REG_NUM_CH_SHIFT)
90 & SYS_REG_NUM_CH_MASK);
91
92 dram_type = (sys_reg2 >> SYS_REG_DDRTYPE_SHIFT) & SYS_REG_DDRTYPE_MASK;
93 debug("%s %x %x\n", __func__, (u32)reg, sys_reg2);
94 for (ch = 0; ch < ch_num; ch++) {
95 rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) &
96 SYS_REG_RANK_MASK);
97 cs0_col = 9 + (sys_reg2 >> SYS_REG_COL_SHIFT(ch) &
98 SYS_REG_COL_MASK);
99 cs1_col = cs0_col;
100 bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK);
101 if ((sys_reg3 >> SYS_REG_VERSION_SHIFT &
102 SYS_REG_VERSION_MASK) == 0x2) {
103 cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) &
104 SYS_REG_CS1_COL_MASK);
105 if (((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
106 SYS_REG_EXTEND_CS0_ROW_MASK) << 2) + (sys_reg2 >>
107 SYS_REG_CS0_ROW_SHIFT(ch) &
108 SYS_REG_CS0_ROW_MASK) == 7)
109 cs0_row = 12;
110 else
111 cs0_row = 13 + (sys_reg2 >>
112 SYS_REG_CS0_ROW_SHIFT(ch) &
113 SYS_REG_CS0_ROW_MASK) +
114 ((sys_reg3 >>
115 SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) &
116 SYS_REG_EXTEND_CS0_ROW_MASK) << 2);
117 if (((sys_reg3 >> SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
118 SYS_REG_EXTEND_CS1_ROW_MASK) << 2) + (sys_reg2 >>
119 SYS_REG_CS1_ROW_SHIFT(ch) &
120 SYS_REG_CS1_ROW_MASK) == 7)
121 cs1_row = 12;
122 else
123 cs1_row = 13 + (sys_reg2 >>
124 SYS_REG_CS1_ROW_SHIFT(ch) &
125 SYS_REG_CS1_ROW_MASK) +
126 ((sys_reg3 >>
127 SYS_REG_EXTEND_CS1_ROW_SHIFT(ch) &
128 SYS_REG_EXTEND_CS1_ROW_MASK) << 2);
129 } else {
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) &
131 SYS_REG_CS0_ROW_MASK);
132 cs1_row = 13 + (sys_reg2 >> SYS_REG_CS1_ROW_SHIFT(ch) &
133 SYS_REG_CS1_ROW_MASK);
134 }
135 bw = (2 >> ((sys_reg2 >> SYS_REG_BW_SHIFT(ch)) &
136 SYS_REG_BW_MASK));
137 row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) &
138 SYS_REG_ROW_3_4_MASK;
139 if (dram_type == DDR4) {
140 dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) &
141 SYS_REG_DBW_MASK;
142 bg = (dbw == 2) ? 2 : 1;
143 }
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20));
145
146 if (rank > 1)
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) +
148 (cs0_col - cs1_col));
149 if (row_3_4)
150 chipsize_mb = chipsize_mb * 3 / 4;
151 size_mb += chipsize_mb;
152 if (rank > 1)
153 debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d\
154 cs1_row %d bw %d row_3_4 %d\n",
155 rank, cs0_col, cs1_col, bk, cs0_row,
156 cs1_row, bw, row_3_4);
157 else
158 debug("rank %d cs0_col %d bk %d cs0_row %d\
159 bw %d row_3_4 %d\n",
160 rank, cs0_col, bk, cs0_row,
161 bw, row_3_4);
162 }
163
164 /*
165 * This is workaround for issue we can't get correct size for 4GB ram
166 * in 32bit system and available before we really need ram space
167 * out of 4GB, eg.enable ARM LAPE(rk3288 supports 8GB ram).
168 * The size of 4GB is '0x1 00000000', and this value will be truncated
169 * to 0 in 32bit system, and system can not get correct ram size.
170 * Rockchip SoCs reserve a blob of space for peripheral near 4GB,
171 * and we are now setting SDRAM_MAX_SIZE as max available space for
172 * ram in 4GB, so we can use this directly to workaround the issue.
173 * TODO:
174 * 1. update correct value for SDRAM_MAX_SIZE as what dram
175 * controller sees.
176 * 2. update board_get_usable_ram_top() and dram_init_banksize()
177 * to reserve memory for peripheral space after previous update.
178 */
179 if (size_mb > (SDRAM_MAX_SIZE >> 20))
180 size_mb = (SDRAM_MAX_SIZE >> 20);
181
182 return (size_t)size_mb << 20;
183 }
184
dram_init(void)185 int dram_init(void)
186 {
187 struct ram_info ram;
188 struct udevice *dev;
189 int ret;
190
191 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
192 if (ret) {
193 debug("DRAM init failed: %d\n", ret);
194 return ret;
195 }
196 ret = ram_get_info(dev, &ram);
197 if (ret) {
198 debug("Cannot get DRAM size: %d\n", ret);
199 return ret;
200 }
201 gd->ram_size = ram.size;
202 debug("SDRAM base=%lx, size=%lx\n",
203 (unsigned long)ram.base, (unsigned long)ram.size);
204
205 return 0;
206 }
207
board_get_usable_ram_top(ulong total_size)208 ulong board_get_usable_ram_top(ulong total_size)
209 {
210 unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE;
211
212 return (gd->ram_top > top) ? top : gd->ram_top;
213 }
214