1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2015 Rockchip Electronics Co., Ltd
4  */
5 #ifndef _ASM_ARCH_CRU_RK3036_H
6 #define _ASM_ARCH_CRU_RK3036_H
7 
8 #define OSC_HZ		(24 * 1000 * 1000)
9 
10 #define APLL_HZ		(600 * 1000000)
11 #define GPLL_HZ		(594 * 1000000)
12 
13 #define CORE_PERI_HZ	150000000
14 #define CORE_ACLK_HZ	300000000
15 
16 #define BUS_ACLK_HZ	148500000
17 #define BUS_HCLK_HZ	148500000
18 #define BUS_PCLK_HZ	74250000
19 
20 #define PERI_ACLK_HZ	148500000
21 #define PERI_HCLK_HZ	148500000
22 #define PERI_PCLK_HZ	74250000
23 
24 /* Private data for the clock driver - used by rockchip_get_cru() */
25 struct rk3036_clk_priv {
26 	struct rk3036_cru *cru;
27 	ulong rate;
28 };
29 
30 struct rk3036_cru {
31 	struct rk3036_pll {
32 		unsigned int con0;
33 		unsigned int con1;
34 		unsigned int con2;
35 		unsigned int con3;
36 	} pll[4];
37 	unsigned int cru_mode_con;
38 	unsigned int cru_clksel_con[35];
39 	unsigned int cru_clkgate_con[11];
40 	unsigned int reserved;
41 	unsigned int cru_glb_srst_fst_value;
42 	unsigned int cru_glb_srst_snd_value;
43 	unsigned int reserved1[2];
44 	unsigned int cru_softrst_con[9];
45 	unsigned int cru_misc_con;
46 	unsigned int reserved2[2];
47 	unsigned int cru_glb_cnt_th;
48 	unsigned int cru_sdmmc_con[2];
49 	unsigned int cru_sdio_con[2];
50 	unsigned int cru_emmc_con[2];
51 	unsigned int reserved3;
52 	unsigned int cru_rst_st;
53 	unsigned int reserved4[0x23];
54 	unsigned int cru_pll_mask_con;
55 };
56 check_member(rk3036_cru, cru_pll_mask_con, 0x01f0);
57 
58 struct pll_div {
59 	u32 refdiv;
60 	u32 fbdiv;
61 	u32 postdiv1;
62 	u32 postdiv2;
63 	u32 frac;
64 };
65 
66 enum {
67 	/* PLLCON0*/
68 	PLL_POSTDIV1_SHIFT	= 12,
69 	PLL_POSTDIV1_MASK	= 7 << PLL_POSTDIV1_SHIFT,
70 	PLL_FBDIV_SHIFT		= 0,
71 	PLL_FBDIV_MASK		= 0xfff,
72 
73 	/* PLLCON1 */
74 	PLL_RST_SHIFT		= 14,
75 	PLL_DSMPD_SHIFT		= 12,
76 	PLL_DSMPD_MASK		= 1 << PLL_DSMPD_SHIFT,
77 	PLL_LOCK_STATUS_SHIFT	= 10,
78 	PLL_LOCK_STATUS_MASK	= 1 << PLL_LOCK_STATUS_SHIFT,
79 	PLL_POSTDIV2_SHIFT	= 6,
80 	PLL_POSTDIV2_MASK	= 7 << PLL_POSTDIV2_SHIFT,
81 	PLL_REFDIV_SHIFT	= 0,
82 	PLL_REFDIV_MASK		= 0x3f,
83 
84 	/* CRU_MODE */
85 	GPLL_MODE_SHIFT		= 12,
86 	GPLL_MODE_MASK		= 3 << GPLL_MODE_SHIFT,
87 	GPLL_MODE_SLOW		= 0,
88 	GPLL_MODE_NORM,
89 	GPLL_MODE_DEEP,
90 	DPLL_MODE_SHIFT		= 4,
91 	DPLL_MODE_MASK		= 1 << DPLL_MODE_SHIFT,
92 	DPLL_MODE_SLOW		= 0,
93 	DPLL_MODE_NORM,
94 	APLL_MODE_SHIFT		= 0,
95 	APLL_MODE_MASK		= 1 << APLL_MODE_SHIFT,
96 	APLL_MODE_SLOW		= 0,
97 	APLL_MODE_NORM,
98 
99 	/* CRU_CLK_SEL0_CON */
100 	BUS_ACLK_PLL_SEL_SHIFT	= 14,
101 	BUS_ACLK_PLL_SEL_MASK	= 3 << BUS_ACLK_PLL_SEL_SHIFT,
102 	BUS_ACLK_PLL_SEL_APLL	= 0,
103 	BUS_ACLK_PLL_SEL_DPLL,
104 	BUS_ACLK_PLL_SEL_GPLL,
105 	BUS_ACLK_DIV_SHIFT	= 8,
106 	BUS_ACLK_DIV_MASK	= 0x1f << BUS_ACLK_DIV_SHIFT,
107 	CORE_CLK_PLL_SEL_SHIFT	= 7,
108 	CORE_CLK_PLL_SEL_MASK	= 1 << CORE_CLK_PLL_SEL_SHIFT,
109 	CORE_CLK_PLL_SEL_APLL	= 0,
110 	CORE_CLK_PLL_SEL_GPLL,
111 	CORE_DIV_CON_SHIFT	= 0,
112 	CORE_DIV_CON_MASK	= 0x1f << CORE_DIV_CON_SHIFT,
113 
114 	/* CRU_CLK_SEL1_CON */
115 	BUS_PCLK_DIV_SHIFT	= 12,
116 	BUS_PCLK_DIV_MASK	= 7 << BUS_PCLK_DIV_SHIFT,
117 	BUS_HCLK_DIV_SHIFT	= 8,
118 	BUS_HCLK_DIV_MASK	= 3 << BUS_HCLK_DIV_SHIFT,
119 	CORE_ACLK_DIV_SHIFT	= 4,
120 	CORE_ACLK_DIV_MASK	= 7 << CORE_ACLK_DIV_SHIFT,
121 	CORE_PERI_DIV_SHIFT	= 0,
122 	CORE_PERI_DIV_MASK	= 0xf << CORE_PERI_DIV_SHIFT,
123 
124 	/* CRU_CLKSEL10_CON */
125 	PERI_PLL_SEL_SHIFT	= 14,
126 	PERI_PLL_SEL_MASK	= 3 << PERI_PLL_SEL_SHIFT,
127 	PERI_PLL_APLL		= 0,
128 	PERI_PLL_DPLL,
129 	PERI_PLL_GPLL,
130 	PERI_PCLK_DIV_SHIFT	= 12,
131 	PERI_PCLK_DIV_MASK	= 3 << PERI_PCLK_DIV_SHIFT,
132 	PERI_HCLK_DIV_SHIFT	= 8,
133 	PERI_HCLK_DIV_MASK	= 3 << PERI_HCLK_DIV_SHIFT,
134 	PERI_ACLK_DIV_SHIFT	= 0,
135 	PERI_ACLK_DIV_MASK	= 0x1f << PERI_ACLK_DIV_SHIFT,
136 
137 	/* CRU_CLKSEL11_CON */
138 	SDIO_DIV_SHIFT		= 8,
139 	SDIO_DIV_MASK		= 0x7f << SDIO_DIV_SHIFT,
140 	MMC0_DIV_SHIFT		= 0,
141 	MMC0_DIV_MASK		= 0x7f << MMC0_DIV_SHIFT,
142 
143 	/* CRU_CLKSEL12_CON */
144 	EMMC_PLL_SHIFT		= 12,
145 	EMMC_PLL_MASK		= 3 << EMMC_PLL_SHIFT,
146 	EMMC_SEL_APLL		= 0,
147 	EMMC_SEL_DPLL,
148 	EMMC_SEL_GPLL,
149 	EMMC_SEL_24M,
150 	SDIO_PLL_SHIFT		= 10,
151 	SDIO_PLL_MASK		= 3 << SDIO_PLL_SHIFT,
152 	SDIO_SEL_APLL		= 0,
153 	SDIO_SEL_DPLL,
154 	SDIO_SEL_GPLL,
155 	SDIO_SEL_24M,
156 	MMC0_PLL_SHIFT		= 8,
157 	MMC0_PLL_MASK		= 3 << MMC0_PLL_SHIFT,
158 	MMC0_SEL_APLL		= 0,
159 	MMC0_SEL_DPLL,
160 	MMC0_SEL_GPLL,
161 	MMC0_SEL_24M,
162 	EMMC_DIV_SHIFT		= 0,
163 	EMMC_DIV_MASK		= 0x7f << EMMC_DIV_SHIFT,
164 
165 	/* CRU_SOFTRST5_CON */
166 	DDRCTRL_PSRST_SHIFT	= 11,
167 	DDRCTRL_SRST_SHIFT	= 10,
168 	DDRPHY_PSRST_SHIFT	= 9,
169 	DDRPHY_SRST_SHIFT	= 8,
170 };
171 #endif
172