1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2017-2019 NXP
4 *
5 * Peng Fan <peng.fan@nxp.com>
6 */
7
8 #include <common.h>
9 #include <cpu_func.h>
10 #include <init.h>
11 #include <log.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/global_data.h>
14 #include <asm/io.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/sys_proto.h>
17 #include <asm/mach-imx/hab.h>
18 #include <asm/mach-imx/boot_mode.h>
19 #include <asm/mach-imx/syscounter.h>
20 #include <asm/ptrace.h>
21 #include <asm/armv8/mmu.h>
22 #include <dm/uclass.h>
23 #include <efi_loader.h>
24 #include <env.h>
25 #include <env_internal.h>
26 #include <errno.h>
27 #include <fdt_support.h>
28 #include <fsl_wdog.h>
29 #include <imx_sip.h>
30 #include <linux/arm-smccc.h>
31 #include <linux/bitops.h>
32
33 DECLARE_GLOBAL_DATA_PTR;
34
35 #if defined(CONFIG_IMX_HAB)
36 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
37 .bank = 1,
38 .word = 3,
39 };
40 #endif
41
timer_init(void)42 int timer_init(void)
43 {
44 #ifdef CONFIG_SPL_BUILD
45 struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
46 unsigned long freq = readl(&sctr->cntfid0);
47
48 /* Update with accurate clock frequency */
49 asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
50
51 clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
52 SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
53 #endif
54
55 gd->arch.tbl = 0;
56 gd->arch.tbu = 0;
57
58 return 0;
59 }
60
enable_tzc380(void)61 void enable_tzc380(void)
62 {
63 struct iomuxc_gpr_base_regs *gpr =
64 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
65
66 /* Enable TZASC and lock setting */
67 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
68 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
69 if (is_imx8mm() || is_imx8mn() || is_imx8mp())
70 setbits_le32(&gpr->gpr[10], BIT(1));
71 /*
72 * set Region 0 attribute to allow secure and non-secure
73 * read/write permission. Found some masters like usb dwc3
74 * controllers can't work with secure memory.
75 */
76 writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
77 }
78
set_wdog_reset(struct wdog_regs * wdog)79 void set_wdog_reset(struct wdog_regs *wdog)
80 {
81 /*
82 * Output WDOG_B signal to reset external pmic or POR_B decided by
83 * the board design. Without external reset, the peripherals/DDR/
84 * PMIC are not reset, that may cause system working abnormal.
85 * WDZST bit is write-once only bit. Align this bit in kernel,
86 * otherwise kernel code will have no chance to set this bit.
87 */
88 setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
89 }
90
91 static struct mm_region imx8m_mem_map[] = {
92 {
93 /* ROM */
94 .virt = 0x0UL,
95 .phys = 0x0UL,
96 .size = 0x100000UL,
97 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
98 PTE_BLOCK_OUTER_SHARE
99 }, {
100 /* CAAM */
101 .virt = 0x100000UL,
102 .phys = 0x100000UL,
103 .size = 0x8000UL,
104 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
105 PTE_BLOCK_NON_SHARE |
106 PTE_BLOCK_PXN | PTE_BLOCK_UXN
107 }, {
108 /* OCRAM_S */
109 .virt = 0x180000UL,
110 .phys = 0x180000UL,
111 .size = 0x8000UL,
112 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
113 PTE_BLOCK_OUTER_SHARE
114 }, {
115 /* TCM */
116 .virt = 0x7C0000UL,
117 .phys = 0x7C0000UL,
118 .size = 0x80000UL,
119 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
120 PTE_BLOCK_NON_SHARE |
121 PTE_BLOCK_PXN | PTE_BLOCK_UXN
122 }, {
123 /* OCRAM */
124 .virt = 0x900000UL,
125 .phys = 0x900000UL,
126 .size = 0x200000UL,
127 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
128 PTE_BLOCK_OUTER_SHARE
129 }, {
130 /* AIPS */
131 .virt = 0xB00000UL,
132 .phys = 0xB00000UL,
133 .size = 0x3f500000UL,
134 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
135 PTE_BLOCK_NON_SHARE |
136 PTE_BLOCK_PXN | PTE_BLOCK_UXN
137 }, {
138 /* DRAM1 */
139 .virt = 0x40000000UL,
140 .phys = 0x40000000UL,
141 .size = PHYS_SDRAM_SIZE,
142 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
143 PTE_BLOCK_OUTER_SHARE
144 #ifdef PHYS_SDRAM_2_SIZE
145 }, {
146 /* DRAM2 */
147 .virt = 0x100000000UL,
148 .phys = 0x100000000UL,
149 .size = PHYS_SDRAM_2_SIZE,
150 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
151 PTE_BLOCK_OUTER_SHARE
152 #endif
153 }, {
154 /* empty entrie to split table entry 5 if needed when TEEs are used */
155 0,
156 }, {
157 /* List terminator */
158 0,
159 }
160 };
161
162 struct mm_region *mem_map = imx8m_mem_map;
163
imx8m_find_dram_entry_in_mem_map(void)164 static unsigned int imx8m_find_dram_entry_in_mem_map(void)
165 {
166 int i;
167
168 for (i = 0; i < ARRAY_SIZE(imx8m_mem_map); i++)
169 if (imx8m_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE)
170 return i;
171
172 hang(); /* Entry not found, this must never happen. */
173 }
174
enable_caches(void)175 void enable_caches(void)
176 {
177 /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */
178 if (rom_pointer[1]) {
179 /*
180 * TEE are loaded, So the ddr bank structures
181 * have been modified update mmu table accordingly
182 */
183 int i = 0;
184 /*
185 * please make sure that entry initial value matches
186 * imx8m_mem_map for DRAM1
187 */
188 int entry = imx8m_find_dram_entry_in_mem_map();
189 u64 attrs = imx8m_mem_map[entry].attrs;
190
191 while (i < CONFIG_NR_DRAM_BANKS &&
192 entry < ARRAY_SIZE(imx8m_mem_map)) {
193 if (gd->bd->bi_dram[i].start == 0)
194 break;
195 imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
196 imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
197 imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
198 imx8m_mem_map[entry].attrs = attrs;
199 debug("Added memory mapping (%d): %llx %llx\n", entry,
200 imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
201 i++; entry++;
202 }
203 }
204
205 icache_enable();
206 dcache_enable();
207 }
208
board_phys_sdram_size(phys_size_t * size)209 __weak int board_phys_sdram_size(phys_size_t *size)
210 {
211 if (!size)
212 return -EINVAL;
213
214 *size = PHYS_SDRAM_SIZE;
215 return 0;
216 }
217
dram_init(void)218 int dram_init(void)
219 {
220 unsigned int entry = imx8m_find_dram_entry_in_mem_map();
221 phys_size_t sdram_size;
222 int ret;
223
224 ret = board_phys_sdram_size(&sdram_size);
225 if (ret)
226 return ret;
227
228 /* rom_pointer[1] contains the size of TEE occupies */
229 if (rom_pointer[1])
230 gd->ram_size = sdram_size - rom_pointer[1];
231 else
232 gd->ram_size = sdram_size;
233
234 /* also update the SDRAM size in the mem_map used externally */
235 imx8m_mem_map[entry].size = sdram_size;
236
237 #ifdef PHYS_SDRAM_2_SIZE
238 gd->ram_size += PHYS_SDRAM_2_SIZE;
239 #endif
240
241 return 0;
242 }
243
dram_init_banksize(void)244 int dram_init_banksize(void)
245 {
246 int bank = 0;
247 int ret;
248 phys_size_t sdram_size;
249
250 ret = board_phys_sdram_size(&sdram_size);
251 if (ret)
252 return ret;
253
254 gd->bd->bi_dram[bank].start = PHYS_SDRAM;
255 if (rom_pointer[1]) {
256 phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
257 phys_size_t optee_size = (size_t)rom_pointer[1];
258
259 gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
260 if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {
261 if (++bank >= CONFIG_NR_DRAM_BANKS) {
262 puts("CONFIG_NR_DRAM_BANKS is not enough\n");
263 return -1;
264 }
265
266 gd->bd->bi_dram[bank].start = optee_start + optee_size;
267 gd->bd->bi_dram[bank].size = PHYS_SDRAM +
268 sdram_size - gd->bd->bi_dram[bank].start;
269 }
270 } else {
271 gd->bd->bi_dram[bank].size = sdram_size;
272 }
273
274 #ifdef PHYS_SDRAM_2_SIZE
275 if (++bank >= CONFIG_NR_DRAM_BANKS) {
276 puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
277 return -1;
278 }
279 gd->bd->bi_dram[bank].start = PHYS_SDRAM_2;
280 gd->bd->bi_dram[bank].size = PHYS_SDRAM_2_SIZE;
281 #endif
282
283 return 0;
284 }
285
get_effective_memsize(void)286 phys_size_t get_effective_memsize(void)
287 {
288 /* return the first bank as effective memory */
289 if (rom_pointer[1])
290 return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
291
292 #ifdef PHYS_SDRAM_2_SIZE
293 return gd->ram_size - PHYS_SDRAM_2_SIZE;
294 #else
295 return gd->ram_size;
296 #endif
297 }
298
get_cpu_variant_type(u32 type)299 static u32 get_cpu_variant_type(u32 type)
300 {
301 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
302 struct fuse_bank *bank = &ocotp->bank[1];
303 struct fuse_bank1_regs *fuse =
304 (struct fuse_bank1_regs *)bank->fuse_regs;
305
306 u32 value = readl(&fuse->tester4);
307
308 if (type == MXC_CPU_IMX8MQ) {
309 if ((value & 0x3) == 0x2)
310 return MXC_CPU_IMX8MD;
311 else if (value & 0x200000)
312 return MXC_CPU_IMX8MQL;
313
314 } else if (type == MXC_CPU_IMX8MM) {
315 switch (value & 0x3) {
316 case 2:
317 if (value & 0x1c0000)
318 return MXC_CPU_IMX8MMDL;
319 else
320 return MXC_CPU_IMX8MMD;
321 case 3:
322 if (value & 0x1c0000)
323 return MXC_CPU_IMX8MMSL;
324 else
325 return MXC_CPU_IMX8MMS;
326 default:
327 if (value & 0x1c0000)
328 return MXC_CPU_IMX8MML;
329 break;
330 }
331 } else if (type == MXC_CPU_IMX8MN) {
332 switch (value & 0x3) {
333 case 2:
334 if (value & 0x1000000) {
335 if (value & 0x10000000) /* MIPI DSI */
336 return MXC_CPU_IMX8MNUD;
337 else
338 return MXC_CPU_IMX8MNDL;
339 } else {
340 return MXC_CPU_IMX8MND;
341 }
342 case 3:
343 if (value & 0x1000000) {
344 if (value & 0x10000000) /* MIPI DSI */
345 return MXC_CPU_IMX8MNUS;
346 else
347 return MXC_CPU_IMX8MNSL;
348 } else {
349 return MXC_CPU_IMX8MNS;
350 }
351 default:
352 if (value & 0x1000000) {
353 if (value & 0x10000000) /* MIPI DSI */
354 return MXC_CPU_IMX8MNUQ;
355 else
356 return MXC_CPU_IMX8MNL;
357 }
358 break;
359 }
360 } else if (type == MXC_CPU_IMX8MP) {
361 u32 value0 = readl(&fuse->tester3);
362 u32 flag = 0;
363
364 if ((value0 & 0xc0000) == 0x80000)
365 return MXC_CPU_IMX8MPD;
366
367 /* vpu disabled */
368 if ((value0 & 0x43000000) == 0x43000000)
369 flag = 1;
370
371 /* npu disabled*/
372 if ((value & 0x8) == 0x8)
373 flag |= (1 << 1);
374
375 /* isp disabled */
376 if ((value & 0x3) == 0x3)
377 flag |= (1 << 2);
378
379 switch (flag) {
380 case 7:
381 return MXC_CPU_IMX8MPL;
382 case 2:
383 return MXC_CPU_IMX8MP6;
384 default:
385 break;
386 }
387
388 }
389
390 return type;
391 }
392
get_cpu_rev(void)393 u32 get_cpu_rev(void)
394 {
395 struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
396 u32 reg = readl(&ana_pll->digprog);
397 u32 type = (reg >> 16) & 0xff;
398 u32 major_low = (reg >> 8) & 0xff;
399 u32 rom_version;
400
401 reg &= 0xff;
402
403 /* iMX8MP */
404 if (major_low == 0x43) {
405 type = get_cpu_variant_type(MXC_CPU_IMX8MP);
406 } else if (major_low == 0x42) {
407 /* iMX8MN */
408 type = get_cpu_variant_type(MXC_CPU_IMX8MN);
409 } else if (major_low == 0x41) {
410 type = get_cpu_variant_type(MXC_CPU_IMX8MM);
411 } else {
412 if (reg == CHIP_REV_1_0) {
413 /*
414 * For B0 chip, the DIGPROG is not updated,
415 * it is still TO1.0. we have to check ROM
416 * version or OCOTP_READ_FUSE_DATA.
417 * 0xff0055aa is magic number for B1.
418 */
419 if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
420 /*
421 * B2 uses same DIGPROG and OCOTP_READ_FUSE_DATA value with B1,
422 * so have to check ROM to distinguish them
423 */
424 rom_version = readl((void __iomem *)ROM_VERSION_B0);
425 rom_version &= 0xff;
426 if (rom_version == CHIP_REV_2_2)
427 reg = CHIP_REV_2_2;
428 else
429 reg = CHIP_REV_2_1;
430 } else {
431 rom_version =
432 readl((void __iomem *)ROM_VERSION_A0);
433 if (rom_version != CHIP_REV_1_0) {
434 rom_version = readl((void __iomem *)ROM_VERSION_B0);
435 rom_version &= 0xff;
436 if (rom_version == CHIP_REV_2_0)
437 reg = CHIP_REV_2_0;
438 }
439 }
440 }
441
442 type = get_cpu_variant_type(type);
443 }
444
445 return (type << 12) | reg;
446 }
447
imx_set_wdog_powerdown(bool enable)448 static void imx_set_wdog_powerdown(bool enable)
449 {
450 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
451 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
452 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
453
454 /* Write to the PDE (Power Down Enable) bit */
455 writew(enable, &wdog1->wmcr);
456 writew(enable, &wdog2->wmcr);
457 writew(enable, &wdog3->wmcr);
458 }
459
arch_cpu_init_dm(void)460 int arch_cpu_init_dm(void)
461 {
462 struct udevice *dev;
463 int ret;
464
465 if (CONFIG_IS_ENABLED(CLK)) {
466 ret = uclass_get_device_by_name(UCLASS_CLK,
467 "clock-controller@30380000",
468 &dev);
469 if (ret < 0) {
470 printf("Failed to find clock node. Check device tree\n");
471 return ret;
472 }
473 }
474
475 return 0;
476 }
477
arch_cpu_init(void)478 int arch_cpu_init(void)
479 {
480 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
481 /*
482 * ROM might disable clock for SCTR,
483 * enable the clock before timer_init.
484 */
485 if (IS_ENABLED(CONFIG_SPL_BUILD))
486 clock_enable(CCGR_SCTR, 1);
487 /*
488 * Init timer at very early state, because sscg pll setting
489 * will use it
490 */
491 timer_init();
492
493 if (IS_ENABLED(CONFIG_SPL_BUILD)) {
494 clock_init();
495 imx_set_wdog_powerdown(false);
496
497 if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() ||
498 is_imx8mmsl() || is_imx8mnd() || is_imx8mndl() || is_imx8mns() ||
499 is_imx8mnsl() || is_imx8mpd() || is_imx8mnud() || is_imx8mnus()) {
500 /* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */
501 struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840);
502 struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880);
503 struct pgc_reg *pgc_core3 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x8C0);
504 struct gpc_reg *gpc = (struct gpc_reg *)GPC_BASE_ADDR;
505
506 writel(0x1, &pgc_core2->pgcr);
507 writel(0x1, &pgc_core3->pgcr);
508 if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl() || is_imx8mnus()) {
509 writel(0x1, &pgc_core1->pgcr);
510 writel(0xE, &gpc->cpu_pgc_dn_trg);
511 } else {
512 writel(0xC, &gpc->cpu_pgc_dn_trg);
513 }
514 }
515 }
516
517 if (is_imx8mq()) {
518 clock_enable(CCGR_OCOTP, 1);
519 if (readl(&ocotp->ctrl) & 0x200)
520 writel(0x200, &ocotp->ctrl_clr);
521 }
522
523 return 0;
524 }
525
526 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
527 struct rom_api *g_rom_api = (struct rom_api *)0x980;
528
get_boot_device(void)529 enum boot_device get_boot_device(void)
530 {
531 volatile gd_t *pgd = gd;
532 int ret;
533 u32 boot;
534 u16 boot_type;
535 u8 boot_instance;
536 enum boot_device boot_dev = SD1_BOOT;
537
538 ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
539 ((uintptr_t)&boot) ^ QUERY_BT_DEV);
540 set_gd(pgd);
541
542 if (ret != ROM_API_OKAY) {
543 puts("ROMAPI: failure at query_boot_info\n");
544 return -1;
545 }
546
547 boot_type = boot >> 16;
548 boot_instance = (boot >> 8) & 0xff;
549
550 switch (boot_type) {
551 case BT_DEV_TYPE_SD:
552 boot_dev = boot_instance + SD1_BOOT;
553 break;
554 case BT_DEV_TYPE_MMC:
555 boot_dev = boot_instance + MMC1_BOOT;
556 break;
557 case BT_DEV_TYPE_NAND:
558 boot_dev = NAND_BOOT;
559 break;
560 case BT_DEV_TYPE_FLEXSPINOR:
561 boot_dev = QSPI_BOOT;
562 break;
563 case BT_DEV_TYPE_USB:
564 boot_dev = USB_BOOT;
565 break;
566 default:
567 break;
568 }
569
570 return boot_dev;
571 }
572 #endif
573
is_usb_boot(void)574 bool is_usb_boot(void)
575 {
576 return get_boot_device() == USB_BOOT;
577 }
578
579 #ifdef CONFIG_OF_SYSTEM_SETUP
check_fdt_new_path(void * blob)580 bool check_fdt_new_path(void *blob)
581 {
582 const char *soc_path = "/soc@0";
583 int nodeoff;
584
585 nodeoff = fdt_path_offset(blob, soc_path);
586 if (nodeoff < 0)
587 return false;
588
589 return true;
590 }
591
disable_fdt_nodes(void * blob,const char * const nodes_path[],int size_array)592 static int disable_fdt_nodes(void *blob, const char *const nodes_path[], int size_array)
593 {
594 int i = 0;
595 int rc;
596 int nodeoff;
597 const char *status = "disabled";
598
599 for (i = 0; i < size_array; i++) {
600 nodeoff = fdt_path_offset(blob, nodes_path[i]);
601 if (nodeoff < 0)
602 continue; /* Not found, skip it */
603
604 printf("Found %s node\n", nodes_path[i]);
605
606 add_status:
607 rc = fdt_setprop(blob, nodeoff, "status", status, strlen(status) + 1);
608 if (rc) {
609 if (rc == -FDT_ERR_NOSPACE) {
610 rc = fdt_increase_size(blob, 512);
611 if (!rc)
612 goto add_status;
613 }
614 printf("Unable to update property %s:%s, err=%s\n",
615 nodes_path[i], "status", fdt_strerror(rc));
616 } else {
617 printf("Modify %s:%s disabled\n",
618 nodes_path[i], "status");
619 }
620 }
621
622 return 0;
623 }
624
625 #ifdef CONFIG_IMX8MQ
check_dcss_fused(void)626 bool check_dcss_fused(void)
627 {
628 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
629 struct fuse_bank *bank = &ocotp->bank[1];
630 struct fuse_bank1_regs *fuse =
631 (struct fuse_bank1_regs *)bank->fuse_regs;
632 u32 value = readl(&fuse->tester4);
633
634 if (value & 0x4000000)
635 return true;
636
637 return false;
638 }
639
disable_mipi_dsi_nodes(void * blob)640 static int disable_mipi_dsi_nodes(void *blob)
641 {
642 static const char * const nodes_path[] = {
643 "/mipi_dsi@30A00000",
644 "/mipi_dsi_bridge@30A00000",
645 "/dsi_phy@30A00300",
646 "/soc@0/bus@30800000/mipi_dsi@30a00000",
647 "/soc@0/bus@30800000/dphy@30a00300",
648 "/soc@0/bus@30800000/mipi-dsi@30a00000",
649 };
650
651 return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
652 }
653
disable_dcss_nodes(void * blob)654 static int disable_dcss_nodes(void *blob)
655 {
656 static const char * const nodes_path[] = {
657 "/dcss@0x32e00000",
658 "/dcss@32e00000",
659 "/hdmi@32c00000",
660 "/hdmi_cec@32c33800",
661 "/hdmi_drm@32c00000",
662 "/display-subsystem",
663 "/sound-hdmi",
664 "/sound-hdmi-arc",
665 "/soc@0/bus@32c00000/display-controller@32e00000",
666 "/soc@0/bus@32c00000/hdmi@32c00000",
667 };
668
669 return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
670 }
671
check_mipi_dsi_nodes(void * blob)672 static int check_mipi_dsi_nodes(void *blob)
673 {
674 static const char * const lcdif_path[] = {
675 "/lcdif@30320000",
676 "/soc@0/bus@30000000/lcdif@30320000",
677 "/soc@0/bus@30000000/lcd-controller@30320000"
678 };
679 static const char * const mipi_dsi_path[] = {
680 "/mipi_dsi@30A00000",
681 "/soc@0/bus@30800000/mipi_dsi@30a00000"
682 };
683 static const char * const lcdif_ep_path[] = {
684 "/lcdif@30320000/port@0/mipi-dsi-endpoint",
685 "/soc@0/bus@30000000/lcdif@30320000/port@0/endpoint",
686 "/soc@0/bus@30000000/lcd-controller@30320000/port@0/endpoint"
687 };
688 static const char * const mipi_dsi_ep_path[] = {
689 "/mipi_dsi@30A00000/port@1/endpoint",
690 "/soc@0/bus@30800000/mipi_dsi@30a00000/ports/port@0/endpoint",
691 "/soc@0/bus@30800000/mipi-dsi@30a00000/ports/port@0/endpoint@0"
692 };
693
694 int lookup_node;
695 int nodeoff;
696 bool new_path = check_fdt_new_path(blob);
697 int i = new_path ? 1 : 0;
698
699 nodeoff = fdt_path_offset(blob, lcdif_path[i]);
700 if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff)) {
701 /*
702 * If can't find lcdif node or lcdif node is disabled,
703 * then disable all mipi dsi, since they only can input
704 * from DCSS
705 */
706 return disable_mipi_dsi_nodes(blob);
707 }
708
709 nodeoff = fdt_path_offset(blob, mipi_dsi_path[i]);
710 if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff))
711 return 0;
712
713 nodeoff = fdt_path_offset(blob, lcdif_ep_path[i]);
714 if (nodeoff < 0) {
715 /*
716 * If can't find lcdif endpoint, then disable all mipi dsi,
717 * since they only can input from DCSS
718 */
719 return disable_mipi_dsi_nodes(blob);
720 }
721
722 lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint");
723 nodeoff = fdt_path_offset(blob, mipi_dsi_ep_path[i]);
724
725 if (nodeoff > 0 && nodeoff == lookup_node)
726 return 0;
727
728 return disable_mipi_dsi_nodes(blob);
729 }
730 #endif
731
disable_vpu_nodes(void * blob)732 int disable_vpu_nodes(void *blob)
733 {
734 static const char * const nodes_path_8mq[] = {
735 "/vpu@38300000",
736 "/soc@0/vpu@38300000"
737 };
738
739 static const char * const nodes_path_8mm[] = {
740 "/vpu_g1@38300000",
741 "/vpu_g2@38310000",
742 "/vpu_h1@38320000"
743 };
744
745 static const char * const nodes_path_8mp[] = {
746 "/vpu_g1@38300000",
747 "/vpu_g2@38310000",
748 "/vpu_vc8000e@38320000"
749 };
750
751 if (is_imx8mq())
752 return disable_fdt_nodes(blob, nodes_path_8mq, ARRAY_SIZE(nodes_path_8mq));
753 else if (is_imx8mm())
754 return disable_fdt_nodes(blob, nodes_path_8mm, ARRAY_SIZE(nodes_path_8mm));
755 else if (is_imx8mp())
756 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
757 else
758 return -EPERM;
759 }
760
761 #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
low_drive_gpu_freq(void * blob)762 static int low_drive_gpu_freq(void *blob)
763 {
764 static const char *nodes_path_8mn[] = {
765 "/gpu@38000000",
766 "/soc@0/gpu@38000000"
767 };
768
769 int nodeoff, cnt, i;
770 u32 assignedclks[7];
771
772 nodeoff = fdt_path_offset(blob, nodes_path_8mn[0]);
773 if (nodeoff < 0)
774 return nodeoff;
775
776 cnt = fdtdec_get_int_array_count(blob, nodeoff, "assigned-clock-rates", assignedclks, 7);
777 if (cnt < 0)
778 return cnt;
779
780 if (cnt != 7)
781 printf("Warning: %s, assigned-clock-rates count %d\n", nodes_path_8mn[0], cnt);
782
783 assignedclks[cnt - 1] = 200000000;
784 assignedclks[cnt - 2] = 200000000;
785
786 for (i = 0; i < cnt; i++) {
787 debug("<%u>, ", assignedclks[i]);
788 assignedclks[i] = cpu_to_fdt32(assignedclks[i]);
789 }
790 debug("\n");
791
792 return fdt_setprop(blob, nodeoff, "assigned-clock-rates", &assignedclks, sizeof(assignedclks));
793 }
794 #endif
795
disable_gpu_nodes(void * blob)796 int disable_gpu_nodes(void *blob)
797 {
798 static const char * const nodes_path_8mn[] = {
799 "/gpu@38000000",
800 "/soc@/gpu@38000000"
801 };
802
803 return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn));
804 }
805
disable_npu_nodes(void * blob)806 int disable_npu_nodes(void *blob)
807 {
808 static const char * const nodes_path_8mp[] = {
809 "/vipsi@38500000"
810 };
811
812 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
813 }
814
disable_isp_nodes(void * blob)815 int disable_isp_nodes(void *blob)
816 {
817 static const char * const nodes_path_8mp[] = {
818 "/soc@0/bus@32c00000/camera/isp@32e10000",
819 "/soc@0/bus@32c00000/camera/isp@32e20000"
820 };
821
822 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
823 }
824
disable_dsp_nodes(void * blob)825 int disable_dsp_nodes(void *blob)
826 {
827 static const char * const nodes_path_8mp[] = {
828 "/dsp@3b6e8000"
829 };
830
831 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
832 }
833
disable_thermal_cpu_nodes(void * blob,u32 disabled_cores)834 static void disable_thermal_cpu_nodes(void *blob, u32 disabled_cores)
835 {
836 static const char * const thermal_path[] = {
837 "/thermal-zones/cpu-thermal/cooling-maps/map0"
838 };
839
840 int nodeoff, cnt, i, ret, j;
841 u32 cooling_dev[12];
842
843 for (i = 0; i < ARRAY_SIZE(thermal_path); i++) {
844 nodeoff = fdt_path_offset(blob, thermal_path[i]);
845 if (nodeoff < 0)
846 continue; /* Not found, skip it */
847
848 cnt = fdtdec_get_int_array_count(blob, nodeoff, "cooling-device", cooling_dev, 12);
849 if (cnt < 0)
850 continue;
851
852 if (cnt != 12)
853 printf("Warning: %s, cooling-device count %d\n", thermal_path[i], cnt);
854
855 for (j = 0; j < cnt; j++)
856 cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]);
857
858 ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev,
859 sizeof(u32) * (12 - disabled_cores * 3));
860 if (ret < 0) {
861 printf("Warning: %s, cooling-device setprop failed %d\n",
862 thermal_path[i], ret);
863 continue;
864 }
865
866 printf("Update node %s, cooling-device prop\n", thermal_path[i]);
867 }
868 }
869
disable_pmu_cpu_nodes(void * blob,u32 disabled_cores)870 static void disable_pmu_cpu_nodes(void *blob, u32 disabled_cores)
871 {
872 static const char * const pmu_path[] = {
873 "/pmu"
874 };
875
876 int nodeoff, cnt, i, ret, j;
877 u32 irq_affinity[4];
878
879 for (i = 0; i < ARRAY_SIZE(pmu_path); i++) {
880 nodeoff = fdt_path_offset(blob, pmu_path[i]);
881 if (nodeoff < 0)
882 continue; /* Not found, skip it */
883
884 cnt = fdtdec_get_int_array_count(blob, nodeoff, "interrupt-affinity",
885 irq_affinity, 4);
886 if (cnt < 0)
887 continue;
888
889 if (cnt != 4)
890 printf("Warning: %s, interrupt-affinity count %d\n", pmu_path[i], cnt);
891
892 for (j = 0; j < cnt; j++)
893 irq_affinity[j] = cpu_to_fdt32(irq_affinity[j]);
894
895 ret = fdt_setprop(blob, nodeoff, "interrupt-affinity", &irq_affinity,
896 sizeof(u32) * (4 - disabled_cores));
897 if (ret < 0) {
898 printf("Warning: %s, interrupt-affinity setprop failed %d\n",
899 pmu_path[i], ret);
900 continue;
901 }
902
903 printf("Update node %s, interrupt-affinity prop\n", pmu_path[i]);
904 }
905 }
906
disable_cpu_nodes(void * blob,u32 disabled_cores)907 static int disable_cpu_nodes(void *blob, u32 disabled_cores)
908 {
909 static const char * const nodes_path[] = {
910 "/cpus/cpu@1",
911 "/cpus/cpu@2",
912 "/cpus/cpu@3",
913 };
914 u32 i = 0;
915 int rc;
916 int nodeoff;
917
918 if (disabled_cores > 3)
919 return -EINVAL;
920
921 i = 3 - disabled_cores;
922
923 for (; i < 3; i++) {
924 nodeoff = fdt_path_offset(blob, nodes_path[i]);
925 if (nodeoff < 0)
926 continue; /* Not found, skip it */
927
928 debug("Found %s node\n", nodes_path[i]);
929
930 rc = fdt_del_node(blob, nodeoff);
931 if (rc < 0) {
932 printf("Unable to delete node %s, err=%s\n",
933 nodes_path[i], fdt_strerror(rc));
934 } else {
935 printf("Delete node %s\n", nodes_path[i]);
936 }
937 }
938
939 disable_thermal_cpu_nodes(blob, disabled_cores);
940 disable_pmu_cpu_nodes(blob, disabled_cores);
941
942 return 0;
943 }
944
ft_system_setup(void * blob,struct bd_info * bd)945 int ft_system_setup(void *blob, struct bd_info *bd)
946 {
947 #ifdef CONFIG_IMX8MQ
948 int i = 0;
949 int rc;
950 int nodeoff;
951
952 if (get_boot_device() == USB_BOOT) {
953 disable_dcss_nodes(blob);
954
955 bool new_path = check_fdt_new_path(blob);
956 int v = new_path ? 1 : 0;
957 static const char * const usb_dwc3_path[] = {
958 "/usb@38100000/dwc3",
959 "/soc@0/usb@38100000"
960 };
961
962 nodeoff = fdt_path_offset(blob, usb_dwc3_path[v]);
963 if (nodeoff >= 0) {
964 const char *speed = "high-speed";
965
966 printf("Found %s node\n", usb_dwc3_path[v]);
967
968 usb_modify_speed:
969
970 rc = fdt_setprop(blob, nodeoff, "maximum-speed", speed, strlen(speed) + 1);
971 if (rc) {
972 if (rc == -FDT_ERR_NOSPACE) {
973 rc = fdt_increase_size(blob, 512);
974 if (!rc)
975 goto usb_modify_speed;
976 }
977 printf("Unable to set property %s:%s, err=%s\n",
978 usb_dwc3_path[v], "maximum-speed", fdt_strerror(rc));
979 } else {
980 printf("Modify %s:%s = %s\n",
981 usb_dwc3_path[v], "maximum-speed", speed);
982 }
983 } else {
984 printf("Can't found %s node\n", usb_dwc3_path[v]);
985 }
986 }
987
988 /* Disable the CPU idle for A0 chip since the HW does not support it */
989 if (is_soc_rev(CHIP_REV_1_0)) {
990 static const char * const nodes_path[] = {
991 "/cpus/cpu@0",
992 "/cpus/cpu@1",
993 "/cpus/cpu@2",
994 "/cpus/cpu@3",
995 };
996
997 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
998 nodeoff = fdt_path_offset(blob, nodes_path[i]);
999 if (nodeoff < 0)
1000 continue; /* Not found, skip it */
1001
1002 debug("Found %s node\n", nodes_path[i]);
1003
1004 rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
1005 if (rc == -FDT_ERR_NOTFOUND)
1006 continue;
1007 if (rc) {
1008 printf("Unable to update property %s:%s, err=%s\n",
1009 nodes_path[i], "status", fdt_strerror(rc));
1010 return rc;
1011 }
1012
1013 debug("Remove %s:%s\n", nodes_path[i],
1014 "cpu-idle-states");
1015 }
1016 }
1017
1018 if (is_imx8mql()) {
1019 disable_vpu_nodes(blob);
1020 if (check_dcss_fused()) {
1021 printf("DCSS is fused\n");
1022 disable_dcss_nodes(blob);
1023 check_mipi_dsi_nodes(blob);
1024 }
1025 }
1026
1027 if (is_imx8md())
1028 disable_cpu_nodes(blob, 2);
1029
1030 #elif defined(CONFIG_IMX8MM)
1031 if (is_imx8mml() || is_imx8mmdl() || is_imx8mmsl())
1032 disable_vpu_nodes(blob);
1033
1034 if (is_imx8mmd() || is_imx8mmdl())
1035 disable_cpu_nodes(blob, 2);
1036 else if (is_imx8mms() || is_imx8mmsl())
1037 disable_cpu_nodes(blob, 3);
1038
1039 #elif defined(CONFIG_IMX8MN)
1040 if (is_imx8mnl() || is_imx8mndl() || is_imx8mnsl())
1041 disable_gpu_nodes(blob);
1042 #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
1043 else {
1044 int ldm_gpu = low_drive_gpu_freq(blob);
1045
1046 if (ldm_gpu < 0)
1047 printf("Update GPU node assigned-clock-rates failed\n");
1048 else
1049 printf("Update GPU node assigned-clock-rates ok\n");
1050 }
1051 #endif
1052
1053 if (is_imx8mnd() || is_imx8mndl() || is_imx8mnud())
1054 disable_cpu_nodes(blob, 2);
1055 else if (is_imx8mns() || is_imx8mnsl() || is_imx8mnus())
1056 disable_cpu_nodes(blob, 3);
1057
1058 #elif defined(CONFIG_IMX8MP)
1059 if (is_imx8mpl())
1060 disable_vpu_nodes(blob);
1061
1062 if (is_imx8mpl() || is_imx8mp6())
1063 disable_npu_nodes(blob);
1064
1065 if (is_imx8mpl())
1066 disable_isp_nodes(blob);
1067
1068 if (is_imx8mpl() || is_imx8mp6())
1069 disable_dsp_nodes(blob);
1070
1071 if (is_imx8mpd())
1072 disable_cpu_nodes(blob, 2);
1073 #endif
1074
1075 return 0;
1076 }
1077 #endif
1078
1079 #if !CONFIG_IS_ENABLED(SYSRESET)
reset_cpu(void)1080 void reset_cpu(void)
1081 {
1082 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
1083
1084 /* Clear WDA to trigger WDOG_B immediately */
1085 writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr);
1086
1087 while (1) {
1088 /*
1089 * spin for .5 seconds before reset
1090 */
1091 }
1092 }
1093 #endif
1094
1095 #if defined(CONFIG_ARCH_MISC_INIT)
acquire_buildinfo(void)1096 static void acquire_buildinfo(void)
1097 {
1098 u64 atf_commit = 0;
1099 struct arm_smccc_res res;
1100
1101 /* Get ARM Trusted Firmware commit id */
1102 arm_smccc_smc(IMX_SIP_BUILDINFO, IMX_SIP_BUILDINFO_GET_COMMITHASH,
1103 0, 0, 0, 0, 0, 0, &res);
1104 atf_commit = res.a0;
1105 if (atf_commit == 0xffffffff) {
1106 debug("ATF does not support build info\n");
1107 atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */
1108 }
1109
1110 printf("\n BuildInfo:\n - ATF %s\n\n", (char *)&atf_commit);
1111 }
1112
arch_misc_init(void)1113 int arch_misc_init(void)
1114 {
1115 acquire_buildinfo();
1116
1117 return 0;
1118 }
1119 #endif
1120
imx_tmu_arch_init(void * reg_base)1121 void imx_tmu_arch_init(void *reg_base)
1122 {
1123 if (is_imx8mm() || is_imx8mn()) {
1124 /* Load TCALIV and TASR from fuses */
1125 struct ocotp_regs *ocotp =
1126 (struct ocotp_regs *)OCOTP_BASE_ADDR;
1127 struct fuse_bank *bank = &ocotp->bank[3];
1128 struct fuse_bank3_regs *fuse =
1129 (struct fuse_bank3_regs *)bank->fuse_regs;
1130
1131 u32 tca_rt, tca_hr, tca_en;
1132 u32 buf_vref, buf_slope;
1133
1134 tca_rt = fuse->ana0 & 0xFF;
1135 tca_hr = (fuse->ana0 & 0xFF00) >> 8;
1136 tca_en = (fuse->ana0 & 0x2000000) >> 25;
1137
1138 buf_vref = (fuse->ana0 & 0x1F00000) >> 20;
1139 buf_slope = (fuse->ana0 & 0xF0000) >> 16;
1140
1141 writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
1142 writel((tca_en << 31) | (tca_hr << 16) | tca_rt,
1143 (ulong)reg_base + 0x30);
1144 }
1145 #ifdef CONFIG_IMX8MP
1146 /* Load TCALIV0/1/m40 and TRIM from fuses */
1147 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
1148 struct fuse_bank *bank = &ocotp->bank[38];
1149 struct fuse_bank38_regs *fuse =
1150 (struct fuse_bank38_regs *)bank->fuse_regs;
1151 struct fuse_bank *bank2 = &ocotp->bank[39];
1152 struct fuse_bank39_regs *fuse2 =
1153 (struct fuse_bank39_regs *)bank2->fuse_regs;
1154 u32 buf_vref, buf_slope, bjt_cur, vlsb, bgr;
1155 u32 reg;
1156 u32 tca40[2], tca25[2], tca105[2];
1157
1158 /* For blank sample */
1159 if (!fuse->ana_trim2 && !fuse->ana_trim3 &&
1160 !fuse->ana_trim4 && !fuse2->ana_trim5) {
1161 /* Use a default 25C binary codes */
1162 tca25[0] = 1596;
1163 tca25[1] = 1596;
1164 writel(tca25[0], (ulong)reg_base + 0x30);
1165 writel(tca25[1], (ulong)reg_base + 0x34);
1166 return;
1167 }
1168
1169 buf_vref = (fuse->ana_trim2 & 0xc0) >> 6;
1170 buf_slope = (fuse->ana_trim2 & 0xF00) >> 8;
1171 bjt_cur = (fuse->ana_trim2 & 0xF000) >> 12;
1172 bgr = (fuse->ana_trim2 & 0xF0000) >> 16;
1173 vlsb = (fuse->ana_trim2 & 0xF00000) >> 20;
1174 writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
1175
1176 reg = (bgr << 28) | (bjt_cur << 20) | (vlsb << 12) | (1 << 7);
1177 writel(reg, (ulong)reg_base + 0x3c);
1178
1179 tca40[0] = (fuse->ana_trim3 & 0xFFF0000) >> 16;
1180 tca25[0] = (fuse->ana_trim3 & 0xF0000000) >> 28;
1181 tca25[0] |= ((fuse->ana_trim4 & 0xFF) << 4);
1182 tca105[0] = (fuse->ana_trim4 & 0xFFF00) >> 8;
1183 tca40[1] = (fuse->ana_trim4 & 0xFFF00000) >> 20;
1184 tca25[1] = fuse2->ana_trim5 & 0xFFF;
1185 tca105[1] = (fuse2->ana_trim5 & 0xFFF000) >> 12;
1186
1187 /* use 25c for 1p calibration */
1188 writel(tca25[0] | (tca105[0] << 16), (ulong)reg_base + 0x30);
1189 writel(tca25[1] | (tca105[1] << 16), (ulong)reg_base + 0x34);
1190 writel(tca40[0] | (tca40[1] << 16), (ulong)reg_base + 0x38);
1191 #endif
1192 }
1193
1194 #if defined(CONFIG_SPL_BUILD)
1195 #if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
1196 bool serror_need_skip = true;
1197
do_error(struct pt_regs * pt_regs,unsigned int esr)1198 void do_error(struct pt_regs *pt_regs, unsigned int esr)
1199 {
1200 /*
1201 * If stack is still in ROM reserved OCRAM not switch to SPL,
1202 * it is the ROM SError
1203 */
1204 ulong sp;
1205
1206 asm volatile("mov %0, sp" : "=r"(sp) : );
1207
1208 if (serror_need_skip && sp < 0x910000 && sp >= 0x900000) {
1209 /* Check for ERR050342, imx8mq HDCP enabled parts */
1210 if (is_imx8mq() && !(readl(OCOTP_BASE_ADDR + 0x450) & 0x08000000)) {
1211 serror_need_skip = false;
1212 return; /* Do nothing skip the SError in ROM */
1213 }
1214
1215 /* Check for ERR050350, field return mode for imx8mq, mm and mn */
1216 if (readl(OCOTP_BASE_ADDR + 0x630) & 0x1) {
1217 serror_need_skip = false;
1218 return; /* Do nothing skip the SError in ROM */
1219 }
1220 }
1221
1222 efi_restore_gd();
1223 printf("\"Error\" handler, esr 0x%08x\n", esr);
1224 show_regs(pt_regs);
1225 panic("Resetting CPU ...\n");
1226 }
1227 #endif
1228 #endif
1229
1230 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
env_get_location(enum env_operation op,int prio)1231 enum env_location env_get_location(enum env_operation op, int prio)
1232 {
1233 enum boot_device dev = get_boot_device();
1234 enum env_location env_loc = ENVL_UNKNOWN;
1235
1236 if (prio)
1237 return env_loc;
1238
1239 switch (dev) {
1240 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
1241 case QSPI_BOOT:
1242 env_loc = ENVL_SPI_FLASH;
1243 break;
1244 #endif
1245 #ifdef CONFIG_ENV_IS_IN_NAND
1246 case NAND_BOOT:
1247 env_loc = ENVL_NAND;
1248 break;
1249 #endif
1250 #ifdef CONFIG_ENV_IS_IN_MMC
1251 case SD1_BOOT:
1252 case SD2_BOOT:
1253 case SD3_BOOT:
1254 case MMC1_BOOT:
1255 case MMC2_BOOT:
1256 case MMC3_BOOT:
1257 env_loc = ENVL_MMC;
1258 break;
1259 #endif
1260 default:
1261 #if defined(CONFIG_ENV_IS_NOWHERE)
1262 env_loc = ENVL_NOWHERE;
1263 #endif
1264 break;
1265 }
1266
1267 return env_loc;
1268 }
1269
1270 #ifndef ENV_IS_EMBEDDED
env_get_offset(long long defautl_offset)1271 long long env_get_offset(long long defautl_offset)
1272 {
1273 enum boot_device dev = get_boot_device();
1274
1275 switch (dev) {
1276 case NAND_BOOT:
1277 return (60 << 20); /* 60MB offset for NAND */
1278 default:
1279 break;
1280 }
1281
1282 return defautl_offset;
1283 }
1284 #endif
1285 #endif
1286