README.P1010RDB-PA
1Overview
2=========
3The P1010RDB is a Freescale reference design board that hosts the P1010 SoC.
4
5The P1010 is a cost-effective, low-power, highly integrated host processor
6based on a Power Architecture e500v2 core (maximum core frequency 800/1000 MHz),
7that addresses the requirements of several routing, gateways, storage, consumer,
8and industrial applications. Applications of interest include the main CPUs and
9I/O processors in network attached storage (NAS), the voice over IP (VoIP)
10router/gateway, and wireless LAN (WLAN) and industrial controllers.
11
12The P1010RDB board features are as follows:
13Memory subsystem:
14 - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
15 - 32 Mbyte NOR flash single-chip memory
16 - 32 Mbyte NAND flash memory
17 - 256 Kbit M24256 I2C EEPROM
18 - 16 Mbyte SPI memory
19 - I2C Board EEPROM 128x8 bit memory
20 - SD/MMC connector to interface with the SD memory card
21Interfaces:
22 - PCIe:
23 - Lane0: x1 mini-PCIe slot
24 - Lane1: x1 PCIe standard slot
25 - SATA:
26 - 1 internal SATA connector to 2.5” 160G SATA2 HDD
27 - 1 eSATA connector to rear panel
28 - 10/100/1000 BaseT Ethernet ports:
29 - eTSEC1, RGMII: one 10/100/1000 port using Vitesse VSC8641XKO
30 - eTSEC2, SGMII: one 10/100/1000 port using Vitesse VSC8221
31 - eTSEC3, SGMII: one 10/100/1000 port using Vitesse VSC8221
32 - USB 2.0 port:
33 - x1 USB2.0 port via an external ULPI PHY to micro-AB connector
34 - x1 USB2.0 port via an internal UTMI PHY to micro-AB connector
35 - FlexCAN ports:
36 - 2 DB-9 female connectors for FlexCAN bus(revision 2.0B)
37 interface;
38 - DUART interface:
39 - DUART interface: supports two UARTs up to 115200 bps for
40 console display
41 - RJ45 connectors are used for these 2 UART ports.
42 - TDM
43 - 2 FXS ports connected via an external SLIC to the TDM interface.
44 SLIC is controllled via SPI.
45 - 1 FXO port connected via a relay to FXS for switchover to POTS
46Board connectors:
47 - Mini-ITX power supply connector
48 - JTAG/COP for debugging
49IEEE Std. 1588 signals for test and measurement
50Real-time clock on I2C bus
51POR
52 - support critical POR setting changed via switch on board
53PCB
54 - 6-layer routing (4-layer signals, 2-layer power and ground)
55
56
57Physical Memory Map on P1010RDB
58===============================
59Address Start Address End Memory type Attributes
600x0000_0000 0x3fff_ffff DDR 1G Cacheable
610xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
620xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable
630xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
640xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable
650xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
660xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0
670xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
68
69
70Serial Port Configuration on P1010RDB
71=====================================
72Configure the serial port of the attached computer with the following values:
73 -Data rate: 115200 bps
74 -Number of data bits: 8
75 -Parity: None
76 -Number of Stop bits: 1
77 -Flow Control: Hardware/None
78
79
80Settings of DIP-switch
81======================
82 SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash
83 SW4[1:4]= 1000 and SW6[4]=1 for boot from 8bit NAND flash
84 SW4[1:4]= 0110 and SW6[4]=0 for boot from SPI flash
85Note: 1 stands for 'on', 0 stands for 'off'
86
87
88Setting of hwconfig
89===================
90If FlexCAN or TDM is needed, please set "fsl_p1010mux:tdm_can=can" or
91"fsl_p1010mux:tdm_can=tdm" explicitly in u-boot prompt as below for example:
92setenv hwconfig "fsl_p1010mux:tdm_can=tdm;usb1:dr_mode=host,phy_type=utmi"
93By default, don't set fsl_p1010mux:tdm_can, in this case, spi chip selection
94is set to spi-flash instead of to SLIC/TDM/DAC and tdm_can_sel is set to TDM
95instead of to CAN/UART1.
96
97
98Build and burn U-Boot to NOR flash
99==================================
1001. Build u-boot.bin image
101 export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
102 make P1010RDB_NOR
103
1042. Burn u-boot.bin into NOR flash
105 => tftp $loadaddr $uboot
106 => protect off eff40000 +$filesize
107 => erase eff40000 +$filesize
108 => cp.b $loadaddr eff40000 $filesize
109
1103. Check SW4[1:4]= 1111 and SW6[4]=0, then power on.
111
112
113Alternate NOR bank
114==================
1151. Burn u-boot.bin into alternate NOR bank
116 => tftp $loadaddr $uboot
117 => protect off eef40000 +$filesize
118 => erase eef40000 +$filesize
119 => cp.b $loadaddr eef40000 $filesize
120
1212. Switch to alternate NOR bank
122 => mw.b ffb00009 1
123 => reset
124 or set SW1[8]= ON
125
126SW1[8]= OFF: Upper bank used for booting start
127SW1[8]= ON: Lower bank used for booting start
128CPLD NOR bank selection register address 0xFFB00009 Bit[0]:
1290 - boot from upper 4 sectors
1301 - boot from lower 4 sectors
131
132
133Build and burn U-Boot to NAND flash
134===================================
1351. Build u-boot.bin image
136 export ARCH=powerpc
137 export CROSS_COMPILE=/your_path/powerpc-linux-gnu-
138 make P1010RDB_NAND
139
1402. Burn u-boot-nand.bin into NAND flash
141 => tftp $loadaddr $uboot-nand
142 => nand erase 0 $filesize
143 => nand write $loadaddr 0 $filesize
144
1453. Check SW4[1:4]= 1000 and SW6[4]=1, then power on.
146
147
148Build and burn U-Boot to SPI flash
149==================================
1501. Build u-boot-spi.bin image
151 make P1010RDB_SPIFLASH_config; make
152 Boot up kernel with rootfs.ext2.gz.uboot.p1010rdb
153 Download u-boot.bin to linux and you can find some config files
154 under /usr/share such as config_xx.dat. Do below command:
155 boot_format config_ddr3_1gb_p1010rdb_800M.dat u-boot.bin -spi \
156 u-boot-spi.bin
157 to generate u-boot-spi.bin.
158
1592. Burn u-boot-spi.bin into SPI flash
160 => tftp $loadaddr $uboot-spi
161 => sf erase 0 100000
162 => sf write $loadaddr 0 $filesize
163
1643. Check SW4[1:4]= 0110 and SW6[4]=0, then power on.
165
166
167CPLD POR setting registers
168==========================
1691. Set POR switch selection register (addr 0xFFB00011) to 0.
1702. Write CPLD POR registers (BCSR0~BCSR3, addr 0xFFB00014~0xFFB00017) with
171 proper values.
172 If change boot ROM location to NOR or NAND flash, need write the IFC_CS0
173 switch command by I2C.
1743. Send reset command.
175 After reset, the new POR setting will be implemented.
176
177Two examples are given in below:
178Switch from NOR to NAND boot with default frequency:
179 => i2c dev 0
180 => i2c mw 18 1 f9
181 => i2c mw 18 3 f0
182 => mw.b ffb00011 0
183 => mw.b ffb00017 1
184 => reset
185Switch from NAND to NOR boot with Core/CCB/DDR (800/400/667 MHz):
186 => i2c dev 0
187 => i2c mw 18 1 f1
188 => i2c mw 18 3 f0
189 => mw.b ffb00011 0
190 => mw.b ffb00014 2
191 => mw.b ffb00015 5
192 => mw.b ffb00016 3
193 => mw.b ffb00017 f
194 => reset
195
196
197Boot Linux from network using TFTP on P1010RDB
198==============================================
199Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.
200 => tftp 1000000 uImage
201 => tftp 2000000 p1010rdb.dtb
202 => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
203 => bootm 1000000 3000000 2000000
204
205
206For more details, please refer to P1010RDB User Guide and access website
207www.freescale.com
208
README.P1010RDB-PB
1Overview
2=========
3The P1010RDB-PB is a Freescale Reference Design Board that hosts the P1010 SoC.
4P1010RDB-PB is a variation of previous P1010RDB-PA board.
5
6The P1010 is a cost-effective, low-power, highly integrated host processor
7based on a Power Architecture e500v2 core (maximum core frequency 1GHz),that
8addresses the requirements of several routing, gateways, storage, consumer,
9and industrial applications. Applications of interest include the main CPUs and
10I/O processors in network attached storage (NAS), the voice over IP (VoIP)
11router/gateway, and wireless LAN (WLAN) and industrial controllers.
12
13The P1010RDB-PB board features are as following:
14Memory subsystem:
15 - 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus)
16 - 32M bytes NOR flash single-chip memory
17 - 2G bytes NAND flash memory
18 - 16M bytes SPI memory
19 - 256K bit M24256 I2C EEPROM
20 - I2C Board EEPROM 128x8 bit memory
21 - SD/MMC connector to interface with the SD memory card
22Interfaces:
23 - Three 10/100/1000 BaseT Ethernet ports (One RGMII and two SGMII)
24 - PCIe 2.0: two x1 mini-PCIe slots
25 - SATA 2.0: two SATA interfaces
26 - USB 2.0: one USB interface
27 - FlexCAN: two FlexCAN interfaces (revision 2.0B)
28 - UART: one USB-to-Serial interface
29 - TDM: 2 FXS ports connected via an external SLIC to the TDM interface.
30 1 FXO port connected via a relay to FXS for switchover to POTS
31
32Board connectors:
33 - Mini-ITX power supply connector
34 - JTAG/COP for debugging
35
36POR: support critical POR setting changed via switch on board
37PCB: 6-layer routing (4-layer signals, 2-layer power and ground)
38
39Physical Memory Map on P1010RDB
40===============================
41Address Start Address End Memory type Attributes
420x0000_0000 0x3fff_ffff DDR 1G Cacheable
430xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
440xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable
450xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
460xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable
470xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
480xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0
490xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
50
51
52Serial Port Configuration on P1010RDB
53=====================================
54Configure the serial port of the attached computer with the following values:
55 -Data rate: 115200 bps
56 -Number of data bits: 8
57 -Parity: None
58 -Number of Stop bits: 1
59 -Flow Control: Hardware/None
60
61
62P1010RDB-PB default DIP-switch settings
63=======================================
64SW1[1:8]= 10101010
65SW2[1:8]= 11011000
66SW3[1:8]= 10010000
67SW4[1:4]= 1010
68SW5[1:8]= 11111010
69
70
71P1010RDB-PB boot mode settings via DIP-switch
72=============================================
73SW4[1:4]= 1111 and SW3[3:4]= 00 for 16bit NOR boot
74SW4[1:4]= 1010 and SW3[3:4]= 01 for 8bit NAND boot
75SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot
76SW4[1:4]= 0111 and SW3[3:4]= 10 for SD boot
77Note: 1 stands for 'on', 0 stands for 'off'
78
79
80Switch P1010RDB-PB boot mode via software without setting DIP-switch
81====================================================================
82=> run boot_bank0 (boot from NOR bank0)
83=> run boot_bank1 (boot from NOR bank1)
84=> run boot_nand (boot from NAND flash)
85=> run boot_spi (boot from SPI flash)
86=> run boot_sd (boot from SD card)
87
88
89Frequency combination support on P1010RDB-PB
90=============================================
91SW1[4:7] SW5[1] SW5[5:8] SW2[2] Core(MHz) Platform(MHz) DDR(MT/s)
920101 1 1010 0 800 400 800
931001 1 1010 0 800 400 667
941010 1 1100 0 667 333 667
951000 0 1010 0 533 266 667
960101 1 1010 1 1000 400 800
971001 1 1010 1 1000 400 667
98
99
100Setting of pin mux
101==================
102Since pins multiplexing, TDM and CAN are muxed with SPI flash.
103SDHC is muxed with IFC. IFC and SPI flash are enabled by default.
104
105To enable TDM:
106=> setenv hwconfig fsl_p1010mux:tdm_can=tdm
107=> save;reset
108
109To enable FlexCAN:
110=> setenv hwconfig fsl_p1010mux:tdm_can=can
111=> save;reset
112
113To enable SDHC in case of NOR/NAND/SPI boot
114 a) For temporary use case in runtime without reboot system
115 run 'mux sdhc' in U-Boot to validate SDHC with invalidating IFC.
116
117 b) For long-term use case
118 set 'esdhc' in hwconfig and save it.
119
120To enable IFC in case of SD boot
121 a) For temporary use case in runtime without reboot system
122 run 'mux ifc' in U-Boot to validate IFC with invalidating SDHC.
123
124 b) For long-term use case
125 set 'ifc' in hwconfig and save it.
126
127
128Build images for different boot mode
129====================================
130First setup cross compile environment on build host
131 $ export CROSS_COMPILE=<your-compiler-path>/powerpc-linux-gnu-
132
1331. For NOR boot
134 $ make P1010RDB-PB_NOR
135
1362. For NAND boot
137 $ make P1010RDB-PB_NAND
138
1393. For SPI boot
140 $ make P1010RDB-PB_SPIFLASH
141
1424. For SD boot
143 $ make P1010RDB-PB_SDCARD
144
145
146Steps to program images to flash for different boot mode
147========================================================
1481. NOR boot
149 => tftp 1000000 u-boot.bin
150 For bank0
151 => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
152 set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
153
154 For bank1
155 => pro off all;era eef40000 eeffffff;cp.b 1000000 eef40000 $filesize
156 set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
157
1582. NAND boot
159 => tftp 1000000 u-boot-nand.bin
160 => nand erase 0 $filesize; nand write $loadaddr 0 $filesize
161 Set SW4[1:4]= 1010 and SW3[3:4]= 01, then power on the board
162
1633. SPI boot
164 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-spi-combined.bin
165 2) => tftp 1000000 u-boot-spi-combined.bin
166 3) => sf probe 0; sf erase 0 100000; sf write 1000000 0 100000
167 set SW4[1:4]= 0110 and SW3[3:4]= 00, then power on the board
168
1694. SD boot
170 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-sd-combined.bin
171 2) => tftp 1000000 u-boot-sd-combined.bin
172 3) => mux sdhc
173 4) => mmc write 1000000 0 1050
174 set SW4[1:4]= 0111 and SW3[3:4]= 10, then power on the board
175
176
177Boot Linux from network using TFTP on P1010RDB-PB
178=================================================
179Place uImage, p1010rdb.dtb and rootfs files in the TFTP download path.
180 => tftp 1000000 uImage
181 => tftp 2000000 p1010rdb.dtb
182 => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
183 => bootm 1000000 3000000 2000000
184
185
186For more details, please refer to P1010RDB-PB User Guide and access website
187www.freescale.com and Freescale QorIQ SDK Infocenter document.
188