1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Cadence DDR Driver 4 * 5 * Copyright (C) 2012-2021 Cadence Design Systems, Inc. 6 * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ 7 */ 8 9 #ifndef LPDDR4_32BIT_IF_H 10 #define LPDDR4_32BIT_IF_H 11 12 #include <linux/types.h> 13 14 #define LPDDR4_INTR_MAX_CS (2U) 15 16 #define LPDDR4_INTR_CTL_REG_COUNT (459U) 17 18 #define LPDDR4_INTR_PHY_INDEP_REG_COUNT (300U) 19 20 #define LPDDR4_INTR_PHY_REG_COUNT (1423U) 21 22 typedef enum { 23 LPDDR4_INTR_RESET_DONE = 0U, 24 LPDDR4_INTR_BUS_ACCESS_ERROR = 1U, 25 LPDDR4_INTR_MULTIPLE_BUS_ACCESS_ERROR = 2U, 26 LPDDR4_INTR_ECC_MULTIPLE_CORR_ERROR = 3U, 27 LPDDR4_INTR_ECC_MULTIPLE_UNCORR_ERROR = 4U, 28 LPDDR4_INTR_ECC_WRITEBACK_EXEC_ERROR = 5U, 29 LPDDR4_INTR_ECC_SCRUB_DONE = 6U, 30 LPDDR4_INTR_ECC_SCRUB_ERROR = 7U, 31 LPDDR4_INTR_PORT_COMMAND_ERROR = 8U, 32 LPDDR4_INTR_MC_INIT_DONE = 9U, 33 LPDDR4_INTR_LP_DONE = 10U, 34 LPDDR4_INTR_BIST_DONE = 11U, 35 LPDDR4_INTR_WRAP_ERROR = 12U, 36 LPDDR4_INTR_INVALID_BURST_ERROR = 13U, 37 LPDDR4_INTR_RDLVL_ERROR = 14U, 38 LPDDR4_INTR_RDLVL_GATE_ERROR = 15U, 39 LPDDR4_INTR_WRLVL_ERROR = 16U, 40 LPDDR4_INTR_CA_TRAINING_ERROR = 17U, 41 LPDDR4_INTR_DFI_UPDATE_ERROR = 18U, 42 LPDDR4_INTR_MRR_ERROR = 19U, 43 LPDDR4_INTR_PHY_MASTER_ERROR = 20U, 44 LPDDR4_INTR_WRLVL_REQ = 21U, 45 LPDDR4_INTR_RDLVL_REQ = 22U, 46 LPDDR4_INTR_RDLVL_GATE_REQ = 23U, 47 LPDDR4_INTR_CA_TRAINING_REQ = 24U, 48 LPDDR4_INTR_LEVELING_DONE = 25U, 49 LPDDR4_INTR_PHY_ERROR = 26U, 50 LPDDR4_INTR_MR_READ_DONE = 27U, 51 LPDDR4_INTR_TEMP_CHANGE = 28U, 52 LPDDR4_INTR_TEMP_ALERT = 29U, 53 LPDDR4_INTR_SW_DQS_COMPLETE = 30U, 54 LPDDR4_INTR_DQS_OSC_BV_UPDATED = 31U, 55 LPDDR4_INTR_DQS_OSC_OVERFLOW = 32U, 56 LPDDR4_INTR_DQS_OSC_VAR_OUT = 33U, 57 LPDDR4_INTR_MR_WRITE_DONE = 34U, 58 LPDDR4_INTR_INHIBIT_DRAM_DONE = 35U, 59 LPDDR4_INTR_DFI_INIT_STATE = 36U, 60 LPDDR4_INTR_DLL_RESYNC_DONE = 37U, 61 LPDDR4_INTR_TDFI_TO = 38U, 62 LPDDR4_INTR_DFS_DONE = 39U, 63 LPDDR4_INTR_DFS_STATUS = 40U, 64 LPDDR4_INTR_REFRESH_STATUS = 41U, 65 LPDDR4_INTR_ZQ_STATUS = 42U, 66 LPDDR4_INTR_SW_REQ_MODE = 43U, 67 LPDDR4_INTR_LOR_BITS = 44U 68 } lpddr4_intr_ctlinterrupt; 69 70 typedef enum { 71 LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT = 0U, 72 LPDDR4_INTR_PHY_INDEP_CONTROL_ERROR_BIT = 1U, 73 LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT = 2U, 74 LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT = 3U, 75 LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT = 4U, 76 LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT = 5U, 77 LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT = 6U, 78 LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT = 7U, 79 LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT = 8U, 80 LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT = 9U, 81 LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT = 10U, 82 LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT = 11U, 83 LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT = 12U, 84 LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT = 13U, 85 LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT = 14U, 86 LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT = 15U, 87 LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT = 16U, 88 LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 17U 89 } lpddr4_intr_phyindepinterrupt; 90 91 #endif /* LPDDR4_32BIT_IF_H */ 92