1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 * Copyright 2020-2021 NXP 5 */ 6 7 /* 8 * T4240 RDB board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include <linux/stringify.h> 14 15 #define CONFIG_FSL_SATA_V2 16 #define CONFIG_PCIE4 17 18 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 19 20 #ifdef CONFIG_RAMBOOT_PBL 21 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg 22 #ifndef CONFIG_SDCARD 23 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 25 #else 26 #define CONFIG_SPL_FLUSH_IMAGE 27 #define CONFIG_SPL_PAD_TO 0x40000 28 #define CONFIG_SPL_MAX_SIZE 0x28000 29 #define RESET_VECTOR_OFFSET 0x27FFC 30 #define BOOT_PAGE_OFFSET 0x27000 31 32 #ifdef CONFIG_SDCARD 33 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 34 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 35 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 36 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 37 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 38 #ifndef CONFIG_SPL_BUILD 39 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 40 #endif 41 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg 42 #endif 43 44 #ifdef CONFIG_SPL_BUILD 45 #define CONFIG_SPL_SKIP_RELOCATE 46 #define CONFIG_SPL_COMMON_INIT_DDR 47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 48 #endif 49 50 #endif 51 #endif /* CONFIG_RAMBOOT_PBL */ 52 53 #define CONFIG_DDR_ECC 54 55 /* High Level Configuration Options */ 56 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 57 58 #ifndef CONFIG_RESET_VECTOR_ADDRESS 59 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 60 #endif 61 62 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 63 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 64 #define CONFIG_PCIE1 /* PCIE controller 1 */ 65 #define CONFIG_PCIE2 /* PCIE controller 2 */ 66 #define CONFIG_PCIE3 /* PCIE controller 3 */ 67 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 68 69 /* 70 * These can be toggled for performance analysis, otherwise use default. 71 */ 72 #define CONFIG_SYS_CACHE_STASHING 73 #define CONFIG_BTB /* toggle branch predition */ 74 #ifdef CONFIG_DDR_ECC 75 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 76 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 77 #endif 78 79 #define CONFIG_ENABLE_36BIT_PHYS 80 81 /* 82 * Config the L3 Cache as L3 SRAM 83 */ 84 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 85 #define CONFIG_SYS_L3_SIZE (512 << 10) 86 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 87 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 88 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 89 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 90 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 91 92 #define CONFIG_SYS_DCSRBAR 0xf0000000 93 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 94 95 /* 96 * DDR Setup 97 */ 98 #define CONFIG_VERY_BIG_RAM 99 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 100 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 101 102 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 103 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 104 105 #define CONFIG_DDR_SPD 106 107 /* 108 * IFC Definitions 109 */ 110 #define CONFIG_SYS_FLASH_BASE 0xe0000000 111 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 112 113 #ifdef CONFIG_SPL_BUILD 114 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 115 #else 116 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 117 #endif 118 119 #define CONFIG_HWCONFIG 120 121 /* define to use L1 as initial stack */ 122 #define CONFIG_L1_INIT_RAM 123 #define CONFIG_SYS_INIT_RAM_LOCK 124 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 125 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 126 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 127 /* The assembler doesn't like typecast */ 128 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 129 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 130 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 131 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 132 133 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 134 GENERATED_GBL_DATA_SIZE) 135 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 136 137 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 138 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 139 140 /* Serial Port - controlled on board with jumper J8 141 * open - index 2 142 * shorted - index 1 143 */ 144 #define CONFIG_SYS_NS16550_SERIAL 145 #define CONFIG_SYS_NS16550_REG_SIZE 1 146 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 147 148 #define CONFIG_SYS_BAUDRATE_TABLE \ 149 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 150 151 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 152 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 153 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 154 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 155 156 /* I2C */ 157 #if !CONFIG_IS_ENABLED(DM_I2C) 158 #define CONFIG_SYS_I2C 159 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 160 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 161 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 162 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 163 #else 164 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM 165 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 166 #endif 167 168 #define CONFIG_SYS_I2C_FSL 169 170 /* 171 * General PCI 172 * Memory space is mapped 1-1, but I/O space must start from 0. 173 */ 174 175 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 176 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 177 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 178 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 179 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 180 181 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 182 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 183 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 184 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 185 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 186 187 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 188 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 189 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 190 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 191 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 192 193 /* controller 4, Base address 203000 */ 194 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 195 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 196 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 197 198 #ifdef CONFIG_PCI 199 #if !defined(CONFIG_DM_PCI) 200 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 201 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 202 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 203 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 204 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 205 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 206 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 207 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 208 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 209 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 210 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 211 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 212 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 213 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 214 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 215 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 216 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 217 #define CONFIG_PCI_INDIRECT_BRIDGE 218 #endif 219 220 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 221 #endif /* CONFIG_PCI */ 222 223 /* SATA */ 224 #ifdef CONFIG_FSL_SATA_V2 225 #define CONFIG_SYS_SATA_MAX_DEVICE 2 226 #define CONFIG_SATA1 227 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 228 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 229 #define CONFIG_SATA2 230 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 231 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 232 233 #define CONFIG_LBA48 234 #endif 235 236 #ifdef CONFIG_FMAN_ENET 237 #define CONFIG_ETHPRIME "FM1@DTSEC1" 238 #endif 239 240 /* 241 * Environment 242 */ 243 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 244 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 245 246 /* 247 * Miscellaneous configurable options 248 */ 249 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 250 251 /* 252 * For booting Linux, the board info and command line data 253 * have to be in the first 64 MB of memory, since this is 254 * the maximum mapped by the Linux kernel during initialization. 255 */ 256 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 257 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 258 259 #ifdef CONFIG_CMD_KGDB 260 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 261 #endif 262 263 /* 264 * Environment Configuration 265 */ 266 #define CONFIG_ROOTPATH "/opt/nfsroot" 267 #define CONFIG_BOOTFILE "uImage" 268 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 269 270 /* default location for tftp and bootm */ 271 #define CONFIG_LOADADDR 1000000 272 273 #define CONFIG_HVBOOT \ 274 "setenv bootargs config-addr=0x60000000; " \ 275 "bootm 0x01000000 - 0x00f00000" 276 277 #define CONFIG_SYS_CLK_FREQ 66666666 278 #define CONFIG_DDR_CLK_FREQ 133333333 279 280 #ifndef __ASSEMBLY__ 281 unsigned long get_board_sys_clk(void); 282 unsigned long get_board_ddr_clk(void); 283 #endif 284 285 /* 286 * DDR Setup 287 */ 288 #define CONFIG_SYS_SPD_BUS_NUM 0 289 #define SPD_EEPROM_ADDRESS1 0x52 290 #define SPD_EEPROM_ADDRESS2 0x54 291 #define SPD_EEPROM_ADDRESS3 0x56 292 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 293 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 294 295 /* 296 * IFC Definitions 297 */ 298 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 299 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 300 + 0x8000000) | \ 301 CSPR_PORT_SIZE_16 | \ 302 CSPR_MSEL_NOR | \ 303 CSPR_V) 304 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 305 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 306 CSPR_PORT_SIZE_16 | \ 307 CSPR_MSEL_NOR | \ 308 CSPR_V) 309 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 310 /* NOR Flash Timing Params */ 311 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 312 313 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 314 FTIM0_NOR_TEADC(0x5) | \ 315 FTIM0_NOR_TEAHC(0x5)) 316 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 317 FTIM1_NOR_TRAD_NOR(0x1A) |\ 318 FTIM1_NOR_TSEQRAD_NOR(0x13)) 319 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 320 FTIM2_NOR_TCH(0x4) | \ 321 FTIM2_NOR_TWPH(0x0E) | \ 322 FTIM2_NOR_TWP(0x1c)) 323 #define CONFIG_SYS_NOR_FTIM3 0x0 324 325 #define CONFIG_SYS_FLASH_QUIET_TEST 326 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 327 328 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 329 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 330 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 331 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 332 333 #define CONFIG_SYS_FLASH_EMPTY_INFO 334 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 335 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 336 337 /* NAND Flash on IFC */ 338 #define CONFIG_NAND_FSL_IFC 339 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 340 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 341 #define CONFIG_SYS_NAND_BASE 0xff800000 342 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 343 344 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 345 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 346 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 347 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 348 | CSPR_V) 349 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 350 351 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 352 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 353 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 354 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 355 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 356 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 357 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ 358 359 #define CONFIG_SYS_NAND_ONFI_DETECTION 360 361 /* ONFI NAND Flash mode0 Timing Params */ 362 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 363 FTIM0_NAND_TWP(0x18) | \ 364 FTIM0_NAND_TWCHT(0x07) | \ 365 FTIM0_NAND_TWH(0x0a)) 366 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 367 FTIM1_NAND_TWBE(0x39) | \ 368 FTIM1_NAND_TRR(0x0e) | \ 369 FTIM1_NAND_TRP(0x18)) 370 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 371 FTIM2_NAND_TREH(0x0a) | \ 372 FTIM2_NAND_TWHRE(0x1e)) 373 #define CONFIG_SYS_NAND_FTIM3 0x0 374 375 #define CONFIG_SYS_NAND_DDR_LAW 11 376 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 377 #define CONFIG_SYS_MAX_NAND_DEVICE 1 378 379 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 380 381 #if defined(CONFIG_MTD_RAW_NAND) 382 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 383 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 384 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 385 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 386 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 387 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 388 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 389 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 390 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 391 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 392 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 393 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 394 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 395 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 396 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 397 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 398 #else 399 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 400 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 401 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 402 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 403 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 404 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 405 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 406 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 407 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 408 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 409 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 410 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 411 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 412 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 413 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 414 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 415 #endif 416 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 417 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 418 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 419 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 420 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 421 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 422 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 423 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 424 425 /* CPLD on IFC */ 426 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 427 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 428 #define CONFIG_SYS_CSPR3_EXT (0xf) 429 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 430 | CSPR_PORT_SIZE_8 \ 431 | CSPR_MSEL_GPCM \ 432 | CSPR_V) 433 434 #define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) 435 #define CONFIG_SYS_CSOR3 0x0 436 437 /* CPLD Timing parameters for IFC CS3 */ 438 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 439 FTIM0_GPCM_TEADC(0x0e) | \ 440 FTIM0_GPCM_TEAHC(0x0e)) 441 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 442 FTIM1_GPCM_TRAD(0x1f)) 443 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 444 FTIM2_GPCM_TCH(0x8) | \ 445 FTIM2_GPCM_TWP(0x1f)) 446 #define CONFIG_SYS_CS3_FTIM3 0x0 447 448 #if defined(CONFIG_RAMBOOT_PBL) 449 #define CONFIG_SYS_RAMBOOT 450 #endif 451 452 /* I2C */ 453 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 454 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 455 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 456 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 457 458 #define I2C_MUX_CH_DEFAULT 0x8 459 #define I2C_MUX_CH_VOL_MONITOR 0xa 460 #define I2C_MUX_CH_VSC3316_FS 0xc 461 #define I2C_MUX_CH_VSC3316_BS 0xd 462 463 /* Voltage monitor on channel 2*/ 464 #define I2C_VOL_MONITOR_ADDR 0x40 465 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 466 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 467 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 468 469 #define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" 470 #ifndef CONFIG_SPL_BUILD 471 #define CONFIG_VID 472 #endif 473 #define CONFIG_VOL_MONITOR_IR36021_SET 474 #define CONFIG_VOL_MONITOR_IR36021_READ 475 /* The lowest and highest voltage allowed for T4240RDB */ 476 #define VDD_MV_MIN 819 477 #define VDD_MV_MAX 1212 478 479 /* 480 * eSPI - Enhanced SPI 481 */ 482 483 /* Qman/Bman */ 484 #ifndef CONFIG_NOBQFMAN 485 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 486 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 487 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 488 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 489 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 490 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 491 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 492 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 493 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 494 CONFIG_SYS_BMAN_CENA_SIZE) 495 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 496 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 497 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 498 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 499 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 500 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 501 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 502 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 503 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 504 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 505 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 506 CONFIG_SYS_QMAN_CENA_SIZE) 507 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 508 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 509 510 #define CONFIG_SYS_DPAA_FMAN 511 #define CONFIG_SYS_DPAA_PME 512 #define CONFIG_SYS_PMAN 513 #define CONFIG_SYS_DPAA_DCE 514 #define CONFIG_SYS_DPAA_RMAN 515 #define CONFIG_SYS_INTERLAKEN 516 517 /* Default address of microcode for the Linux Fman driver */ 518 #if defined(CONFIG_SPIFLASH) 519 /* 520 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 521 * env, so we got 0x110000. 522 */ 523 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 524 #elif defined(CONFIG_SDCARD) 525 /* 526 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 527 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 528 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 529 */ 530 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 531 #elif defined(CONFIG_MTD_RAW_NAND) 532 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 533 #else 534 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 535 #endif 536 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 537 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 538 #endif /* CONFIG_NOBQFMAN */ 539 540 #ifdef CONFIG_SYS_DPAA_FMAN 541 #define CONFIG_CORTINA_FW_ADDR 0xefe00000 542 #define CONFIG_CORTINA_FW_LENGTH 0x40000 543 #define SGMII_PHY_ADDR1 0x0 544 #define SGMII_PHY_ADDR2 0x1 545 #define SGMII_PHY_ADDR3 0x2 546 #define SGMII_PHY_ADDR4 0x3 547 #define SGMII_PHY_ADDR5 0x4 548 #define SGMII_PHY_ADDR6 0x5 549 #define SGMII_PHY_ADDR7 0x6 550 #define SGMII_PHY_ADDR8 0x7 551 #define FM1_10GEC1_PHY_ADDR 0x10 552 #define FM1_10GEC2_PHY_ADDR 0x11 553 #define FM2_10GEC1_PHY_ADDR 0x12 554 #define FM2_10GEC2_PHY_ADDR 0x13 555 #define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR 556 #define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR 557 #define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR 558 #define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR 559 #endif 560 561 /* SATA */ 562 #ifdef CONFIG_FSL_SATA_V2 563 #define CONFIG_SYS_SATA_MAX_DEVICE 2 564 #define CONFIG_SATA1 565 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 566 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 567 #define CONFIG_SATA2 568 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 569 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 570 571 #define CONFIG_LBA48 572 #endif 573 574 #ifdef CONFIG_FMAN_ENET 575 #define CONFIG_ETHPRIME "FM1@DTSEC1" 576 #endif 577 578 /* 579 * USB 580 */ 581 #define CONFIG_USB_EHCI_FSL 582 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 583 #define CONFIG_HAS_FSL_DR_USB 584 585 #ifdef CONFIG_MMC 586 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 587 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 588 #endif 589 590 591 #define __USB_PHY_TYPE utmi 592 593 /* 594 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 595 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 596 * interleaving. It can be cacheline, page, bank, superbank. 597 * See doc/README.fsl-ddr for details. 598 */ 599 #ifdef CONFIG_ARCH_T4240 600 #define CTRL_INTLV_PREFERED 3way_4KB 601 #else 602 #define CTRL_INTLV_PREFERED cacheline 603 #endif 604 605 #define CONFIG_EXTRA_ENV_SETTINGS \ 606 "hwconfig=fsl_ddr:" \ 607 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 608 "bank_intlv=auto;" \ 609 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 610 "netdev=eth0\0" \ 611 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 612 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 613 "tftpflash=tftpboot $loadaddr $uboot && " \ 614 "protect off $ubootaddr +$filesize && " \ 615 "erase $ubootaddr +$filesize && " \ 616 "cp.b $loadaddr $ubootaddr $filesize && " \ 617 "protect on $ubootaddr +$filesize && " \ 618 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 619 "consoledev=ttyS0\0" \ 620 "ramdiskaddr=2000000\0" \ 621 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ 622 "fdtaddr=1e00000\0" \ 623 "fdtfile=t4240rdb/t4240rdb.dtb\0" \ 624 "bdev=sda3\0" 625 626 #define CONFIG_HVBOOT \ 627 "setenv bootargs config-addr=0x60000000; " \ 628 "bootm 0x01000000 - 0x00f00000" 629 630 #define CONFIG_LINUX \ 631 "setenv bootargs root=/dev/ram rw " \ 632 "console=$consoledev,$baudrate $othbootargs;" \ 633 "setenv ramdiskaddr 0x02000000;" \ 634 "setenv fdtaddr 0x00c00000;" \ 635 "setenv loadaddr 0x1000000;" \ 636 "bootm $loadaddr $ramdiskaddr $fdtaddr" 637 638 #define CONFIG_HDBOOT \ 639 "setenv bootargs root=/dev/$bdev rw " \ 640 "console=$consoledev,$baudrate $othbootargs;" \ 641 "tftp $loadaddr $bootfile;" \ 642 "tftp $fdtaddr $fdtfile;" \ 643 "bootm $loadaddr - $fdtaddr" 644 645 #define CONFIG_NFSBOOTCOMMAND \ 646 "setenv bootargs root=/dev/nfs rw " \ 647 "nfsroot=$serverip:$rootpath " \ 648 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 649 "console=$consoledev,$baudrate $othbootargs;" \ 650 "tftp $loadaddr $bootfile;" \ 651 "tftp $fdtaddr $fdtfile;" \ 652 "bootm $loadaddr - $fdtaddr" 653 654 #define CONFIG_RAMBOOTCOMMAND \ 655 "setenv bootargs root=/dev/ram rw " \ 656 "console=$consoledev,$baudrate $othbootargs;" \ 657 "tftp $ramdiskaddr $ramdiskfile;" \ 658 "tftp $loadaddr $bootfile;" \ 659 "tftp $fdtaddr $fdtfile;" \ 660 "bootm $loadaddr $ramdiskaddr $fdtaddr" 661 662 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 663 664 #include <asm/fsl_secure_boot.h> 665 666 #endif /* __CONFIG_H */ 667