1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Altera SoCFPGA common board code
4 *
5 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
6 */
7
8 #include <common.h>
9 #include <asm/arch/clock_manager.h>
10 #include <asm/arch/misc.h>
11 #include <asm/arch/reset_manager.h>
12 #include <asm/arch/secure_vab.h>
13 #include <asm/global_data.h>
14 #include <asm/io.h>
15 #include <errno.h>
16 #include <fdtdec.h>
17 #include <hang.h>
18 #include <image.h>
19 #include <init.h>
20 #include <log.h>
21 #include <usb.h>
22 #include <usb/dwc2_udc.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
s_init(void)26 void s_init(void) {
27 #ifndef CONFIG_ARM64
28 /*
29 * Preconfigure ACTLR and CPACR, make sure Write Full Line of Zeroes
30 * is disabled in ACTLR.
31 * This is optional on CycloneV / ArriaV.
32 * This is mandatory on Arria10, otherwise Linux refuses to boot.
33 */
34 asm volatile(
35 "mcr p15, 0, %0, c1, c0, 1\n"
36 "mcr p15, 0, %0, c1, c0, 2\n"
37 "isb\n"
38 "dsb\n"
39 ::"r"(0x0));
40 #endif
41 }
42
43 /*
44 * Miscellaneous platform dependent initialisations
45 */
board_init(void)46 int board_init(void)
47 {
48 /* Address of boot parameters for ATAG (if ATAG is used) */
49 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
50
51 return 0;
52 }
53
dram_init_banksize(void)54 int dram_init_banksize(void)
55 {
56 fdtdec_setup_memory_banksize();
57
58 return 0;
59 }
60
61 #ifdef CONFIG_USB_GADGET
62 struct dwc2_plat_otg_data socfpga_otg_data = {
63 .usb_gusbcfg = 0x1417,
64 };
65
board_usb_init(int index,enum usb_init_type init)66 int board_usb_init(int index, enum usb_init_type init)
67 {
68 int node[2], count;
69 fdt_addr_t addr;
70
71 count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc",
72 COMPAT_ALTERA_SOCFPGA_DWC2USB,
73 node, 2);
74 if (count <= 0) /* No controller found. */
75 return 0;
76
77 addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg");
78 if (addr == FDT_ADDR_T_NONE) {
79 printf("UDC Controller has no 'reg' property!\n");
80 return -EINVAL;
81 }
82
83 /* Patch the address from OF into the controller pdata. */
84 socfpga_otg_data.regs_otg = addr;
85
86 return dwc2_udc_probe(&socfpga_otg_data);
87 }
88
g_dnl_board_usb_cable_connected(void)89 int g_dnl_board_usb_cable_connected(void)
90 {
91 return 1;
92 }
93 #endif
94
95 #ifdef CONFIG_SPL_BUILD
board_fit_config_name_match(const char * name)96 __weak int board_fit_config_name_match(const char *name)
97 {
98 /* Just empty function now - can't decide what to choose */
99 debug("%s: %s\n", __func__, name);
100
101 return 0;
102 }
103 #endif
104
105 #if IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS)
board_fit_image_post_process(void ** p_image,size_t * p_size)106 void board_fit_image_post_process(void **p_image, size_t *p_size)
107 {
108 if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH)) {
109 if (socfpga_vendor_authentication(p_image, p_size))
110 hang();
111 }
112 }
113 #endif
114
115 #if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_FIT)
board_prep_linux(bootm_headers_t * images)116 void board_prep_linux(bootm_headers_t *images)
117 {
118 if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH) &&
119 !IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) {
120 /*
121 * Ensure the OS is always booted from FIT and with
122 * VAB signed certificate
123 */
124 if (!images->fit_uname_cfg) {
125 printf("Please use FIT with VAB signed images!\n");
126 hang();
127 }
128
129 env_set_hex("fdt_addr", (ulong)images->ft_addr);
130 debug("images->ft_addr = 0x%08lx\n", (ulong)images->ft_addr);
131 }
132
133 if (IS_ENABLED(CONFIG_CADENCE_QSPI)) {
134 if (env_get("linux_qspi_enable"))
135 run_command(env_get("linux_qspi_enable"), 0);
136 }
137 }
138 #endif
139