1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved.
4 */
5
6 #include <common.h>
7 #include <log.h>
8 #include <asm/io.h>
9 #include <asm/arch/clock.h>
10 #include <asm/arch/gp_padctrl.h>
11 #include <asm/arch/pinmux.h>
12 #include <asm/arch/tegra.h>
13 #include <asm/arch-tegra/clk_rst.h>
14 #include <asm/arch-tegra/pmc.h>
15 #include <asm/arch-tegra/scu.h>
16 #include <linux/delay.h>
17 #include "cpu.h"
18
get_num_cpus(void)19 int get_num_cpus(void)
20 {
21 struct apb_misc_gp_ctlr *gp;
22 uint rev;
23 debug("%s entry\n", __func__);
24
25 gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
26 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
27
28 switch (rev) {
29 case CHIPID_TEGRA20:
30 return 2;
31 break;
32 case CHIPID_TEGRA30:
33 case CHIPID_TEGRA114:
34 case CHIPID_TEGRA124:
35 case CHIPID_TEGRA210:
36 default:
37 return 4;
38 break;
39 }
40 }
41
42 /*
43 * Timing tables for each SOC for all four oscillator options.
44 */
45 struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
46 /*
47 * T20: 1 GHz
48 *
49 * Register Field Bits Width
50 * ------------------------------
51 * PLLX_BASE p 22:20 3
52 * PLLX_BASE n 17: 8 10
53 * PLLX_BASE m 4: 0 5
54 * PLLX_MISC cpcon 11: 8 4
55 */
56 {
57 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
58 { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
59 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
60 { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
61 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
62 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
63 },
64 /*
65 * T25: 1.2 GHz
66 *
67 * Register Field Bits Width
68 * ------------------------------
69 * PLLX_BASE p 22:20 3
70 * PLLX_BASE n 17: 8 10
71 * PLLX_BASE m 4: 0 5
72 * PLLX_MISC cpcon 11: 8 4
73 */
74 {
75 { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
76 { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
77 { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
78 { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
79 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
80 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
81 },
82 /*
83 * T30: 600 MHz
84 *
85 * Register Field Bits Width
86 * ------------------------------
87 * PLLX_BASE p 22:20 3
88 * PLLX_BASE n 17: 8 10
89 * PLLX_BASE m 4: 0 5
90 * PLLX_MISC cpcon 11: 8 4
91 */
92 {
93 { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
94 { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
95 { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
96 { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
97 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
98 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
99 },
100 /*
101 * T114: 700 MHz
102 *
103 * Register Field Bits Width
104 * ------------------------------
105 * PLLX_BASE p 23:20 4
106 * PLLX_BASE n 15: 8 8
107 * PLLX_BASE m 7: 0 8
108 */
109 {
110 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
111 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
112 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
113 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
114 { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
115 { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
116 },
117
118 /*
119 * T124: 700 MHz
120 *
121 * Register Field Bits Width
122 * ------------------------------
123 * PLLX_BASE p 23:20 4
124 * PLLX_BASE n 15: 8 8
125 * PLLX_BASE m 7: 0 8
126 */
127 {
128 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
129 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
130 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
131 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
132 { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
133 { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
134 },
135
136 /*
137 * T210: 700 MHz
138 *
139 * Register Field Bits Width
140 * ------------------------------
141 * PLLX_BASE p 24:20 5
142 * PLLX_BASE n 15: 8 8
143 * PLLX_BASE m 7: 0 8
144 */
145 {
146 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz*/
147 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/
148 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/
149 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/
150 { .n = 36, .m = 1, .p = 1 }, /* OSC: 38.4 MHz = 691.2 MHz */
151 { .n = 58, .m = 2, .p = 1 }, /* OSC: 48.0 MHz = 696 MHz */
152 },
153 };
154
pllx_set_iddq(void)155 static inline void pllx_set_iddq(void)
156 {
157 #if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
158 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
159 u32 reg;
160 debug("%s entry\n", __func__);
161
162 /* Disable IDDQ */
163 reg = readl(&clkrst->crc_pllx_misc3);
164 reg &= ~PLLX_IDDQ_MASK;
165 writel(reg, &clkrst->crc_pllx_misc3);
166 udelay(2);
167 debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__,
168 readl(&clkrst->crc_pllx_misc3));
169 #endif
170 }
171
pllx_set_rate(struct clk_pll_simple * pll,u32 divn,u32 divm,u32 divp,u32 cpcon)172 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
173 u32 divp, u32 cpcon)
174 {
175 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU];
176 int chip = tegra_get_chip();
177 u32 reg;
178 debug("%s entry\n", __func__);
179
180 /* If PLLX is already enabled, just return */
181 if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
182 debug("%s: PLLX already enabled, returning\n", __func__);
183 return 0;
184 }
185
186 pllx_set_iddq();
187
188 /* Set BYPASS, m, n and p to PLLX_BASE */
189 reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift);
190 reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift);
191 writel(reg, &pll->pll_base);
192
193 /* Set cpcon to PLLX_MISC */
194 if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
195 reg = (cpcon << pllinfo->kcp_shift);
196 else
197 reg = 0;
198
199 /*
200 * TODO(twarren@nvidia.com) Check which SoCs use DCCON
201 * and add to pllinfo table if needed!
202 */
203 /* Set dccon to PLLX_MISC if freq > 600MHz */
204 if (divn > 600)
205 reg |= (1 << PLL_DCCON_SHIFT);
206 writel(reg, &pll->pll_misc);
207
208 /* Disable BYPASS */
209 reg = readl(&pll->pll_base);
210 reg &= ~PLL_BYPASS_MASK;
211 writel(reg, &pll->pll_base);
212 debug("%s: base = 0x%08X\n", __func__, reg);
213
214 /* Set lock_enable to PLLX_MISC if lock_ena is valid (i.e. 0-31) */
215 reg = readl(&pll->pll_misc);
216 if (pllinfo->lock_ena < 32)
217 reg |= (1 << pllinfo->lock_ena);
218 writel(reg, &pll->pll_misc);
219 debug("%s: misc = 0x%08X\n", __func__, reg);
220
221 /* Enable PLLX last, once it's all configured */
222 reg = readl(&pll->pll_base);
223 reg |= PLL_ENABLE_MASK;
224 writel(reg, &pll->pll_base);
225 debug("%s: base final = 0x%08X\n", __func__, reg);
226
227 return 0;
228 }
229
init_pllx(void)230 void init_pllx(void)
231 {
232 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
233 struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
234 int soc_type, sku_info, chip_sku;
235 enum clock_osc_freq osc;
236 struct clk_pll_table *sel;
237 debug("%s entry\n", __func__);
238
239 /* get SOC (chip) type */
240 soc_type = tegra_get_chip();
241 debug("%s: SoC = 0x%02X\n", __func__, soc_type);
242
243 /* get SKU info */
244 sku_info = tegra_get_sku_info();
245 debug("%s: SKU info byte = 0x%02X\n", __func__, sku_info);
246
247 /* get chip SKU, combo of the above info */
248 chip_sku = tegra_get_chip_sku();
249 debug("%s: Chip SKU = %d\n", __func__, chip_sku);
250
251 /* get osc freq */
252 osc = clock_get_osc_freq();
253 debug("%s: osc = %d\n", __func__, osc);
254
255 /* set pllx */
256 sel = &tegra_pll_x_table[chip_sku][osc];
257 pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
258 }
259
enable_cpu_clock(int enable)260 void enable_cpu_clock(int enable)
261 {
262 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
263 u32 clk;
264 debug("%s entry\n", __func__);
265
266 /*
267 * NOTE:
268 * Regardless of whether the request is to enable or disable the CPU
269 * clock, every processor in the CPU complex except the master (CPU 0)
270 * will have it's clock stopped because the AVP only talks to the
271 * master.
272 */
273
274 if (enable) {
275 /* Initialize PLLX */
276 init_pllx();
277
278 /* Wait until all clocks are stable */
279 udelay(PLL_STABILIZATION_DELAY);
280
281 writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
282 writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
283 }
284
285 /*
286 * Read the register containing the individual CPU clock enables and
287 * always stop the clocks to CPUs > 0.
288 */
289 clk = readl(&clkrst->crc_clk_cpu_cmplx);
290 clk |= 1 << CPU1_CLK_STP_SHIFT;
291 if (get_num_cpus() == 4)
292 clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
293
294 /* Stop/Unstop the CPU clock */
295 clk &= ~CPU0_CLK_STP_MASK;
296 clk |= !enable << CPU0_CLK_STP_SHIFT;
297 writel(clk, &clkrst->crc_clk_cpu_cmplx);
298
299 clock_enable(PERIPH_ID_CPU);
300 }
301
is_cpu_powered(void)302 static int is_cpu_powered(void)
303 {
304 return (tegra_pmc_readl(offsetof(struct pmc_ctlr,
305 pmc_pwrgate_status)) & CPU_PWRED) ? 1 : 0;
306 }
307
remove_cpu_io_clamps(void)308 static void remove_cpu_io_clamps(void)
309 {
310 u32 reg;
311 debug("%s entry\n", __func__);
312
313 /* Remove the clamps on the CPU I/O signals */
314 reg = tegra_pmc_readl(offsetof(struct pmc_ctlr, pmc_remove_clamping));
315 reg |= CPU_CLMP;
316 tegra_pmc_writel(reg, offsetof(struct pmc_ctlr, pmc_remove_clamping));
317
318 /* Give I/O signals time to stabilize */
319 udelay(IO_STABILIZATION_DELAY);
320 }
321
powerup_cpu(void)322 void powerup_cpu(void)
323 {
324 u32 reg;
325 int timeout = IO_STABILIZATION_DELAY;
326 debug("%s entry\n", __func__);
327
328 if (!is_cpu_powered()) {
329 /* Toggle the CPU power state (OFF -> ON) */
330 reg = tegra_pmc_readl(offsetof(struct pmc_ctlr,
331 pmc_pwrgate_toggle));
332 reg &= PARTID_CP;
333 reg |= START_CP;
334 tegra_pmc_writel(reg,
335 offsetof(struct pmc_ctlr,
336 pmc_pwrgate_toggle));
337
338 /* Wait for the power to come up */
339 while (!is_cpu_powered()) {
340 if (timeout-- == 0)
341 printf("CPU failed to power up!\n");
342 else
343 udelay(10);
344 }
345
346 /*
347 * Remove the I/O clamps from CPU power partition.
348 * Recommended only on a Warm boot, if the CPU partition gets
349 * power gated. Shouldn't cause any harm when called after a
350 * cold boot according to HW, probably just redundant.
351 */
352 remove_cpu_io_clamps();
353 }
354 }
355
reset_A9_cpu(int reset)356 void reset_A9_cpu(int reset)
357 {
358 /*
359 * NOTE: Regardless of whether the request is to hold the CPU in reset
360 * or take it out of reset, every processor in the CPU complex
361 * except the master (CPU 0) will be held in reset because the
362 * AVP only talks to the master. The AVP does not know that there
363 * are multiple processors in the CPU complex.
364 */
365 int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
366 int num_cpus = get_num_cpus();
367 int cpu;
368
369 debug("%s entry\n", __func__);
370 /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
371 for (cpu = 1; cpu < num_cpus; cpu++)
372 reset_cmplx_set_enable(cpu, mask, 1);
373 reset_cmplx_set_enable(0, mask, reset);
374
375 /* Enable/Disable master CPU reset */
376 reset_set_enable(PERIPH_ID_CPU, reset);
377 }
378
clock_enable_coresight(int enable)379 void clock_enable_coresight(int enable)
380 {
381 u32 rst, src = 2;
382
383 debug("%s entry\n", __func__);
384 clock_set_enable(PERIPH_ID_CORESIGHT, enable);
385 reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
386
387 if (enable) {
388 /*
389 * Put CoreSight on PLLP_OUT0 and divide it down as per
390 * PLLP base frequency based on SoC type (T20/T30+).
391 * Clock divider request would setup CSITE clock as 144MHz
392 * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
393 */
394 src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ);
395 clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
396
397 /* Unlock the CPU CoreSight interfaces */
398 rst = CORESIGHT_UNLOCK;
399 writel(rst, CSITE_CPU_DBG0_LAR);
400 writel(rst, CSITE_CPU_DBG1_LAR);
401 if (get_num_cpus() == 4) {
402 writel(rst, CSITE_CPU_DBG2_LAR);
403 writel(rst, CSITE_CPU_DBG3_LAR);
404 }
405 }
406 }
407
halt_avp(void)408 void halt_avp(void)
409 {
410 debug("%s entry\n", __func__);
411
412 for (;;) {
413 writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
414 FLOW_CTLR_HALT_COP_EVENTS);
415 }
416 }
417