1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2007-2009 Freescale Semiconductor, Inc.
4 * Copyright (C) 2008-2009 MontaVista Software, Inc.
5 *
6 * Authors: Tony Li <tony.li@freescale.com>
7 * Anton Vorontsov <avorontsov@ru.mvista.com>
8 */
9
10 #include <common.h>
11 #include <pci.h>
12 #include <mpc83xx.h>
13 #include <asm/global_data.h>
14 #include <asm/io.h>
15 #include <linux/delay.h>
16
17 DECLARE_GLOBAL_DATA_PTR;
18
19 #define PCIE_MAX_BUSES 2
20
21 static struct {
22 u32 base;
23 u32 size;
24 } mpc83xx_pcie_cfg_space[] = {
25 {
26 .base = CONFIG_SYS_PCIE1_CFG_BASE,
27 .size = CONFIG_SYS_PCIE1_CFG_SIZE,
28 },
29 #if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_CFG_SIZE)
30 {
31 .base = CONFIG_SYS_PCIE2_CFG_BASE,
32 .size = CONFIG_SYS_PCIE2_CFG_SIZE,
33 },
34 #endif
35 };
36
37 #ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
38
39 /* private structure for mpc83xx pcie hose */
40 static struct mpc83xx_pcie_priv {
41 u8 index;
42 } pcie_priv[PCIE_MAX_BUSES] = {
43 {
44 /* pcie controller 1 */
45 .index = 0,
46 },
47 {
48 /* pcie controller 2 */
49 .index = 1,
50 },
51 };
52
mpc83xx_pcie_remap_cfg(struct pci_controller * hose,pci_dev_t dev)53 static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
54 {
55 int bus = PCI_BUS(dev) - hose->first_busno;
56 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
57 struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data;
58 pex83xx_t *pex = &immr->pciexp[pcie_priv->index];
59 struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0];
60 u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev);
61 u32 dev_base = bus << 24 | devfn << 16;
62
63 if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK)
64 return -1;
65 /*
66 * Workaround for the HW bug: for Type 0 configure transactions the
67 * PCI-E controller does not check the device number bits and just
68 * assumes that the device number bits are 0.
69 */
70 if (devfn & 0xf8)
71 return -1;
72
73 out_le32(&out_win->tarl, dev_base);
74 return 0;
75 }
76
77 #define cfg_read(val, addr, type, op) \
78 do { *val = op((type)(addr)); } while (0)
79 #define cfg_write(val, addr, type, op) \
80 do { op((type *)(addr), (val)); } while (0)
81
82 #define cfg_read_err(val) do { *val = -1; } while (0)
83 #define cfg_write_err(val) do { } while (0)
84
85 #define PCIE_OP(rw, size, type, op) \
86 static int pcie_##rw##_config_##size(struct pci_controller *hose, \
87 pci_dev_t dev, int offset, \
88 type val) \
89 { \
90 int ret; \
91 \
92 ret = mpc83xx_pcie_remap_cfg(hose, dev); \
93 if (ret) { \
94 cfg_##rw##_err(val); \
95 return ret; \
96 } \
97 cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op); \
98 return 0; \
99 }
100
PCIE_OP(read,byte,u8 *,in_8)101 PCIE_OP(read, byte, u8 *, in_8)
102 PCIE_OP(read, word, u16 *, in_le16)
103 PCIE_OP(read, dword, u32 *, in_le32)
104 PCIE_OP(write, byte, u8, out_8)
105 PCIE_OP(write, word, u16, out_le16)
106 PCIE_OP(write, dword, u32, out_le32)
107
108 static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
109 u8 link)
110 {
111 extern void disable_addr_trans(void); /* start.S */
112 static struct pci_controller pcie_hose[PCIE_MAX_BUSES];
113 struct pci_controller *hose = &pcie_hose[bus];
114 int i;
115
116 /*
117 * There are no spare BATs to remap all PCI-E windows for U-Boot, so
118 * disable translations. In general, this is not great solution, and
119 * that's why we don't register PCI-E hoses by default.
120 */
121 disable_addr_trans();
122
123 for (i = 0; i < 2; i++, reg++) {
124 if (reg->size == 0)
125 break;
126
127 hose->regions[i] = *reg;
128 hose->region_count++;
129 }
130
131 i = hose->region_count++;
132 hose->regions[i].bus_start = 0;
133 hose->regions[i].phys_start = 0;
134 hose->regions[i].size = gd->ram_size;
135 hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
136
137 i = hose->region_count++;
138 hose->regions[i].bus_start = CONFIG_SYS_IMMR;
139 hose->regions[i].phys_start = CONFIG_SYS_IMMR;
140 hose->regions[i].size = 0x100000;
141 hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
142
143 hose->first_busno = pci_last_busno() + 1;
144 hose->last_busno = 0xff;
145
146 hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base;
147
148 hose->priv_data = &pcie_priv[bus];
149
150 pci_set_ops(hose,
151 pcie_read_config_byte,
152 pcie_read_config_word,
153 pcie_read_config_dword,
154 pcie_write_config_byte,
155 pcie_write_config_word,
156 pcie_write_config_dword);
157
158 if (!link)
159 hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK;
160
161 pci_register_hose(hose);
162
163 #ifdef CONFIG_PCI_SCAN_SHOW
164 printf("PCI: Bus Dev VenId DevId Class Int\n");
165 #endif
166 /*
167 * Hose scan.
168 */
169 hose->last_busno = pci_hose_scan(hose);
170 }
171
172 #else
173
mpc83xx_pcie_register_hose(int bus,struct pci_region * reg,u8 link)174 static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
175 u8 link) {}
176
177 #endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */
178
get_pcie_clk(int index)179 int get_pcie_clk(int index)
180 {
181 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
182 u32 pci_sync_in;
183 u8 spmf;
184 u8 clkin_div;
185 u32 sccr;
186 u32 csb_clk;
187 u32 testval;
188
189 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
190 sccr = im->clk.sccr;
191 pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
192 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
193 csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
194
195 if (index)
196 testval = (sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT;
197 else
198 testval = (sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT;
199
200 switch (testval) {
201 case 0:
202 return 0;
203 case 1:
204 return csb_clk;
205 case 2:
206 return csb_clk / 2;
207 case 3:
208 return csb_clk / 3;
209 }
210
211 return 0;
212 }
213
mpc83xx_pcie_init_bus(int bus,struct pci_region * reg)214 static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
215 {
216 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
217 pex83xx_t *pex = &immr->pciexp[bus];
218 struct pex_outbound_window *out_win;
219 struct pex_inbound_window *in_win;
220 void *hose_cfg_base;
221 unsigned int ram_sz;
222 unsigned int barl;
223 unsigned int tar;
224 u16 reg16;
225 int i;
226
227 /* Enable pex csb bridge inbound & outbound transactions */
228 out_le32(&pex->bridge.pex_csb_ctrl,
229 in_le32(&pex->bridge.pex_csb_ctrl) | PEX_CSB_CTRL_OBPIOE |
230 PEX_CSB_CTRL_IBPIOE);
231
232 /* Enable bridge outbound */
233 out_le32(&pex->bridge.pex_csb_obctrl, PEX_CSB_OBCTRL_PIOE |
234 PEX_CSB_OBCTRL_MEMWE | PEX_CSB_OBCTRL_IOWE |
235 PEX_CSB_OBCTRL_CFGWE);
236
237 out_win = &pex->bridge.pex_outbound_win[0];
238 out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG |
239 mpc83xx_pcie_cfg_space[bus].size);
240 out_le32(&out_win->bar, mpc83xx_pcie_cfg_space[bus].base);
241 out_le32(&out_win->tarl, 0);
242 out_le32(&out_win->tarh, 0);
243
244 for (i = 0; i < 2; i++) {
245 u32 ar;
246
247 if (reg[i].size == 0)
248 break;
249
250 out_win = &pex->bridge.pex_outbound_win[i + 1];
251 out_le32(&out_win->bar, reg[i].phys_start);
252 out_le32(&out_win->tarl, reg[i].bus_start);
253 out_le32(&out_win->tarh, 0);
254 ar = PEX_OWAR_EN | (reg[i].size & PEX_OWAR_SIZE);
255 if (reg[i].flags & PCI_REGION_IO)
256 ar |= PEX_OWAR_TYPE_IO;
257 else
258 ar |= PEX_OWAR_TYPE_MEM;
259 out_le32(&out_win->ar, ar);
260 }
261
262 out_le32(&pex->bridge.pex_csb_ibctrl, PEX_CSB_IBCTRL_PIOE);
263
264 ram_sz = gd->ram_size;
265 barl = 0;
266 tar = 0;
267 i = 0;
268 while (ram_sz > 0) {
269 in_win = &pex->bridge.pex_inbound_win[i];
270 out_le32(&in_win->barl, barl);
271 out_le32(&in_win->barh, 0x0);
272 out_le32(&in_win->tar, tar);
273 if (ram_sz >= 0x10000000) {
274 /* The maxium windows size is 256M */
275 out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
276 PEX_IWAR_TYPE_PF | 0x0FFFF000);
277 barl += 0x10000000;
278 tar += 0x10000000;
279 ram_sz -= 0x10000000;
280 } else {
281 /* The UM is not clear here.
282 * So, round up to even Mb boundary */
283
284 ram_sz = ram_sz >> (20 +
285 ((ram_sz & 0xFFFFF) ? 1 : 0));
286 if (!(ram_sz % 2))
287 ram_sz -= 1;
288 out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV |
289 PEX_IWAR_TYPE_PF | (ram_sz << 20) | 0xFF000);
290 ram_sz = 0;
291 }
292 i++;
293 }
294
295 in_win = &pex->bridge.pex_inbound_win[i];
296 out_le32(&in_win->barl, CONFIG_SYS_IMMR);
297 out_le32(&in_win->barh, 0);
298 out_le32(&in_win->tar, CONFIG_SYS_IMMR);
299 out_le32(&in_win->ar, PEX_IWAR_EN |
300 PEX_IWAR_TYPE_NO_PF | PEX_IWAR_SIZE_1M);
301
302 /* Enable the host virtual INTX interrupts */
303 out_le32(&pex->bridge.pex_int_axi_misc_enb,
304 in_le32(&pex->bridge.pex_int_axi_misc_enb) | 0x1E0);
305
306 /* Hose configure header is memory-mapped */
307 hose_cfg_base = (void *)pex;
308
309 /* Configure the PCIE controller core clock ratio */
310 out_le32(hose_cfg_base + PEX_GCLK_RATIO,
311 ((get_pcie_clk(bus) / 1000000) * 16) / 333);
312 udelay(1000000);
313
314 /* Do Type 1 bridge configuration */
315 out_8(hose_cfg_base + PCI_PRIMARY_BUS, 0);
316 out_8(hose_cfg_base + PCI_SECONDARY_BUS, 1);
317 out_8(hose_cfg_base + PCI_SUBORDINATE_BUS, 255);
318
319 /*
320 * Write to Command register
321 */
322 reg16 = in_le16(hose_cfg_base + PCI_COMMAND);
323 reg16 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO |
324 PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
325 out_le16(hose_cfg_base + PCI_COMMAND, reg16);
326
327 /*
328 * Clear non-reserved bits in status register.
329 */
330 out_le16(hose_cfg_base + PCI_STATUS, 0xffff);
331 out_8(hose_cfg_base + PCI_LATENCY_TIMER, 0x80);
332 out_8(hose_cfg_base + PCI_CACHE_LINE_SIZE, 0x08);
333
334 printf("PCIE%d: ", bus);
335
336 #define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
337 #define PCI_LTSSM_L0 0x16 /* L0 state */
338 reg16 = in_le16(hose_cfg_base + PCI_LTSSM);
339 if (reg16 >= PCI_LTSSM_L0)
340 printf("link\n");
341 else
342 printf("No link\n");
343
344 mpc83xx_pcie_register_hose(bus, reg, reg16 >= PCI_LTSSM_L0);
345 }
346
347 /*
348 * The caller must have already set SCCR, SERDES and the PCIE_LAW BARs
349 * must have been set to cover all of the requested regions.
350 */
mpc83xx_pcie_init(int num_buses,struct pci_region ** reg)351 void mpc83xx_pcie_init(int num_buses, struct pci_region **reg)
352 {
353 int i;
354
355 /*
356 * Release PCI RST Output signal.
357 * Power on to RST high must be at least 100 ms as per PCI spec.
358 * On warm boots only 1 ms is required, but we play it safe.
359 */
360 udelay(100000);
361
362 if (num_buses > ARRAY_SIZE(mpc83xx_pcie_cfg_space)) {
363 printf("Second PCIE host contoller not configured!\n");
364 num_buses = ARRAY_SIZE(mpc83xx_pcie_cfg_space);
365 }
366
367 for (i = 0; i < num_buses; i++)
368 mpc83xx_pcie_init_bus(i, reg[i]);
369 }
370