1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
4 * (C) Copyright 2012 Renesas Solutions Corp.
5 */
6
7 #include <common.h>
8 #include <cpu_func.h>
9 #include <init.h>
10 #include <net.h>
11 #include <asm/global_data.h>
12 #include <asm/io.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/gpio.h>
15 #include <netdev.h>
16 #include <i2c.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 #define CS0BCR_D (0x06C00400)
21 #define CS4BCR_D (0x16c90400)
22 #define CS0WCR_D (0x55062C42)
23 #define CS4WCR_D (0x1e071dc3)
24
25 #define CMNCR_BROMMD0 (1 << 21)
26 #define CMNCR_BROMMD1 (1 << 22)
27 #define CMNCR_BROMMD (CMNCR_BROMMD0|CMNCR_BROMMD1)
28 #define VCLKCR1_D (0x27)
29
30 #define SMSTPCR1_CMT0 (1 << 24)
31 #define SMSTPCR1_I2C0 (1 << 16)
32 #define SMSTPCR3_USB (1 << 22)
33 #define SMSTPCR3_I2C1 (1 << 23)
34
35 #define PORT32CR (0xE6051020)
36 #define PORT33CR (0xE6051021)
37 #define PORT34CR (0xE6051022)
38 #define PORT35CR (0xE6051023)
39
cmp_loop(u32 * addr,u32 data,u32 cmp)40 static int cmp_loop(u32 *addr, u32 data, u32 cmp)
41 {
42 int err = -1;
43 int timeout = 100;
44 u32 value;
45
46 while (timeout > 0) {
47 value = readl(addr);
48 if ((value & data) == cmp) {
49 err = 0;
50 break;
51 }
52 timeout--;
53 }
54
55 return err;
56 }
57
58 /* SBSC Init function */
sbsc_init(struct sh73a0_sbsc * sbsc)59 static void sbsc_init(struct sh73a0_sbsc *sbsc)
60 {
61 writel(readl(&sbsc->dllcnt0)|0x2, &sbsc->dllcnt0);
62 writel(0x5, &sbsc->sdgencnt);
63 cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
64
65 writel(0xacc90159, &sbsc->sdcr0);
66 writel(0x00010059, &sbsc->sdcr1);
67 writel(0x50874114, &sbsc->sdwcrc0);
68 writel(0x33199b37, &sbsc->sdwcrc1);
69 writel(0x008f2313, &sbsc->sdwcrc2);
70 writel(0x31020707, &sbsc->sdwcr00);
71 writel(0x0017040a, &sbsc->sdwcr01);
72 writel(0x31020707, &sbsc->sdwcr10);
73 writel(0x0017040a, &sbsc->sdwcr11);
74 writel(0x055557ff, &sbsc->sddrvcr0); /* Enlarge drivability of LPDQS0-3, LPCLK */
75 writel(0x30000000, &sbsc->sdwcr2);
76
77 writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr);
78 cmp_loop(&sbsc->sdpcr, 0x80, 0x80);
79
80 writel(0x00002710, &sbsc->sdgencnt);
81 cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
82
83 writel(0x0000003f, &sbsc->sdmracr0);
84 writel(0x0, SDMRA1A);
85 writel(0x000001f4, &sbsc->sdgencnt);
86 cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
87
88 writel(0x0000ff0a, &sbsc->sdmracr0);
89 if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE)
90 writel(0x0, SDMRA3A);
91 else
92 writel(0x0, SDMRA3B);
93
94 writel(0x00000032, &sbsc->sdgencnt);
95 cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0);
96
97 if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) {
98 writel(0x00002201, &sbsc->sdmracr0);
99 writel(0x0, SDMRA1A);
100 writel(0x00000402, &sbsc->sdmracr0);
101 writel(0x0, SDMRA1A);
102 writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */
103 writel(0x0, SDMRA1A);
104 writel(0x0, SDMRA2A);
105 } else {
106 writel(0x00002201, &sbsc->sdmracr0);
107 writel(0x0, SDMRA1B);
108 writel(0x00000402, &sbsc->sdmracr0);
109 writel(0x0, SDMRA1B);
110 writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */
111 writel(0x0, SDMRA1B);
112 writel(0x0, SDMRA2B);
113 }
114
115 writel(0x88800004, &sbsc->sdmrtmpcr);
116 writel(0x00000004, &sbsc->sdmrtmpmsk);
117 writel(0xa55a0032, &sbsc->rtcor);
118 writel(0xa55a000c, &sbsc->rtcorh);
119 writel(0xa55a2048, &sbsc->rtcsr);
120 writel(readl(&sbsc->sdcr0)|0x800, &sbsc->sdcr0);
121 writel(readl(&sbsc->sdcr1)|0x400, &sbsc->sdcr1);
122 writel(0xfff20000, &sbsc->zqccr);
123
124 /* SCBS2 only */
125 if (sbsc == (struct sh73a0_sbsc *)SBSC2_BASE) {
126 writel(readl(&sbsc->sdpdcr0)|0x00030000, &sbsc->sdpdcr0);
127 writel(0xa5390000, &sbsc->dphycnt1);
128 writel(0x00001200, &sbsc->dphycnt0);
129 writel(0x07ce0000, &sbsc->dphycnt1);
130 writel(0x00001247, &sbsc->dphycnt0);
131 cmp_loop(&sbsc->dphycnt2, 0xffffffff, 0x07ce0000);
132 writel(readl(&sbsc->sdpdcr0) & 0xfffcffff, &sbsc->sdpdcr0);
133 }
134 }
135
s_init(void)136 void s_init(void)
137 {
138 struct sh73a0_rwdt *rwdt = (struct sh73a0_rwdt *)RWDT_BASE;
139 struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE;
140 struct sh73a0_sbsc_cpg_srcr *cpg_srcr =
141 (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE;
142 struct sh73a0_sbsc *sbsc1 = (struct sh73a0_sbsc *)SBSC1_BASE;
143 struct sh73a0_sbsc *sbsc2 = (struct sh73a0_sbsc *)SBSC2_BASE;
144 struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
145 struct sh73a0_hpb_bscr *hpb_bscr =
146 (struct sh73a0_hpb_bscr *)HPBSCR_BASE;
147
148 /* Watchdog init */
149 writew(0xA507, &rwdt->rwtcsra0);
150
151 /* Secure control register Init */
152 #define LIFEC_SEC_SRC_BIT (1 << 15)
153 writel(readl(LIFEC_SEC_SRC) & ~LIFEC_SEC_SRC_BIT, LIFEC_SEC_SRC);
154
155 clrbits_le32(&cpg->smstpcr3, (1 << 15));
156 clrbits_le32(&cpg_srcr->srcr3, (1 << 15));
157 clrbits_le32(&cpg->smstpcr2, (1 << 18));
158 clrbits_le32(&cpg_srcr->srcr2, (1 << 18));
159 writel(0x0, &cpg->pllecr);
160
161 cmp_loop(&cpg->pllecr, 0x00000F00, 0x0);
162 cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
163
164 writel(0x2D000000, &cpg->pll0cr);
165 writel(0x17100000, &cpg->pll1cr);
166 writel(0x96235880, &cpg->frqcrb);
167 cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
168
169 writel(0xB, &cpg->flckcr);
170 clrbits_le32(&cpg->smstpcr0, (1 << 1));
171
172 clrbits_le32(&cpg_srcr->srcr0, (1 << 1));
173 writel(0x0514, &hpb_bscr->smgpiotime);
174 writel(0x0514, &hpb_bscr->smcmt2time);
175 writel(0x0514, &hpb_bscr->smcpgtime);
176 writel(0x0514, &hpb_bscr->smsysctime);
177
178 writel(0x00092000, &cpg->dvfscr4);
179 writel(0x000000DC, &cpg->dvfscr5);
180 writel(0x0, &cpg->pllecr);
181 cmp_loop(&cpg->pllecr, 0x00000F00, 0x0);
182
183 /* FRQCR Init */
184 writel(0x0012453C, &cpg->frqcra);
185 writel(0x80431350, &cpg->frqcrb); /* ETM TRCLK 78MHz */
186 cmp_loop(&cpg->frqcrb, 0x80000000, 0x0);
187 writel(0x00000B0B, &cpg->frqcrd);
188 cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
189
190 /* Clock Init */
191 writel(0x00000003, PCLKCR);
192 writel(0x0000012F, &cpg->vclkcr1);
193 writel(0x00000119, &cpg->vclkcr2);
194 writel(0x00000119, &cpg->vclkcr3);
195 writel(0x00000002, &cpg->zbckcr);
196 writel(0x00000005, &cpg->flckcr);
197 writel(0x00000080, &cpg->sd0ckcr);
198 writel(0x00000080, &cpg->sd1ckcr);
199 writel(0x00000080, &cpg->sd2ckcr);
200 writel(0x0000003F, &cpg->fsiackcr);
201 writel(0x0000003F, &cpg->fsibckcr);
202 writel(0x00000080, &cpg->subckcr);
203 writel(0x0000000B, &cpg->spuackcr);
204 writel(0x0000000B, &cpg->spuvckcr);
205 writel(0x0000013F, &cpg->msuckcr);
206 writel(0x00000080, &cpg->hsickcr);
207 writel(0x0000003F, &cpg->mfck1cr);
208 writel(0x0000003F, &cpg->mfck2cr);
209 writel(0x00000107, &cpg->dsitckcr);
210 writel(0x00000313, &cpg->dsi0pckcr);
211 writel(0x0000130D, &cpg->dsi1pckcr);
212 writel(0x2A800E0E, &cpg->dsi0phycr);
213 writel(0x1E000000, &cpg->pll0cr);
214 writel(0x2D000000, &cpg->pll0cr);
215 writel(0x17100000, &cpg->pll1cr);
216 writel(0x27000080, &cpg->pll2cr);
217 writel(0x1D000000, &cpg->pll3cr);
218 writel(0x00080000, &cpg->pll0stpcr);
219 writel(0x000120C0, &cpg->pll1stpcr);
220 writel(0x00012000, &cpg->pll2stpcr);
221 writel(0x00000030, &cpg->pll3stpcr);
222
223 writel(0x0000000B, &cpg->pllecr);
224 cmp_loop(&cpg->pllecr, 0x00000B00, 0x00000B00);
225
226 writel(0x000120F0, &cpg->dvfscr3);
227 writel(0x00000020, &cpg->mpmode);
228 writel(0x0000028A, &cpg->vrefcr);
229 writel(0xE4628087, &cpg->rmstpcr0);
230 writel(0xFFFFFFFF, &cpg->rmstpcr1);
231 writel(0x53FFFFFF, &cpg->rmstpcr2);
232 writel(0xFFFFFFFF, &cpg->rmstpcr3);
233 writel(0x00800D3D, &cpg->rmstpcr4);
234 writel(0xFFFFF3FF, &cpg->rmstpcr5);
235 writel(0x00000000, &cpg->smstpcr2);
236 writel(0x00040000, &cpg_srcr->srcr2);
237
238 clrbits_le32(&cpg->pllecr, (1 << 3));
239 cmp_loop(&cpg->pllecr, 0x00000800, 0x0);
240
241 writel(0x00000001, &hpb->hpbctrl6);
242 cmp_loop(&hpb->hpbctrl6, 0x1, 0x1);
243
244 writel(0x00001414, &cpg->frqcrd);
245 cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
246
247 writel(0x1d000000, &cpg->pll3cr);
248 setbits_le32(&cpg->pllecr, (1 << 3));
249 cmp_loop(&cpg->pllecr, 0x800, 0x800);
250
251 /* SBSC1 Init*/
252 sbsc_init(sbsc1);
253
254 /* SBSC2 Init*/
255 sbsc_init(sbsc2);
256
257 writel(0x00000b0b, &cpg->frqcrd);
258 cmp_loop(&cpg->frqcrd, 0x80000000, 0x0);
259 writel(0xfffffffc, &cpg->cpgxxcs4);
260 }
261
board_early_init_f(void)262 int board_early_init_f(void)
263 {
264 struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE;
265 struct sh73a0_bsc *bsc = (struct sh73a0_bsc *)BSC_BASE;
266 struct sh73a0_sbsc_cpg_srcr *cpg_srcr =
267 (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE;
268
269 writel(CS0BCR_D, &bsc->cs0bcr);
270 writel(CS4BCR_D, &bsc->cs4bcr);
271 writel(CS0WCR_D, &bsc->cs0wcr);
272 writel(CS4WCR_D, &bsc->cs4wcr);
273
274 clrsetbits_le32(&bsc->cmncr, ~CMNCR_BROMMD, CMNCR_BROMMD);
275
276 clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
277 clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
278 clrbits_le32(&cpg->smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1));
279 clrbits_le32(&cpg_srcr->srcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1));
280 writel(VCLKCR1_D, &cpg->vclkcr1);
281
282 /* Setup SCIF4 / workaround */
283 writeb(0x12, PORT32CR);
284 writeb(0x22, PORT33CR);
285 writeb(0x12, PORT34CR);
286 writeb(0x22, PORT35CR);
287
288 return 0;
289 }
290
adjust_core_voltage(void)291 void adjust_core_voltage(void)
292 {
293 u8 data;
294
295 data = 0x35;
296 i2c_set_bus_num(0);
297 i2c_write(0x40, 3, 1, &data, 1);
298 }
299
board_init(void)300 int board_init(void)
301 {
302 adjust_core_voltage();
303 sh73a0_pinmux_init();
304
305 /* SCIFA 4 */
306 gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
307 gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
308 gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
309 gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
310
311 /* Ethernet/SMSC */
312 gpio_request(GPIO_PORT224, NULL);
313 gpio_direction_input(GPIO_PORT224);
314
315 /* SMSC/USB */
316 gpio_request(GPIO_FN_CS4_, NULL);
317
318 /* MMCIF */
319 gpio_request(GPIO_FN_MMCCLK0, NULL);
320 gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
321 gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
322 gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
323 gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
324 gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
325 gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
326 gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
327 gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
328 gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
329
330 /* SDHI */
331 gpio_request(GPIO_FN_SDHIWP0, NULL);
332 gpio_request(GPIO_FN_SDHICD0, NULL);
333 gpio_request(GPIO_FN_SDHICMD0, NULL);
334 gpio_request(GPIO_FN_SDHICLK0, NULL);
335 gpio_request(GPIO_FN_SDHID0_3, NULL);
336 gpio_request(GPIO_FN_SDHID0_2, NULL);
337 gpio_request(GPIO_FN_SDHID0_1, NULL);
338 gpio_request(GPIO_FN_SDHID0_0, NULL);
339 gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
340 gpio_request(GPIO_PORT15, NULL);
341 gpio_direction_output(GPIO_PORT15, 1);
342
343 /* I2C */
344 gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL);
345 gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL);
346 gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
347 gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
348
349 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
350
351 return 0;
352 }
353
dram_init(void)354 int dram_init(void)
355 {
356 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
357 return 0;
358 }
359
board_eth_init(struct bd_info * bis)360 int board_eth_init(struct bd_info *bis)
361 {
362 int ret = 0;
363 #ifdef CONFIG_SMC911X
364 ret = smc911x_initialize(0, CONFIG_SMC911X_BASE);
365 #endif
366 return ret;
367 }
368
reset_cpu(void)369 void reset_cpu(void)
370 {
371 /* Soft Power On Reset */
372 writel((1 << 31), RESCNT2);
373 }
374