1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2012 Freescale Semiconductor, Inc.
4 */
5
6 #ifndef __PINCTRL_MXS_H
7 #define __PINCTRL_MXS_H
8
9 #include <dm/pinctrl.h>
10
11 #define SET 0x4
12 #define CLR 0x8
13 #define TOG 0xc
14
15 #define MXS_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
16 #define PINID(bank, pin) ((bank) * 32 + (pin))
17
18 /*
19 * pinmux-id bit field definitions
20 *
21 * bank: 15..12 (4)
22 * pin: 11..4 (8)
23 * muxsel: 3..0 (4)
24 */
25 #define MUXID_TO_PINID(m) PINID((m) >> 12 & 0xf, (m) >> 4 & 0xff)
26 #define MUXID_TO_MUXSEL(m) ((m) & 0xf)
27
28 #define PINID_TO_BANK(p) ((p) >> 5)
29 #define PINID_TO_PIN(p) ((p) % 32)
30
31 /*
32 * pin config bit field definitions
33 *
34 * pull-up: 6..5 (2)
35 * voltage: 4..3 (2)
36 * mA: 2..0 (3)
37 *
38 * MSB of each field is presence bit for the config.
39 */
40 #define PULL_PRESENT (1 << 6)
41 #define PULL_SHIFT 5
42 #define VOL_PRESENT (1 << 4)
43 #define VOL_SHIFT 3
44 #define MA_PRESENT (1 << 2)
45 #define MA_SHIFT 0
46 #define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1)
47 #define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1)
48 #define CONFIG_TO_MA(c) ((c) >> MA_SHIFT & 0x3)
49
50 struct mxs_regs {
51 u16 muxsel;
52 u16 drive;
53 u16 pull;
54 };
55
mxs_pinctrl_rmwl(u32 value,u32 mask,u8 shift,void __iomem * reg)56 static inline void mxs_pinctrl_rmwl(u32 value, u32 mask, u8 shift,
57 void __iomem *reg)
58 {
59 clrsetbits_le32(reg, mask << shift, value << shift);
60 }
61 #endif /* __PINCTRL_MXS_H */
62