1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2013-2015
4 * NVIDIA Corporation <www.nvidia.com>
5 */
6
7 /* Tegra124 Clock control functions */
8
9 #include <common.h>
10 #include <init.h>
11 #include <log.h>
12 #include <asm/io.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sysctr.h>
15 #include <asm/arch/tegra.h>
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/timer.h>
18 #include <div64.h>
19 #include <fdtdec.h>
20 #include <linux/delay.h>
21
22 /*
23 * Clock types that we can use as a source. The Tegra124 has muxes for the
24 * peripheral clocks, and in most cases there are four options for the clock
25 * source. This gives us a clock 'type' and exploits what commonality exists
26 * in the device.
27 *
28 * Letters are obvious, except for T which means CLK_M, and S which means the
29 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
30 * datasheet) and PLL_M are different things. The former is the basic
31 * clock supplied to the SOC from an external oscillator. The latter is the
32 * memory clock PLL.
33 *
34 * See definitions in clock_id in the header file.
35 */
36 enum clock_type_id {
37 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
38 CLOCK_TYPE_MCPA, /* and so on */
39 CLOCK_TYPE_MCPT,
40 CLOCK_TYPE_PCM,
41 CLOCK_TYPE_PCMT,
42 CLOCK_TYPE_PDCT,
43 CLOCK_TYPE_ACPT,
44 CLOCK_TYPE_ASPTE,
45 CLOCK_TYPE_PMDACD2T,
46 CLOCK_TYPE_PCST,
47 CLOCK_TYPE_DP,
48
49 CLOCK_TYPE_PC2CC3M,
50 CLOCK_TYPE_PC2CC3S_T,
51 CLOCK_TYPE_PC2CC3M_T,
52 CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
53 CLOCK_TYPE_MC2CC3P_A,
54 CLOCK_TYPE_M,
55 CLOCK_TYPE_MCPTM2C2C3,
56 CLOCK_TYPE_PC2CC3T_S,
57 CLOCK_TYPE_AC2CC3P_TS2,
58
59 CLOCK_TYPE_COUNT,
60 CLOCK_TYPE_NONE = -1, /* invalid clock type */
61 };
62
63 enum {
64 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
65 };
66
67 /*
68 * Clock source mux for each clock type. This just converts our enum into
69 * a list of mux sources for use by the code.
70 *
71 * Note:
72 * The extra column in each clock source array is used to store the mask
73 * bits in its register for the source.
74 */
75 #define CLK(x) CLOCK_ID_ ## x
76 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
77 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(CLK_M),
78 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
79 MASK_BITS_31_30},
80 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
81 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
82 MASK_BITS_31_30},
83 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
84 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
85 MASK_BITS_31_30},
86 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
87 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
88 MASK_BITS_31_30},
89 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
90 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
91 MASK_BITS_31_30},
92 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
93 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
94 MASK_BITS_31_30},
95 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
96 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
97 MASK_BITS_31_30},
98 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
99 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
100 MASK_BITS_31_29},
101 { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
102 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
103 MASK_BITS_31_29},
104 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
105 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
106 MASK_BITS_31_28},
107 /* CLOCK_TYPE_DP */
108 { CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
109 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
110 MASK_BITS_31_28},
111
112 /* Additional clock types on Tegra114+ */
113 /* CLOCK_TYPE_PC2CC3M */
114 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
115 CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
116 MASK_BITS_31_29},
117 /* CLOCK_TYPE_PC2CC3S_T */
118 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
119 CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE),
120 MASK_BITS_31_29},
121 /* CLOCK_TYPE_PC2CC3M_T */
122 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
123 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
124 MASK_BITS_31_29},
125 /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
126 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
127 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
128 MASK_BITS_31_29},
129 /* CLOCK_TYPE_MC2CC3P_A */
130 { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
131 CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE),
132 MASK_BITS_31_29},
133 /* CLOCK_TYPE_M */
134 { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
135 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
136 MASK_BITS_31_30},
137 /* CLOCK_TYPE_MCPTM2C2C3 */
138 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
139 CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE),
140 MASK_BITS_31_29},
141 /* CLOCK_TYPE_PC2CC3T_S */
142 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
143 CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE),
144 MASK_BITS_31_29},
145 /* CLOCK_TYPE_AC2CC3P_TS2 */
146 { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
147 CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),
148 MASK_BITS_31_29},
149 };
150
151 /*
152 * Clock type for each peripheral clock source. We put the name in each
153 * record just so it is easy to match things up
154 */
155 #define TYPE(name, type) type
156 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
157 /* 0x00 */
158 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
159 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
160 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
161 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M),
162 TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T),
163 TYPE(PERIPHC_05h, CLOCK_TYPE_NONE),
164 TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T),
165 TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T),
166
167 /* 0x08 */
168 TYPE(PERIPHC_08h, CLOCK_TYPE_NONE),
169 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16),
170 TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16),
171 TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE),
172 TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE),
173 TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T),
174 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
175 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
176
177 /* 0x10 */
178 TYPE(PERIPHC_10h, CLOCK_TYPE_NONE),
179 TYPE(PERIPHC_11h, CLOCK_TYPE_NONE),
180 TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A),
181 TYPE(PERIPHC_13h, CLOCK_TYPE_NONE),
182 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T),
183 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T),
184 TYPE(PERIPHC_16h, CLOCK_TYPE_NONE),
185 TYPE(PERIPHC_17h, CLOCK_TYPE_NONE),
186
187 /* 0x18 */
188 TYPE(PERIPHC_18h, CLOCK_TYPE_NONE),
189 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T),
190 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T),
191 TYPE(PERIPHC_1Bh, CLOCK_TYPE_NONE),
192 TYPE(PERIPHC_1Ch, CLOCK_TYPE_NONE),
193 TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T),
194 TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T),
195 TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T),
196
197 /* 0x20 */
198 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A),
199 TYPE(PERIPHC_21h, CLOCK_TYPE_NONE),
200 TYPE(PERIPHC_22h, CLOCK_TYPE_NONE),
201 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
202 TYPE(PERIPHC_24h, CLOCK_TYPE_NONE),
203 TYPE(PERIPHC_25h, CLOCK_TYPE_NONE),
204 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16),
205 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3),
206
207 /* 0x28 */
208 TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T),
209 TYPE(PERIPHC_29h, CLOCK_TYPE_NONE),
210 TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A),
211 TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE),
212 TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE),
213 TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T),
214 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16),
215 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T),
216
217 /* 0x30 */
218 TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T),
219 TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T),
220 TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T),
221 TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T),
222 TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T),
223 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T),
224 TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
225 TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE),
226
227 /* 0x38 */
228 TYPE(PERIPHC_38h, CLOCK_TYPE_NONE),
229 TYPE(PERIPHC_39h, CLOCK_TYPE_NONE),
230 TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE),
231 TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE),
232 TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A),
233 TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T),
234 TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE),
235 TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE),
236
237 /* 0x40 */
238 TYPE(PERIPHC_40h, CLOCK_TYPE_NONE), /* start with 0x3b0 */
239 TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T),
240 TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S),
241 TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
242 TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
243 TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16),
244 TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T),
245 TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T),
246
247 /* 0x48 */
248 TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2),
249 TYPE(PERIPHC_49h, CLOCK_TYPE_NONE),
250 TYPE(PERIPHC_DAM0, CLOCK_TYPE_AC2CC3P_TS2),
251 TYPE(PERIPHC_DAM1, CLOCK_TYPE_AC2CC3P_TS2),
252 TYPE(PERIPHC_DAM2, CLOCK_TYPE_AC2CC3P_TS2),
253 TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T),
254 TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T),
255 TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
256
257 /* 0x50 */
258 TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
259 TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
260 TYPE(PERIPHC_52h, CLOCK_TYPE_NONE),
261 TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T),
262 TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
263 TYPE(PERIPHC_55h, CLOCK_TYPE_NONE),
264 TYPE(PERIPHC_56h, CLOCK_TYPE_NONE),
265 TYPE(PERIPHC_57h, CLOCK_TYPE_NONE),
266
267 /* 0x58 */
268 TYPE(PERIPHC_58h, CLOCK_TYPE_NONE),
269 TYPE(PERIPHC_SOR, CLOCK_TYPE_NONE),
270 TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE),
271 TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE),
272 TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT),
273 TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
274 TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T),
275 TYPE(PERIPHC_5fh, CLOCK_TYPE_NONE),
276
277 /* 0x60 */
278 TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE),
279 TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE),
280 TYPE(PERIPHC_XUSB_FS, CLOCK_TYPE_NONE),
281 TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE),
282 TYPE(PERIPHC_XUSB_SS, CLOCK_TYPE_NONE),
283 TYPE(PERIPHC_CILAB, CLOCK_TYPE_NONE),
284 TYPE(PERIPHC_CILCD, CLOCK_TYPE_NONE),
285 TYPE(PERIPHC_CILE, CLOCK_TYPE_NONE),
286
287 /* 0x68 */
288 TYPE(PERIPHC_DSIA_LP, CLOCK_TYPE_NONE),
289 TYPE(PERIPHC_DSIB_LP, CLOCK_TYPE_NONE),
290 TYPE(PERIPHC_ENTROPY, CLOCK_TYPE_NONE),
291 TYPE(PERIPHC_DVFS_REF, CLOCK_TYPE_NONE),
292 TYPE(PERIPHC_DVFS_SOC, CLOCK_TYPE_NONE),
293 TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE),
294 TYPE(PERIPHC_ADX0, CLOCK_TYPE_NONE),
295 TYPE(PERIPHC_AMX0, CLOCK_TYPE_NONE),
296
297 /* 0x70 */
298 TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE),
299 TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE),
300 TYPE(PERIPHC_72h, CLOCK_TYPE_NONE),
301 TYPE(PERIPHC_73h, CLOCK_TYPE_NONE),
302 TYPE(PERIPHC_74h, CLOCK_TYPE_NONE),
303 TYPE(PERIPHC_75h, CLOCK_TYPE_NONE),
304 TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE),
305 TYPE(PERIPHC_I2C6, CLOCK_TYPE_PC2CC3M_T16),
306
307 /* 0x78 */
308 TYPE(PERIPHC_78h, CLOCK_TYPE_NONE),
309 TYPE(PERIPHC_EMC_DLL, CLOCK_TYPE_MCPTM2C2C3),
310 TYPE(PERIPHC_HDMI_AUDIO, CLOCK_TYPE_NONE),
311 TYPE(PERIPHC_CLK72MHZ, CLOCK_TYPE_NONE),
312 TYPE(PERIPHC_ADX1, CLOCK_TYPE_AC2CC3P_TS2),
313 TYPE(PERIPHC_AMX1, CLOCK_TYPE_AC2CC3P_TS2),
314 TYPE(PERIPHC_VIC, CLOCK_TYPE_NONE),
315 TYPE(PERIPHC_7Fh, CLOCK_TYPE_NONE),
316 };
317
318 /*
319 * This array translates a periph_id to a periphc_internal_id
320 *
321 * Not present/matched up:
322 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
323 * SPDIF - which is both 0x08 and 0x0c
324 *
325 */
326 #define NONE(name) (-1)
327 #define OFFSET(name, value) PERIPHC_ ## name
328 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
329 /* Low word: 31:0 */
330 NONE(CPU),
331 NONE(COP),
332 NONE(TRIGSYS),
333 NONE(ISPB),
334 NONE(RESERVED4),
335 NONE(TMR),
336 PERIPHC_UART1,
337 PERIPHC_UART2, /* and vfir 0x68 */
338
339 /* 8 */
340 NONE(GPIO),
341 PERIPHC_SDMMC2,
342 PERIPHC_SPDIF_IN,
343 PERIPHC_I2S1,
344 PERIPHC_I2C1,
345 NONE(RESERVED13),
346 PERIPHC_SDMMC1,
347 PERIPHC_SDMMC4,
348
349 /* 16 */
350 NONE(TCW),
351 PERIPHC_PWM,
352 PERIPHC_I2S2,
353 NONE(RESERVED19),
354 PERIPHC_VI,
355 NONE(RESERVED21),
356 NONE(USBD),
357 NONE(ISP),
358
359 /* 24 */
360 NONE(RESERVED24),
361 NONE(RESERVED25),
362 PERIPHC_DISP2,
363 PERIPHC_DISP1,
364 PERIPHC_HOST1X,
365 NONE(VCP),
366 PERIPHC_I2S0,
367 NONE(CACHE2),
368
369 /* Middle word: 63:32 */
370 NONE(MEM),
371 NONE(AHBDMA),
372 NONE(APBDMA),
373 NONE(RESERVED35),
374 NONE(RESERVED36),
375 NONE(STAT_MON),
376 NONE(RESERVED38),
377 NONE(FUSE),
378
379 /* 40 */
380 NONE(KFUSE),
381 PERIPHC_SBC1, /* SBCx = SPIx */
382 PERIPHC_NOR,
383 NONE(RESERVED43),
384 PERIPHC_SBC2,
385 NONE(XIO),
386 PERIPHC_SBC3,
387 PERIPHC_I2C5,
388
389 /* 48 */
390 NONE(DSI),
391 NONE(RESERVED49),
392 PERIPHC_HSI,
393 PERIPHC_HDMI,
394 NONE(CSI),
395 NONE(RESERVED53),
396 PERIPHC_I2C2,
397 PERIPHC_UART3,
398
399 /* 56 */
400 NONE(MIPI_CAL),
401 PERIPHC_EMC,
402 NONE(USB2),
403 NONE(USB3),
404 NONE(RESERVED60),
405 PERIPHC_VDE,
406 NONE(BSEA),
407 NONE(BSEV),
408
409 /* Upper word 95:64 */
410 NONE(RESERVED64),
411 PERIPHC_UART4,
412 PERIPHC_UART5,
413 PERIPHC_I2C3,
414 PERIPHC_SBC4,
415 PERIPHC_SDMMC3,
416 NONE(PCIE),
417 PERIPHC_OWR,
418
419 /* 72 */
420 NONE(AFI),
421 PERIPHC_CSITE,
422 NONE(PCIEXCLK),
423 NONE(AVPUCQ),
424 NONE(LA),
425 NONE(TRACECLKIN),
426 NONE(SOC_THERM),
427 NONE(DTV),
428
429 /* 80 */
430 NONE(RESERVED80),
431 PERIPHC_I2CSLOW,
432 NONE(DSIB),
433 PERIPHC_TSEC,
434 NONE(RESERVED84),
435 NONE(RESERVED85),
436 NONE(RESERVED86),
437 NONE(EMUCIF),
438
439 /* 88 */
440 NONE(RESERVED88),
441 NONE(XUSB_HOST),
442 NONE(RESERVED90),
443 PERIPHC_MSENC,
444 NONE(RESERVED92),
445 NONE(RESERVED93),
446 NONE(RESERVED94),
447 NONE(XUSB_DEV),
448
449 /* V word: 31:0 */
450 NONE(CPUG),
451 NONE(CPULP),
452 NONE(V_RESERVED2),
453 PERIPHC_MSELECT,
454 NONE(V_RESERVED4),
455 PERIPHC_I2S3,
456 PERIPHC_I2S4,
457 PERIPHC_I2C4,
458
459 /* 104 */
460 PERIPHC_SBC5,
461 PERIPHC_SBC6,
462 PERIPHC_AUDIO,
463 NONE(APBIF),
464 PERIPHC_DAM0,
465 PERIPHC_DAM1,
466 PERIPHC_DAM2,
467 PERIPHC_HDA2CODEC2X,
468
469 /* 112 */
470 NONE(ATOMICS),
471 NONE(V_RESERVED17),
472 NONE(V_RESERVED18),
473 NONE(V_RESERVED19),
474 NONE(V_RESERVED20),
475 NONE(V_RESERVED21),
476 NONE(V_RESERVED22),
477 PERIPHC_ACTMON,
478
479 /* 120 */
480 PERIPHC_EXTPERIPH1,
481 NONE(EXTPERIPH2),
482 NONE(EXTPERIPH3),
483 NONE(OOB),
484 PERIPHC_SATA,
485 PERIPHC_HDA,
486 NONE(TZRAM),
487 NONE(SE),
488
489 /* W word: 31:0 */
490 NONE(HDA2HDMICODEC),
491 NONE(SATACOLD),
492 NONE(W_RESERVED2),
493 NONE(W_RESERVED3),
494 NONE(W_RESERVED4),
495 NONE(W_RESERVED5),
496 NONE(W_RESERVED6),
497 NONE(W_RESERVED7),
498
499 /* 136 */
500 NONE(CEC),
501 NONE(W_RESERVED9),
502 NONE(W_RESERVED10),
503 NONE(W_RESERVED11),
504 NONE(W_RESERVED12),
505 NONE(W_RESERVED13),
506 NONE(XUSB_PADCTL),
507 NONE(W_RESERVED15),
508
509 /* 144 */
510 NONE(W_RESERVED16),
511 NONE(W_RESERVED17),
512 NONE(W_RESERVED18),
513 NONE(W_RESERVED19),
514 NONE(W_RESERVED20),
515 NONE(ENTROPY),
516 NONE(DDS),
517 NONE(W_RESERVED23),
518
519 /* 152 */
520 NONE(DP2),
521 NONE(AMX0),
522 NONE(ADX0),
523 NONE(DVFS),
524 NONE(XUSB_SS),
525 NONE(W_RESERVED29),
526 NONE(W_RESERVED30),
527 NONE(W_RESERVED31),
528
529 /* X word: 31:0 */
530 NONE(SPARE),
531 NONE(X_RESERVED1),
532 NONE(X_RESERVED2),
533 NONE(X_RESERVED3),
534 NONE(CAM_MCLK),
535 NONE(CAM_MCLK2),
536 PERIPHC_I2C6,
537 NONE(X_RESERVED7),
538
539 /* 168 */
540 NONE(X_RESERVED8),
541 NONE(X_RESERVED9),
542 NONE(X_RESERVED10),
543 NONE(VIM2_CLK),
544 NONE(X_RESERVED12),
545 NONE(X_RESERVED13),
546 NONE(EMC_DLL),
547 NONE(X_RESERVED15),
548
549 /* 176 */
550 NONE(HDMI_AUDIO),
551 NONE(CLK72MHZ),
552 NONE(VIC),
553 NONE(X_RESERVED19),
554 NONE(ADX1),
555 NONE(DPAUX),
556 PERIPHC_SOR,
557 NONE(X_RESERVED23),
558
559 /* 184 */
560 NONE(GPU),
561 NONE(AMX1),
562 NONE(X_RESERVED26),
563 NONE(X_RESERVED27),
564 NONE(X_RESERVED28),
565 NONE(X_RESERVED29),
566 NONE(X_RESERVED30),
567 NONE(X_RESERVED31),
568 };
569
570 /*
571 * PLL divider shift/mask tables for all PLL IDs.
572 */
573 struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
574 /*
575 * T124: same as T114, some deviations from T2x/T30. Adds PLLDP.
576 * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.)
577 * If lock_ena or lock_det are >31, they're not used in that PLL.
578 */
579
580 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
581 .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */
582 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
583 .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */
584 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
585 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */
586 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
587 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */
588 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
589 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */
590 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
591 .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */
592 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
593 .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */
594 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
595 .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
596 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
597 .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
598 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0xF,
599 .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */
600 };
601
602 /*
603 * Get the oscillator frequency, from the corresponding hardware configuration
604 * field. Note that Tegra30+ support 3 new higher freqs, but we map back
605 * to the old T20 freqs. Support for the higher oscillators is TBD.
606 */
clock_get_osc_freq(void)607 enum clock_osc_freq clock_get_osc_freq(void)
608 {
609 struct clk_rst_ctlr *clkrst =
610 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
611 u32 reg;
612
613 reg = readl(&clkrst->crc_osc_ctrl);
614 reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
615
616 if (reg & 1) /* one of the newer freqs */
617 printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
618
619 return reg >> 2; /* Map to most common (T20) freqs */
620 }
621
622 /* Returns a pointer to the clock source register for a peripheral */
get_periph_source_reg(enum periph_id periph_id)623 u32 *get_periph_source_reg(enum periph_id periph_id)
624 {
625 struct clk_rst_ctlr *clkrst =
626 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
627 enum periphc_internal_id internal_id;
628
629 /* Coresight is a special case */
630 if (periph_id == PERIPH_ID_CSI)
631 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
632
633 assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
634 internal_id = periph_id_to_internal_id[periph_id];
635 assert(internal_id != -1);
636 if (internal_id >= PERIPHC_X_FIRST) {
637 internal_id -= PERIPHC_X_FIRST;
638 return &clkrst->crc_clk_src_x[internal_id];
639 } else if (internal_id >= PERIPHC_VW_FIRST) {
640 internal_id -= PERIPHC_VW_FIRST;
641 return &clkrst->crc_clk_src_vw[internal_id];
642 } else {
643 return &clkrst->crc_clk_src[internal_id];
644 }
645 }
646
get_periph_clock_info(enum periph_id periph_id,int * mux_bits,int * divider_bits,int * type)647 int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
648 int *divider_bits, int *type)
649 {
650 enum periphc_internal_id internal_id;
651
652 if (!clock_periph_id_isvalid(periph_id))
653 return -1;
654
655 internal_id = periph_id_to_internal_id[periph_id];
656 if (!periphc_internal_id_isvalid(internal_id))
657 return -1;
658
659 *type = clock_periph_type[internal_id];
660 if (!clock_type_id_isvalid(*type))
661 return -1;
662
663 *mux_bits = clock_source[*type][CLOCK_MAX_MUX];
664
665 if (*type == CLOCK_TYPE_PC2CC3M_T16)
666 *divider_bits = 16;
667 else
668 *divider_bits = 8;
669
670 return 0;
671 }
672
get_periph_clock_id(enum periph_id periph_id,int source)673 enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
674 {
675 enum periphc_internal_id internal_id;
676 int type;
677
678 if (!clock_periph_id_isvalid(periph_id))
679 return CLOCK_ID_NONE;
680
681 internal_id = periph_id_to_internal_id[periph_id];
682 if (!periphc_internal_id_isvalid(internal_id))
683 return CLOCK_ID_NONE;
684
685 type = clock_periph_type[internal_id];
686 if (!clock_type_id_isvalid(type))
687 return CLOCK_ID_NONE;
688
689 return clock_source[type][source];
690 }
691
692 /**
693 * Given a peripheral ID and the required source clock, this returns which
694 * value should be programmed into the source mux for that peripheral.
695 *
696 * There is special code here to handle the one source type with 5 sources.
697 *
698 * @param periph_id peripheral to start
699 * @param source PLL id of required parent clock
700 * @param mux_bits Set to number of bits in mux register: 2 or 4
701 * @param divider_bits Set to number of divider bits (8 or 16)
702 * @return mux value (0-4, or -1 if not found)
703 */
get_periph_clock_source(enum periph_id periph_id,enum clock_id parent,int * mux_bits,int * divider_bits)704 int get_periph_clock_source(enum periph_id periph_id,
705 enum clock_id parent, int *mux_bits, int *divider_bits)
706 {
707 enum clock_type_id type;
708 int mux, err;
709
710 err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
711 assert(!err);
712
713 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
714 if (clock_source[type][mux] == parent)
715 return mux;
716
717 /* if we get here, either us or the caller has made a mistake */
718 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
719 parent);
720 return -1;
721 }
722
clock_set_enable(enum periph_id periph_id,int enable)723 void clock_set_enable(enum periph_id periph_id, int enable)
724 {
725 struct clk_rst_ctlr *clkrst =
726 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
727 u32 *clk;
728 u32 reg;
729
730 /* Enable/disable the clock to this peripheral */
731 assert(clock_periph_id_isvalid(periph_id));
732 if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
733 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
734 else if ((int)periph_id < PERIPH_ID_X_FIRST)
735 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
736 else
737 clk = &clkrst->crc_clk_out_enb_x;
738 reg = readl(clk);
739 if (enable)
740 reg |= PERIPH_MASK(periph_id);
741 else
742 reg &= ~PERIPH_MASK(periph_id);
743 writel(reg, clk);
744 }
745
reset_set_enable(enum periph_id periph_id,int enable)746 void reset_set_enable(enum periph_id periph_id, int enable)
747 {
748 struct clk_rst_ctlr *clkrst =
749 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
750 u32 *reset;
751 u32 reg;
752
753 /* Enable/disable reset to the peripheral */
754 assert(clock_periph_id_isvalid(periph_id));
755 if (periph_id < PERIPH_ID_VW_FIRST)
756 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
757 else if ((int)periph_id < PERIPH_ID_X_FIRST)
758 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
759 else
760 reset = &clkrst->crc_rst_devices_x;
761 reg = readl(reset);
762 if (enable)
763 reg |= PERIPH_MASK(periph_id);
764 else
765 reg &= ~PERIPH_MASK(periph_id);
766 writel(reg, reset);
767 }
768
769 #if CONFIG_IS_ENABLED(OF_CONTROL)
770 /*
771 * Convert a device tree clock ID to our peripheral ID. They are mostly
772 * the same but we are very cautious so we check that a valid clock ID is
773 * provided.
774 *
775 * @param clk_id Clock ID according to tegra124 device tree binding
776 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
777 */
clk_id_to_periph_id(int clk_id)778 enum periph_id clk_id_to_periph_id(int clk_id)
779 {
780 if (clk_id > PERIPH_ID_COUNT)
781 return PERIPH_ID_NONE;
782
783 switch (clk_id) {
784 case PERIPH_ID_RESERVED4:
785 case PERIPH_ID_RESERVED25:
786 case PERIPH_ID_RESERVED35:
787 case PERIPH_ID_RESERVED36:
788 case PERIPH_ID_RESERVED38:
789 case PERIPH_ID_RESERVED43:
790 case PERIPH_ID_RESERVED49:
791 case PERIPH_ID_RESERVED53:
792 case PERIPH_ID_RESERVED64:
793 case PERIPH_ID_RESERVED84:
794 case PERIPH_ID_RESERVED85:
795 case PERIPH_ID_RESERVED86:
796 case PERIPH_ID_RESERVED88:
797 case PERIPH_ID_RESERVED90:
798 case PERIPH_ID_RESERVED92:
799 case PERIPH_ID_RESERVED93:
800 case PERIPH_ID_RESERVED94:
801 case PERIPH_ID_V_RESERVED2:
802 case PERIPH_ID_V_RESERVED4:
803 case PERIPH_ID_V_RESERVED17:
804 case PERIPH_ID_V_RESERVED18:
805 case PERIPH_ID_V_RESERVED19:
806 case PERIPH_ID_V_RESERVED20:
807 case PERIPH_ID_V_RESERVED21:
808 case PERIPH_ID_V_RESERVED22:
809 case PERIPH_ID_W_RESERVED2:
810 case PERIPH_ID_W_RESERVED3:
811 case PERIPH_ID_W_RESERVED4:
812 case PERIPH_ID_W_RESERVED5:
813 case PERIPH_ID_W_RESERVED6:
814 case PERIPH_ID_W_RESERVED7:
815 case PERIPH_ID_W_RESERVED9:
816 case PERIPH_ID_W_RESERVED10:
817 case PERIPH_ID_W_RESERVED11:
818 case PERIPH_ID_W_RESERVED12:
819 case PERIPH_ID_W_RESERVED13:
820 case PERIPH_ID_W_RESERVED15:
821 case PERIPH_ID_W_RESERVED16:
822 case PERIPH_ID_W_RESERVED17:
823 case PERIPH_ID_W_RESERVED18:
824 case PERIPH_ID_W_RESERVED19:
825 case PERIPH_ID_W_RESERVED20:
826 case PERIPH_ID_W_RESERVED23:
827 case PERIPH_ID_W_RESERVED29:
828 case PERIPH_ID_W_RESERVED30:
829 case PERIPH_ID_W_RESERVED31:
830 return PERIPH_ID_NONE;
831 default:
832 return clk_id;
833 }
834 }
835 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
836
clock_early_init(void)837 void clock_early_init(void)
838 {
839 struct clk_rst_ctlr *clkrst =
840 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
841 struct clk_pll_info *pllinfo;
842 u32 data;
843
844 tegra30_set_up_pllp();
845
846 /* clear IDDQ before accessing any other PLLC registers */
847 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
848 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ);
849 udelay(2);
850
851 /*
852 * PLLC output frequency set to 600Mhz
853 * PLLD output frequency set to 925Mhz
854 */
855 switch (clock_get_osc_freq()) {
856 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
857 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
858 clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
859 break;
860
861 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
862 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
863 clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
864 break;
865
866 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
867 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
868 clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
869 break;
870 case CLOCK_OSC_FREQ_19_2:
871 default:
872 /*
873 * These are not supported. It is too early to print a
874 * message and the UART likely won't work anyway due to the
875 * oscillator being wrong.
876 */
877 break;
878 }
879
880 /* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
881 writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
882
883 /* PLLC_MISC: Set LOCK_ENABLE */
884 pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
885 setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena));
886 udelay(2);
887
888 /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1, and enable lock */
889 pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY];
890 data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift);
891 data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena);
892 writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
893 udelay(2);
894 }
895
896 /*
897 * clock_early_init_done - Check if clock_early_init() has been called
898 *
899 * Check a register that we set up to see if clock_early_init() has already
900 * been called.
901 *
902 * @return true if clock_early_init() was called, false if not
903 */
clock_early_init_done(void)904 bool clock_early_init_done(void)
905 {
906 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
907 u32 val;
908
909 val = readl(&clkrst->crc_sclk_brst_pol);
910
911 return val == 0x20002222;
912 }
913
arch_timer_init(void)914 void arch_timer_init(void)
915 {
916 struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
917 u32 freq, val;
918
919 freq = clock_get_rate(CLOCK_ID_CLK_M);
920 debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
921
922 /* ARM CNTFRQ */
923 asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
924
925 /* Only Tegra114+ has the System Counter regs */
926 debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
927 writel(freq, &sysctr->cntfid0);
928
929 val = readl(&sysctr->cntcr);
930 val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
931 writel(val, &sysctr->cntcr);
932 debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
933 }
934
935 #define PLLE_SS_CNTL 0x68
936 #define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24)
937 #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
938 #define PLLE_SS_CNTL_SSCINVERT (1 << 15)
939 #define PLLE_SS_CNTL_SSCCENTER (1 << 14)
940 #define PLLE_SS_CNTL_SSCBYP (1 << 12)
941 #define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
942 #define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
943 #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
944
945 #define PLLE_BASE 0x0e8
946 #define PLLE_BASE_ENABLE (1 << 30)
947 #define PLLE_BASE_LOCK_OVERRIDE (1 << 29)
948 #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
949 #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
950 #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
951
952 #define PLLE_MISC 0x0ec
953 #define PLLE_MISC_IDDQ_SWCTL (1 << 14)
954 #define PLLE_MISC_IDDQ_OVERRIDE (1 << 13)
955 #define PLLE_MISC_LOCK_ENABLE (1 << 9)
956 #define PLLE_MISC_PTS (1 << 8)
957 #define PLLE_MISC_VREG_BG_CTRL(x) (((x) & 0x3) << 4)
958 #define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2)
959
960 #define PLLE_AUX 0x48c
961 #define PLLE_AUX_SEQ_ENABLE (1 << 24)
962 #define PLLE_AUX_ENABLE_SWCTL (1 << 4)
963
tegra_plle_enable(void)964 int tegra_plle_enable(void)
965 {
966 unsigned int m = 1, n = 200, cpcon = 13;
967 u32 value;
968
969 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
970 value &= ~PLLE_BASE_LOCK_OVERRIDE;
971 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
972
973 value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
974 value |= PLLE_AUX_ENABLE_SWCTL;
975 value &= ~PLLE_AUX_SEQ_ENABLE;
976 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
977
978 udelay(1);
979
980 value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
981 value |= PLLE_MISC_IDDQ_SWCTL;
982 value &= ~PLLE_MISC_IDDQ_OVERRIDE;
983 value |= PLLE_MISC_LOCK_ENABLE;
984 value |= PLLE_MISC_PTS;
985 value |= PLLE_MISC_VREG_BG_CTRL(3);
986 value |= PLLE_MISC_VREG_CTRL(2);
987 writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
988
989 udelay(5);
990
991 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
992 value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
993 PLLE_SS_CNTL_BYPASS_SS;
994 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
995
996 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
997 value &= ~PLLE_BASE_PLDIV_CML(0xf);
998 value &= ~PLLE_BASE_NDIV(0xff);
999 value &= ~PLLE_BASE_MDIV(0xff);
1000 value |= PLLE_BASE_PLDIV_CML(cpcon);
1001 value |= PLLE_BASE_NDIV(n);
1002 value |= PLLE_BASE_MDIV(m);
1003 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
1004
1005 udelay(1);
1006
1007 value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
1008 value |= PLLE_BASE_ENABLE;
1009 writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
1010
1011 /* wait for lock */
1012 udelay(300);
1013
1014 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1015 value &= ~PLLE_SS_CNTL_SSCINVERT;
1016 value &= ~PLLE_SS_CNTL_SSCCENTER;
1017
1018 value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f);
1019 value &= ~PLLE_SS_CNTL_SSCINC(0xff);
1020 value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
1021
1022 value |= PLLE_SS_CNTL_SSCINCINTR(0x20);
1023 value |= PLLE_SS_CNTL_SSCINC(0x01);
1024 value |= PLLE_SS_CNTL_SSCMAX(0x25);
1025
1026 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1027
1028 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1029 value &= ~PLLE_SS_CNTL_SSCBYP;
1030 value &= ~PLLE_SS_CNTL_BYPASS_SS;
1031 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1032
1033 udelay(1);
1034
1035 value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1036 value &= ~PLLE_SS_CNTL_INTERP_RESET;
1037 writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
1038
1039 udelay(1);
1040
1041 return 0;
1042 }
1043
clock_sor_enable_edp_clock(void)1044 void clock_sor_enable_edp_clock(void)
1045 {
1046 u32 *reg;
1047
1048 /* uses PLLP, has a non-standard bit layout. */
1049 reg = get_periph_source_reg(PERIPH_ID_SOR0);
1050 setbits_le32(reg, SOR0_CLK_SEL0);
1051 }
1052
clock_set_display_rate(u32 frequency)1053 u32 clock_set_display_rate(u32 frequency)
1054 {
1055 /**
1056 * plld (fo) = vco >> p, where 500MHz < vco < 1000MHz
1057 * = (cf * n) >> p, where 1MHz < cf < 6MHz
1058 * = ((ref / m) * n) >> p
1059 *
1060 * Iterate the possible values of p (3 bits, 2^7) to find out a minimum
1061 * safe vco, then find best (m, n). since m has only 5 bits, we can
1062 * iterate all possible values. Note Tegra 124 supports 11 bits for n,
1063 * but our pll_fields has only 10 bits for n.
1064 *
1065 * Note values undershoot or overshoot target output frequency may not
1066 * work if the values are not in "safe" range by panel specification.
1067 */
1068 u32 ref = clock_get_rate(CLOCK_ID_OSC);
1069 u32 divm, divn, divp, cpcon;
1070 u32 cf, vco, rounded_rate = frequency;
1071 u32 diff, best_diff, best_m = 0, best_n = 0, best_p;
1072 const u32 max_m = 1 << 5, max_n = 1 << 10, max_p = 1 << 3,
1073 mhz = 1000 * 1000, min_vco = 500 * mhz, max_vco = 1000 * mhz,
1074 min_cf = 1 * mhz, max_cf = 6 * mhz;
1075 int mux_bits, divider_bits, source;
1076
1077 for (divp = 0, vco = frequency; vco < min_vco && divp < max_p; divp++)
1078 vco <<= 1;
1079
1080 if (vco < min_vco || vco > max_vco) {
1081 printf("%s: Cannot find out a supported VCO for Frequency (%u)\n",
1082 __func__, frequency);
1083 return 0;
1084 }
1085
1086 best_p = divp;
1087 best_diff = vco;
1088
1089 for (divm = 1; divm < max_m && best_diff; divm++) {
1090 cf = ref / divm;
1091 if (cf < min_cf)
1092 break;
1093 if (cf > max_cf)
1094 continue;
1095
1096 divn = vco / cf;
1097 if (divn >= max_n)
1098 continue;
1099
1100 diff = vco - divn * cf;
1101 if (divn + 1 < max_n && diff > cf / 2) {
1102 divn++;
1103 diff = cf - diff;
1104 }
1105
1106 if (diff >= best_diff)
1107 continue;
1108
1109 best_diff = diff;
1110 best_m = divm;
1111 best_n = divn;
1112 }
1113
1114 if (best_n < 50)
1115 cpcon = 2;
1116 else if (best_n < 300)
1117 cpcon = 3;
1118 else if (best_n < 600)
1119 cpcon = 8;
1120 else
1121 cpcon = 12;
1122
1123 if (best_diff) {
1124 printf("%s: Failed to match output frequency %u, best difference is %u\n",
1125 __func__, frequency, best_diff);
1126 rounded_rate = (ref / best_m * best_n) >> best_p;
1127 }
1128
1129 debug("%s: PLLD=%u ref=%u, m/n/p/cpcon=%u/%u/%u/%u\n",
1130 __func__, rounded_rate, ref, best_m, best_n, best_p, cpcon);
1131
1132 source = get_periph_clock_source(PERIPH_ID_DISP1, CLOCK_ID_DISPLAY,
1133 &mux_bits, ÷r_bits);
1134 clock_ll_set_source_bits(PERIPH_ID_DISP1, mux_bits, source);
1135 clock_set_rate(CLOCK_ID_DISPLAY, best_n, best_m, best_p, cpcon);
1136
1137 return rounded_rate;
1138 }
1139
clock_set_up_plldp(void)1140 void clock_set_up_plldp(void)
1141 {
1142 struct clk_rst_ctlr *clkrst =
1143 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
1144 u32 value;
1145
1146 value = PLLDP_SS_CFG_UNDOCUMENTED | PLLDP_SS_CFG_DITHER;
1147 writel(value | PLLDP_SS_CFG_CLAMP, &clkrst->crc_plldp_ss_cfg);
1148 clock_start_pll(CLOCK_ID_DP, 1, 90, 3, 0, 0);
1149 writel(value, &clkrst->crc_plldp_ss_cfg);
1150 }
1151
clock_get_simple_pll(enum clock_id clkid)1152 struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
1153 {
1154 struct clk_rst_ctlr *clkrst =
1155 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
1156
1157 if (clkid == CLOCK_ID_DP)
1158 return &clkrst->plldp;
1159
1160 return NULL;
1161 }
1162
1163 struct periph_clk_init periph_clk_init_table[] = {
1164 { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
1165 { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
1166 { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
1167 { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
1168 { PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
1169 { PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
1170 { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
1171 { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
1172 { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
1173 { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
1174 { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
1175 { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
1176 { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
1177 { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
1178 { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
1179 { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
1180 { PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
1181 { PERIPH_ID_I2C5, CLOCK_ID_PERIPH },
1182 { PERIPH_ID_I2C6, CLOCK_ID_PERIPH },
1183 { -1, },
1184 };
1185