1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2020 Marvell International Ltd.
4 *
5 * Interface to PCIe as a host(RC) or target(EP)
6 */
7
8 #include <log.h>
9 #include <linux/delay.h>
10 #include <linux/libfdt.h>
11
12 #include <mach/cvmx-regs.h>
13 #include <mach/octeon-model.h>
14 #include <mach/cvmx-fuse.h>
15 #include <mach/octeon-feature.h>
16 #include <mach/cvmx-qlm.h>
17 #include <mach/octeon_qlm.h>
18
19 #include <mach/cvmx-helper-fdt.h>
20
21 #include <mach/cvmx-regs.h>
22 #include <mach/octeon-model.h>
23 #include <mach/cvmx-fuse.h>
24 #include <mach/octeon-feature.h>
25 #include <mach/cvmx-qlm.h>
26 #include <mach/octeon_qlm.h>
27 #include <mach/cvmx-pcie.h>
28 #include <mach/cvmx-error.h>
29 #include <mach/cvmx-helper.h>
30 #include <mach/cvmx-helper-util.h>
31 #include <mach/cvmx-bgxx-defs.h>
32 #include <mach/cvmx-ciu-defs.h>
33 #include <mach/cvmx-gmxx-defs.h>
34 #include <mach/cvmx-gserx-defs.h>
35 #include <mach/cvmx-mio-defs.h>
36 #include <mach/cvmx-pciercx-defs.h>
37 #include <mach/cvmx-pcieepx-defs.h>
38 #include <mach/cvmx-pemx-defs.h>
39 #include <mach/cvmx-pexp-defs.h>
40 #include <mach/cvmx-rst-defs.h>
41 #include <mach/cvmx-sata-defs.h>
42 #include <mach/cvmx-sli-defs.h>
43 #include <mach/cvmx-sriomaintx-defs.h>
44 #include <mach/cvmx-sriox-defs.h>
45
46 #include <mach/cvmx-dpi-defs.h>
47 #include <mach/cvmx-sli-defs.h>
48 #include <mach/cvmx-dtx-defs.h>
49
50 DECLARE_GLOBAL_DATA_PTR;
51
52 #define MRRS_CN6XXX 3 /* 1024 byte Max Read Request Size */
53 #define MPS_CN6XXX 0 /* 128 byte Max Packet Size (Limit of most PCs) */
54
55 /* Endian swap mode. */
56 #define _CVMX_PCIE_ES 1
57
58 #define CVMX_READ_CSR(addr) csr_rd_node(node, addr)
59 #define CVMX_WRITE_CSR(addr, val) csr_wr_node(node, addr, val)
60 #define CVMX_PCIE_CFGX_READ(p, addr) cvmx_pcie_cfgx_read_node(node, p, addr)
61 #define CVMX_PCIE_CFGX_WRITE(p, addr, val) cvmx_pcie_cfgx_write_node(node, p, addr, val)
62
63 /* #define DEBUG_PCIE */
64
65 /* Delay after link up, before issuing first configuration read */
66 #define PCIE_DEVICE_READY_WAIT_DELAY_MICROSECONDS 700000
67
68 /* Recommended Preset Vector: Drop Preset 10 */
69 int pcie_preset_vec[4] = { 0x593, 0x593, 0x593, 0x593 };
70
71 /* Number of LTSSM transitions to record, must be a power of 2 */
72 #define LTSSM_HISTORY_SIZE 64
73 #define MAX_RETRIES 2
74
75 bool pcie_link_initialized[CVMX_MAX_NODES][CVMX_PCIE_MAX_PORTS];
76 int cvmx_primary_pcie_bus_number = 1;
77
78 static uint32_t __cvmx_pcie_config_read32(int node, int pcie_port, int bus, int dev, int func,
79 int reg, int lst);
80
81 /**
82 * Return the Core virtual base address for PCIe IO access. IOs are
83 * read/written as an offset from this address.
84 *
85 * @param pcie_port PCIe port the IO is for
86 *
87 * @return 64bit Octeon IO base address for read/write
88 */
cvmx_pcie_get_io_base_address(int pcie_port)89 uint64_t cvmx_pcie_get_io_base_address(int pcie_port)
90 {
91 cvmx_pcie_address_t pcie_addr;
92
93 pcie_addr.u64 = 0;
94 pcie_addr.io.upper = 0;
95 pcie_addr.io.io = 1;
96 pcie_addr.io.did = 3;
97 pcie_addr.io.subdid = 2;
98 pcie_addr.io.node = (pcie_port >> 4) & 0x3;
99 pcie_addr.io.es = _CVMX_PCIE_ES;
100 pcie_addr.io.port = (pcie_port & 0x3);
101 return pcie_addr.u64;
102 }
103
104 /**
105 * Size of the IO address region returned at address
106 * cvmx_pcie_get_io_base_address()
107 *
108 * @param pcie_port PCIe port the IO is for
109 *
110 * @return Size of the IO window
111 */
cvmx_pcie_get_io_size(int pcie_port)112 uint64_t cvmx_pcie_get_io_size(int pcie_port)
113 {
114 return 1ull << 32;
115 }
116
117 /**
118 * Return the Core virtual base address for PCIe MEM access. Memory is
119 * read/written as an offset from this address.
120 *
121 * @param pcie_port PCIe port the IO is for
122 *
123 * @return 64bit Octeon IO base address for read/write
124 */
cvmx_pcie_get_mem_base_address(int pcie_port)125 uint64_t cvmx_pcie_get_mem_base_address(int pcie_port)
126 {
127 cvmx_pcie_address_t pcie_addr;
128
129 pcie_addr.u64 = 0;
130 pcie_addr.mem.upper = 0;
131 pcie_addr.mem.io = 1;
132 pcie_addr.mem.did = 3;
133 pcie_addr.mem.subdid = 3 + (pcie_port & 0x3);
134 pcie_addr.mem.node = (pcie_port >> 4) & 0x3;
135 return pcie_addr.u64;
136 }
137
138 /**
139 * Size of the Mem address region returned at address
140 * cvmx_pcie_get_mem_base_address()
141 *
142 * @param pcie_port PCIe port the IO is for
143 *
144 * @return Size of the Mem window
145 */
cvmx_pcie_get_mem_size(int pcie_port)146 uint64_t cvmx_pcie_get_mem_size(int pcie_port)
147 {
148 return 1ull << 36;
149 }
150
151 /**
152 * @INTERNAL
153 * Return the QLM number for the PCIE port.
154 *
155 * @param pcie_port QLM number to return for.
156 *
157 * @return QLM number.
158 */
__cvmx_pcie_get_qlm(int node,int pcie_port)159 static int __cvmx_pcie_get_qlm(int node, int pcie_port)
160 {
161 if (OCTEON_IS_MODEL(OCTEON_CN73XX)) {
162 cvmx_pemx_cfg_t pem_cfg;
163 cvmx_pemx_qlm_t pem_qlm;
164 cvmx_gserx_cfg_t gserx_cfg;
165
166 switch (pcie_port) {
167 case 0: /* PEM0 */
168 gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(0));
169 if (gserx_cfg.s.pcie)
170 return 0; /* PEM0 is on QLM0 and possibly QLM1 */
171 else
172 return -1; /* PEM0 is disabled */
173 case 1: /* PEM1 */
174 pem_cfg.u64 = CVMX_READ_CSR(CVMX_PEMX_CFG(0));
175 gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(1));
176 if (!pem_cfg.cn78xx.lanes8 && gserx_cfg.s.pcie)
177 return 1; /* PEM1 is on QLM 1 */
178 else
179 return -1; /* PEM1 is disabled */
180 case 2: /* PEM2 */
181 pem_qlm.u64 = CVMX_READ_CSR(CVMX_PEMX_QLM(2));
182 if (pem_qlm.cn73xx.pemdlmsel == 1) {
183 gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(5));
184 if (gserx_cfg.s.pcie)
185 return 5; /* PEM2 is on DLM5 */
186 else
187 return -1; /* PEM2 is disabled */
188 }
189 gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(2));
190 if (gserx_cfg.s.pcie)
191 return 2; /* PEM2 is on QLM2 and possibly QLM3 */
192 else
193 return -1; /* PEM2 is disabled */
194 case 3: /* PEM3 */
195 pem_qlm.u64 = CVMX_READ_CSR(CVMX_PEMX_QLM(3));
196 if (pem_qlm.cn73xx.pemdlmsel == 1) {
197 gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(6));
198 if (gserx_cfg.s.pcie)
199 return 6; /* PEM2 is on DLM5 */
200 else
201 return -1; /* PEM2 is disabled */
202 }
203 pem_cfg.u64 = CVMX_READ_CSR(CVMX_PEMX_CFG(2));
204 gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(3));
205 if (!pem_cfg.cn78xx.lanes8 && gserx_cfg.s.pcie)
206 return 3; /* PEM2 is on QLM2 and possibly QLM3 */
207 else
208 return -1; /* PEM2 is disabled */
209 default:
210 printf("Invalid %d PCIe port\n", pcie_port);
211 return -2;
212 }
213 } else if (OCTEON_IS_MODEL(OCTEON_CN78XX)) {
214 cvmx_pemx_cfg_t pem_cfg;
215 cvmx_gserx_cfg_t gserx_cfg;
216
217 switch (pcie_port) {
218 case 0:
219 gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(0));
220 if (gserx_cfg.s.pcie)
221 return 0; /* PEM0 is on QLM0 and possibly QLM1 */
222 else
223 return -1; /* PEM0 is disabled */
224 case 1: /* PEM1 */
225 pem_cfg.u64 = CVMX_READ_CSR(CVMX_PEMX_CFG(0));
226 gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(1));
227 if (!pem_cfg.cn78xx.lanes8 && gserx_cfg.s.pcie)
228 return 1; /* PEM1 is on QLM 1 */
229 else
230 return -1; /* PEM1 is disabled */
231 case 2: /* PEM2 */
232 gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(2));
233 if (gserx_cfg.s.pcie)
234 return 2; /* PEM2 is on QLM2 and possibly QLM3 */
235 else
236 return -1; /* PEM2 is disabled */
237 case 3: /* PEM3 */
238 {
239 cvmx_gserx_cfg_t gser4_cfg;
240
241 pem_cfg.u64 = CVMX_READ_CSR(CVMX_PEMX_CFG(2));
242 gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(3));
243 gser4_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(4));
244 if (pem_cfg.cn78xx.lanes8) {
245 if (gser4_cfg.s.pcie)
246 return 4; /* PEM3 is on QLM4 */
247 else
248 return -1; /* PEM3 is disabled */
249 } else {
250 if (gserx_cfg.s.pcie)
251 return 3; /* PEM3 is on QLM3 */
252 else if (gser4_cfg.s.pcie)
253 return 4; /* PEM3 is on QLM4 */
254 else
255 return -1; /* PEM3 is disabled */
256 }
257 }
258 default:
259 printf("Invalid %d PCIe port\n", pcie_port);
260 return -1;
261 }
262 } else if (OCTEON_IS_MODEL(OCTEON_CN70XX)) {
263 enum cvmx_qlm_mode mode1 = cvmx_qlm_get_mode(1);
264 enum cvmx_qlm_mode mode2 = cvmx_qlm_get_mode(2);
265
266 switch (pcie_port) {
267 case 0: /* PCIe0 can be DLM1 with 1, 2 or 4 lanes */
268 if (mode1 == CVMX_QLM_MODE_PCIE || /* Using DLM 1-2 */
269 mode1 == CVMX_QLM_MODE_PCIE_1X2 || /* Using DLM 1 */
270 mode1 == CVMX_QLM_MODE_PCIE_2X1 || /* Using DLM 1, lane 0 */
271 mode1 == CVMX_QLM_MODE_PCIE_1X1) /* Using DLM 1, l0, l1 not used */
272 return 1;
273 else
274 return -1;
275 case 1: /* PCIe1 can be DLM1 1 lane(1), DLM2 1 lane(0) or 2 lanes(0-1) */
276 if (mode1 == CVMX_QLM_MODE_PCIE_2X1)
277 return 1;
278 else if (mode2 == CVMX_QLM_MODE_PCIE_1X2)
279 return 2;
280 else if (mode2 == CVMX_QLM_MODE_PCIE_2X1)
281 return 2;
282 else
283 return -1;
284 case 2: /* PCIe2 can be DLM2 1 lanes(1) */
285 if (mode2 == CVMX_QLM_MODE_PCIE_2X1)
286 return 2;
287 else
288 return -1;
289 default: /* Only three PEM blocks */
290 return -1;
291 }
292 } else if (OCTEON_IS_MODEL(OCTEON_CNF75XX)) {
293 cvmx_gserx_cfg_t gserx_cfg;
294
295 switch (pcie_port) {
296 case 0: /* PEM0 */
297 gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(0));
298 if (gserx_cfg.s.pcie)
299 return 0; /* PEM0 is on QLM0 and possibly QLM1 */
300 else
301 return -1; /* PEM0 is disabled */
302 case 1: /* PEM1 */
303 gserx_cfg.u64 = CVMX_READ_CSR(CVMX_GSERX_CFG(1));
304 if (gserx_cfg.s.pcie)
305 return 1; /* PEM1 is on DLM1 */
306 else
307 return -1; /* PEM1 is disabled */
308 default:
309 return -1;
310 }
311 }
312 return -1;
313 }
314
315 /**
316 * @INTERNAL
317 * Initialize the RC config space CSRs
318 *
319 * @param node node
320 * @param pcie_port PCIe port to initialize
321 */
__cvmx_pcie_rc_initialize_config_space(int node,int pcie_port)322 static void __cvmx_pcie_rc_initialize_config_space(int node, int pcie_port)
323 {
324 /* Max Payload Size (PCIE*_CFG030[MPS]) */
325 /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
326 /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
327 /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
328 {
329 cvmx_pciercx_cfg030_t pciercx_cfg030;
330
331 pciercx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port,
332 CVMX_PCIERCX_CFG030(pcie_port));
333 pciercx_cfg030.s.mps = MPS_CN6XXX;
334 pciercx_cfg030.s.mrrs = MRRS_CN6XXX;
335 /*
336 * Enable relaxed order processing. This will allow devices
337 * to affect read response ordering
338 */
339 pciercx_cfg030.s.ro_en = 1;
340 /* Enable no snoop processing. Not used by Octeon */
341 pciercx_cfg030.s.ns_en = 1;
342 /* Correctable error reporting enable. */
343 pciercx_cfg030.s.ce_en = 1;
344 /* Non-fatal error reporting enable. */
345 pciercx_cfg030.s.nfe_en = 1;
346 /* Fatal error reporting enable. */
347 pciercx_cfg030.s.fe_en = 1;
348 /* Unsupported request reporting enable. */
349 pciercx_cfg030.s.ur_en = 1;
350 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG030(pcie_port),
351 pciercx_cfg030.u32);
352 }
353
354 /*
355 * Max Payload Size (DPI_SLI_PRTX_CFG[MPS]) must match
356 * PCIE*_CFG030[MPS]
357 */
358 /*
359 * Max Read Request Size (DPI_SLI_PRTX_CFG[MRRS]) must not exceed
360 * PCIE*_CFG030[MRRS]
361 */
362 cvmx_dpi_sli_prtx_cfg_t prt_cfg;
363 cvmx_sli_s2m_portx_ctl_t sli_s2m_portx_ctl;
364
365 prt_cfg.u64 = CVMX_READ_CSR(CVMX_DPI_SLI_PRTX_CFG(pcie_port));
366 prt_cfg.s.mps = MPS_CN6XXX;
367 prt_cfg.s.mrrs = MRRS_CN6XXX;
368 /* Max outstanding load request. */
369 prt_cfg.s.molr = 32;
370 CVMX_WRITE_CSR(CVMX_DPI_SLI_PRTX_CFG(pcie_port), prt_cfg.u64);
371
372 sli_s2m_portx_ctl.u64 = CVMX_READ_CSR(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port));
373 if (!(OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN73XX) ||
374 OCTEON_IS_MODEL(OCTEON_CNF75XX)))
375 sli_s2m_portx_ctl.cn61xx.mrrs = MRRS_CN6XXX;
376 CVMX_WRITE_CSR(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port), sli_s2m_portx_ctl.u64);
377
378 /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
379 {
380 cvmx_pciercx_cfg070_t pciercx_cfg070;
381
382 pciercx_cfg070.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
383 pciercx_cfg070.s.ge = 1; /* ECRC generation enable. */
384 pciercx_cfg070.s.ce = 1; /* ECRC check enable. */
385 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG070(pcie_port), pciercx_cfg070.u32);
386 }
387
388 /* Access Enables (PCIE*_CFG001[MSAE,ME]) */
389 /* ME and MSAE should always be set. */
390 /* Interrupt Disable (PCIE*_CFG001[I_DIS]) */
391 /* System Error Message Enable (PCIE*_CFG001[SEE]) */
392 {
393 cvmx_pciercx_cfg001_t pciercx_cfg001;
394
395 pciercx_cfg001.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
396 pciercx_cfg001.s.msae = 1; /* Memory space enable. */
397 pciercx_cfg001.s.me = 1; /* Bus master enable. */
398 pciercx_cfg001.s.i_dis = 1; /* INTx assertion disable. */
399 pciercx_cfg001.s.see = 1; /* SERR# enable */
400 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG001(pcie_port), pciercx_cfg001.u32);
401 }
402
403 /* Advanced Error Recovery Message Enables */
404 /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */
405 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG066(pcie_port), 0);
406 /* Use CVMX_PCIERCX_CFG067 hardware default */
407 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0);
408
409 /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
410 {
411 cvmx_pciercx_cfg032_t pciercx_cfg032;
412
413 pciercx_cfg032.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
414 pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */
415 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG032(pcie_port), pciercx_cfg032.u32);
416 }
417
418 /* Link Width Mode (PCIERCn_CFG452[LME]) - Set during
419 * cvmx_pcie_rc_initialize_link()
420 */
421 /* Primary Bus Number (PCIERCn_CFG006[PBNUM]) */
422 {
423 /* We set the primary bus number to 1 so IDT bridges are happy.
424 * They don't like zero
425 */
426 cvmx_pciercx_cfg006_t pciercx_cfg006;
427
428 pciercx_cfg006.u32 = 0;
429 pciercx_cfg006.s.pbnum = cvmx_primary_pcie_bus_number;
430 pciercx_cfg006.s.sbnum = cvmx_primary_pcie_bus_number;
431 pciercx_cfg006.s.subbnum = cvmx_primary_pcie_bus_number;
432 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG006(pcie_port), pciercx_cfg006.u32);
433 }
434
435 /* Memory-mapped I/O BAR (PCIERCn_CFG008) */
436 /* Most applications should disable the memory-mapped I/O BAR by */
437 /* setting PCIERCn_CFG008[ML_ADDR] < PCIERCn_CFG008[MB_ADDR] */
438 {
439 cvmx_pciercx_cfg008_t pciercx_cfg008;
440
441 pciercx_cfg008.u32 = 0;
442 pciercx_cfg008.s.mb_addr = 0x100;
443 pciercx_cfg008.s.ml_addr = 0;
444 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG008(pcie_port), pciercx_cfg008.u32);
445 }
446
447 /* Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011) */
448 /* Most applications should disable the prefetchable BAR by setting */
449 /* PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] < */
450 /* PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE] */
451 {
452 cvmx_pciercx_cfg009_t pciercx_cfg009;
453 cvmx_pciercx_cfg010_t pciercx_cfg010;
454 cvmx_pciercx_cfg011_t pciercx_cfg011;
455
456 pciercx_cfg009.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));
457 pciercx_cfg010.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
458 pciercx_cfg011.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
459 pciercx_cfg009.s.lmem_base = 0x100;
460 pciercx_cfg009.s.lmem_limit = 0;
461 pciercx_cfg010.s.umem_base = 0x100;
462 pciercx_cfg011.s.umem_limit = 0;
463 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG009(pcie_port), pciercx_cfg009.u32);
464 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32);
465 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG011(pcie_port), pciercx_cfg011.u32);
466 }
467
468 /* System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE]) */
469 /* PME Interrupt Enables (PCIERCn_CFG035[PMEIE]) */
470 {
471 cvmx_pciercx_cfg035_t pciercx_cfg035;
472
473 pciercx_cfg035.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));
474 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */
475 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */
476 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */
477 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */
478 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32);
479 }
480
481 /* Advanced Error Recovery Interrupt Enables */
482 /* (PCIERCn_CFG075[CERE,NFERE,FERE]) */
483 {
484 cvmx_pciercx_cfg075_t pciercx_cfg075;
485
486 pciercx_cfg075.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));
487 pciercx_cfg075.s.cere = 1; /* Correctable error reporting enable. */
488 pciercx_cfg075.s.nfere = 1; /* Non-fatal error reporting enable. */
489 pciercx_cfg075.s.fere = 1; /* Fatal error reporting enable. */
490 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG075(pcie_port), pciercx_cfg075.u32);
491 }
492
493 /* HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN], */
494 /* PCIERCn_CFG034[DLLS_EN,CCINT_EN]) */
495 {
496 cvmx_pciercx_cfg034_t pciercx_cfg034;
497
498 pciercx_cfg034.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));
499 pciercx_cfg034.s.hpint_en = 1; /* Hot-plug interrupt enable. */
500 pciercx_cfg034.s.dlls_en = 1; /* Data Link Layer state changed enable */
501 pciercx_cfg034.s.ccint_en = 1; /* Command completed interrupt enable. */
502 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG034(pcie_port), pciercx_cfg034.u32);
503 }
504
505 if (OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN73XX) ||
506 OCTEON_IS_MODEL(OCTEON_CNF75XX)) {
507 int qlm = __cvmx_pcie_get_qlm(node, pcie_port);
508 int speed = cvmx_qlm_get_gbaud_mhz(qlm);
509 cvmx_pemx_cfg_t pem_cfg;
510 cvmx_pciercx_cfg031_t cfg031;
511 cvmx_pciercx_cfg040_t cfg040;
512 cvmx_pciercx_cfg452_t cfg452;
513 cvmx_pciercx_cfg089_t cfg089;
514 cvmx_pciercx_cfg090_t cfg090;
515 cvmx_pciercx_cfg091_t cfg091;
516 cvmx_pciercx_cfg092_t cfg092;
517 cvmx_pciercx_cfg554_t cfg554;
518
519 /*
520 * Make sure the PEM agrees with GSERX about the speed
521 * its going to try
522 */
523 switch (speed) {
524 case 2500: /* Gen1 */
525 pem_cfg.u64 = CVMX_READ_CSR(CVMX_PEMX_CFG(pcie_port));
526 pem_cfg.s.md = 0;
527 CVMX_WRITE_CSR(CVMX_PEMX_CFG(pcie_port), pem_cfg.u64);
528
529 /* Set the target link speed */
530 cfg040.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG040(pcie_port));
531 cfg040.s.tls = 1;
532 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG040(pcie_port), cfg040.u32);
533 break;
534 case 5000: /* Gen2 */
535 pem_cfg.u64 = CVMX_READ_CSR(CVMX_PEMX_CFG(pcie_port));
536 pem_cfg.s.md = 1;
537 CVMX_WRITE_CSR(CVMX_PEMX_CFG(pcie_port), pem_cfg.u64);
538
539 /* Set the target link speed */
540 cfg040.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG040(pcie_port));
541 cfg040.s.tls = 2;
542 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG040(pcie_port), cfg040.u32);
543 break;
544 case 8000: /* Gen3 */
545 pem_cfg.u64 = CVMX_READ_CSR(CVMX_PEMX_CFG(pcie_port));
546 pem_cfg.s.md = 2;
547 CVMX_WRITE_CSR(CVMX_PEMX_CFG(pcie_port), pem_cfg.u64);
548
549 /* Set the target link speed */
550 cfg040.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG040(pcie_port));
551 cfg040.s.tls = 3;
552 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG040(pcie_port), cfg040.u32);
553 break;
554 default:
555 break;
556 }
557
558 /* Link Width Mode (PCIERCn_CFG452[LME]) */
559 pem_cfg.u64 = CVMX_READ_CSR(CVMX_PEMX_CFG(pcie_port));
560 cfg452.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
561 if (qlm >= 5)
562 cfg452.s.lme = 0x3;
563 else
564 cfg452.s.lme = (pem_cfg.cn78xx.lanes8) ? 0xf : 0x7;
565 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG452(pcie_port), cfg452.u32);
566
567 /* Errata PEM-25990 - Disable ASLPMS */
568 cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG031(pcie_port));
569 cfg031.s.aslpms = 0;
570 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG031(pcie_port), cfg031.u32);
571
572 /* CFG554.PRV default changed from 16'h7ff to 16'h593. */
573 cfg554.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG554(pcie_port));
574 cfg554.s.prv = pcie_preset_vec[pcie_port];
575 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG554(pcie_port), cfg554.u32);
576 /* Errata PEM-26189 - Disable the 2ms timer on all chips */
577 cfg554.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG554(pcie_port));
578 cfg554.s.p23td = 1;
579 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG554(pcie_port), cfg554.u32);
580
581 /* Errata PEM-21178 - Change the CFG[089-092] LxUTP & LxDTP defaults. */
582 cfg089.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG089(pcie_port));
583 cfg089.s.l1ddtp = 7;
584 cfg089.s.l1utp = 7;
585 cfg089.s.l0dtp = 7;
586 cfg089.s.l0utp = 7;
587 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG089(pcie_port), cfg089.u32);
588 cfg090.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG090(pcie_port));
589 cfg090.s.l3dtp = 7;
590 cfg090.s.l3utp = 7;
591 cfg090.s.l2dtp = 7;
592 cfg090.s.l2utp = 7;
593 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG090(pcie_port), cfg090.u32);
594 cfg091.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG091(pcie_port));
595 cfg091.s.l5dtp = 7;
596 cfg091.s.l5utp = 7;
597 cfg091.s.l4dtp = 7;
598 cfg091.s.l4utp = 7;
599 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG091(pcie_port), cfg091.u32);
600 cfg092.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG092(pcie_port));
601 cfg092.s.l7dtp = 7;
602 cfg092.s.l7utp = 7;
603 cfg092.s.l6dtp = 7;
604 cfg092.s.l6utp = 7;
605 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG092(pcie_port), cfg092.u32);
606 }
607 }
608
__cvmx_increment_ba(cvmx_sli_mem_access_subidx_t * pmas)609 static void __cvmx_increment_ba(cvmx_sli_mem_access_subidx_t *pmas)
610 {
611 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
612 pmas->cn68xx.ba++;
613 else
614 pmas->cn63xx.ba++;
615 }
616
617 /*
618 * milliseconds to retry PCIe cfg-space access:
619 * Value 32(unscaled) was recommended in HRM, but may be too small for
620 * some PCIe devices. This 200mS default should cover most devices,
621 * but can be extended by bootparam cvmx-pcie.cfg_timeout, or reduced
622 * to speed boot if it is known that no devices need so much time.
623 */
624 static int cfg_timeout = 200;
625
cfg_retries(void)626 static int cfg_retries(void)
627 {
628 static int cfg_ticks = -1;
629
630 if (cfg_ticks < 0) {
631 u64 nS = cfg_timeout * 1000000;
632 const int ceiling = 0xffff;
633
634 cfg_ticks = nS / (gd->bus_clk >> 16);
635 if (cfg_ticks > ceiling)
636 cfg_ticks = ceiling;
637 }
638
639 return cfg_ticks;
640 }
641
642 /**
643 * @INTERNAL
644 * Enable/Disable PEMX_PEMON.pemon based on the direction.
645 *
646 * @param node node
647 * @param pcie_port PCIe port
648 * @param direction 0 to disable, 1 to enable
649 */
__cvmx_pcie_config_pemon(int node,int pcie_port,bool direction)650 static void __cvmx_pcie_config_pemon(int node, int pcie_port, bool direction)
651 {
652 cvmx_pemx_on_t pemon;
653
654 pemon.u64 = CVMX_READ_CSR(CVMX_PEMX_ON(pcie_port));
655 pemon.s.pemon = direction;
656 CVMX_WRITE_CSR(CVMX_PEMX_ON(pcie_port), pemon.u64);
657 pemon.u64 = CVMX_READ_CSR(CVMX_PEMX_ON(pcie_port));
658 }
659
660 /**
661 * @INTERNAL
662 * De-assert GSER_PHY.phy_reset for a given qlm
663 *
664 * @param node node
665 * @param qlm qlm for a given PCIe port
666 */
__cvmx_pcie_gser_phy_config(int node,int pcie_port,int qlm)667 static void __cvmx_pcie_gser_phy_config(int node, int pcie_port, int qlm)
668 {
669 cvmx_pemx_cfg_t pem_cfg;
670 cvmx_gserx_phy_ctl_t ctrl;
671 int has_8lanes = 0;
672 int is_gen3 = 0;
673
674 ctrl.u64 = CVMX_READ_CSR(CVMX_GSERX_PHY_CTL(qlm));
675
676 /* Assert the reset */
677 ctrl.s.phy_reset = 1;
678 CVMX_WRITE_CSR(CVMX_GSERX_PHY_CTL(qlm), ctrl.u64);
679 pem_cfg.u64 = CVMX_READ_CSR(CVMX_PEMX_CFG(pcie_port));
680 udelay(10);
681
682 has_8lanes = pem_cfg.cn78xx.lanes8;
683 is_gen3 = pem_cfg.cn78xx.md >= 2;
684
685 if (has_8lanes) {
686 ctrl.u64 = CVMX_READ_CSR(CVMX_GSERX_PHY_CTL(qlm + 1));
687 ctrl.s.phy_reset = 1;
688 CVMX_WRITE_CSR(CVMX_GSERX_PHY_CTL(qlm + 1), ctrl.u64);
689 ctrl.u64 = CVMX_READ_CSR(CVMX_GSERX_PHY_CTL(qlm + 1));
690 }
691 ctrl.u64 = CVMX_READ_CSR(CVMX_GSERX_PHY_CTL(qlm));
692 udelay(10);
693
694 /* Deassert the reset */
695 ctrl.s.phy_reset = 0;
696 CVMX_WRITE_CSR(CVMX_GSERX_PHY_CTL(qlm), ctrl.u64);
697 pem_cfg.u64 = CVMX_READ_CSR(CVMX_PEMX_CFG(pcie_port));
698 udelay(500);
699
700 if (has_8lanes) {
701 ctrl.u64 = CVMX_READ_CSR(CVMX_GSERX_PHY_CTL(qlm + 1));
702 ctrl.s.phy_reset = 0;
703 CVMX_WRITE_CSR(CVMX_GSERX_PHY_CTL(qlm + 1), ctrl.u64);
704 }
705 ctrl.u64 = CVMX_READ_CSR(CVMX_GSERX_PHY_CTL(qlm));
706 udelay(500);
707
708 /* Apply some erratas after PHY reset, only applies to PCIe GEN3 */
709 if (is_gen3) {
710 int i;
711 int high_qlm = has_8lanes ? qlm + 1 : qlm;
712
713 /* Apply workaround for Errata GSER-26150 */
714 if (OCTEON_IS_MODEL(OCTEON_CN73XX_PASS1_0)) {
715 for (i = qlm; i < high_qlm; i++) {
716 cvmx_gserx_glbl_pll_cfg_3_t pll_cfg_3;
717 cvmx_gserx_glbl_misc_config_1_t misc_config_1;
718 /* Update PLL parameters */
719 /*
720 * Step 1: Set
721 * GSER()_GLBL_PLL_CFG_3[PLL_VCTRL_SEL_LCVCO_VAL] = 0x2,
722 * and
723 * GSER()_GLBL_PLL_CFG_3[PCS_SDS_PLL_VCO_AMP] = 0
724 */
725 pll_cfg_3.u64 = CVMX_READ_CSR(CVMX_GSERX_GLBL_PLL_CFG_3(i));
726 pll_cfg_3.s.pcs_sds_pll_vco_amp = 0;
727 pll_cfg_3.s.pll_vctrl_sel_lcvco_val = 2;
728 CVMX_WRITE_CSR(CVMX_GSERX_GLBL_PLL_CFG_3(i), pll_cfg_3.u64);
729
730 /*
731 * Step 2: Set
732 * GSER()_GLBL_MISC_CONFIG_1[PCS_SDS_TRIM_CHP_REG] = 0x2.
733 */
734 misc_config_1.u64 = CVMX_READ_CSR(CVMX_GSERX_GLBL_MISC_CONFIG_1(i));
735 misc_config_1.s.pcs_sds_trim_chp_reg = 2;
736 CVMX_WRITE_CSR(CVMX_GSERX_GLBL_MISC_CONFIG_1(i), misc_config_1.u64);
737 }
738 }
739
740 /* Apply workaround for Errata GSER-25992 */
741 if (OCTEON_IS_MODEL(OCTEON_CN73XX_PASS1_X) ||
742 OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X)) {
743 for (i = qlm; i < high_qlm; i++)
744 cvmx_qlm_gser_errata_25992(node, i);
745 }
746 }
747 }
748
749 /* Get the PCIe LTSSM state for the given port
750 *
751 * @param node Node to query
752 * @param pcie_port PEM to query
753 *
754 * @return LTSSM state
755 */
__cvmx_pcie_rc_get_ltssm_state(int node,int pcie_port)756 static int __cvmx_pcie_rc_get_ltssm_state(int node, int pcie_port)
757 {
758 u64 debug;
759
760 if (OCTEON_IS_MODEL(OCTEON_CN73XX) && pcie_port == 0) {
761 CVMX_WRITE_CSR(CVMX_DTX_SPEM_SELX(0), 0);
762 CVMX_READ_CSR(CVMX_DTX_SPEM_SELX(0));
763 CVMX_WRITE_CSR(CVMX_DTX_SPEM_ENAX(0), 0xfffffffffull);
764 CVMX_READ_CSR(CVMX_DTX_SPEM_ENAX(0));
765
766 /* Read the value */
767 debug = CVMX_READ_CSR(CVMX_DTX_SPEM_DATX(0));
768
769 /* Disable the PEM from driving OCLA signals */
770 CVMX_WRITE_CSR(CVMX_DTX_SPEM_ENAX(0), 0);
771 CVMX_READ_CSR(CVMX_DTX_SPEM_ENAX(0));
772 } else {
773 /* LTSSM state is in debug select 0 */
774 CVMX_WRITE_CSR(CVMX_DTX_PEMX_SELX(0, pcie_port), 0);
775 CVMX_READ_CSR(CVMX_DTX_PEMX_SELX(0, pcie_port));
776 CVMX_WRITE_CSR(CVMX_DTX_PEMX_ENAX(0, pcie_port), 0xfffffffffull);
777 CVMX_READ_CSR(CVMX_DTX_PEMX_ENAX(0, pcie_port));
778
779 /* Read the value */
780 debug = CVMX_READ_CSR(CVMX_DTX_PEMX_DATX(0, pcie_port));
781
782 /* Disable the PEM from driving OCLA signals */
783 CVMX_WRITE_CSR(CVMX_DTX_PEMX_ENAX(0, pcie_port), 0);
784 CVMX_READ_CSR(CVMX_DTX_PEMX_ENAX(0, pcie_port));
785 }
786
787 /* DBGSEL = 0x0, bits[8:3] */
788 return cvmx_bit_extract(debug, 3, 6);
789 }
790
791 /**
792 * Get the PCIe LTSSM state for the given port
793 *
794 * @param node Node to query
795 * @param pcie_port PEM to query
796 *
797 * @return LTSSM state
798 */
cvmx_pcie_get_ltssm_string(int ltssm)799 static const char *cvmx_pcie_get_ltssm_string(int ltssm)
800 {
801 switch (ltssm) {
802 case 0x00:
803 return "DETECT_QUIET";
804 case 0x01:
805 return "DETECT_ACT";
806 case 0x02:
807 return "POLL_ACTIVE";
808 case 0x03:
809 return "POLL_COMPLIANCE";
810 case 0x04:
811 return "POLL_CONFIG";
812 case 0x05:
813 return "PRE_DETECT_QUIET";
814 case 0x06:
815 return "DETECT_WAIT";
816 case 0x07:
817 return "CFG_LINKWD_START";
818 case 0x08:
819 return "CFG_LINKWD_ACEPT";
820 case 0x09:
821 return "CFG_LANENUM_WAIT";
822 case 0x0A:
823 return "CFG_LANENUM_ACEPT";
824 case 0x0B:
825 return "CFG_COMPLETE";
826 case 0x0C:
827 return "CFG_IDLE";
828 case 0x0D:
829 return "RCVRY_LOCK";
830 case 0x0E:
831 return "RCVRY_SPEED";
832 case 0x0F:
833 return "RCVRY_RCVRCFG";
834 case 0x10:
835 return "RCVRY_IDLE";
836 case 0x11:
837 return "L0";
838 case 0x12:
839 return "L0S";
840 case 0x13:
841 return "L123_SEND_EIDLE";
842 case 0x14:
843 return "L1_IDLE";
844 case 0x15:
845 return "L2_IDLE";
846 case 0x16:
847 return "L2_WAKE";
848 case 0x17:
849 return "DISABLED_ENTRY";
850 case 0x18:
851 return "DISABLED_IDLE";
852 case 0x19:
853 return "DISABLED";
854 case 0x1A:
855 return "LPBK_ENTRY";
856 case 0x1B:
857 return "LPBK_ACTIVE";
858 case 0x1C:
859 return "LPBK_EXIT";
860 case 0x1D:
861 return "LPBK_EXIT_TIMEOUT";
862 case 0x1E:
863 return "HOT_RESET_ENTRY";
864 case 0x1F:
865 return "HOT_RESET";
866 case 0x20:
867 return "RCVRY_EQ0";
868 case 0x21:
869 return "RCVRY_EQ1";
870 case 0x22:
871 return "RCVRY_EQ2";
872 case 0x23:
873 return "RCVRY_EQ3";
874 default:
875 return "Unknown";
876 }
877 }
878
879 /**
880 * During PCIe link initialization we need to make config request to the attached
881 * device to verify its speed and width. These config access happen very early
882 * after the device is taken out of reset, so may fail for some amount of time.
883 * This function automatically retries these config accesses. The normal builtin
884 * hardware retry isn't enough for this very early access.
885 *
886 * @param node Note to read from
887 * @param pcie_port PCIe port to read from
888 * @param bus PCIe bus number
889 * @param dev PCIe device
890 * @param func PCIe function on the device
891 * @param reg Register to read
892 *
893 * @return Config register value, or all ones on failure
894 */
cvmx_pcie_config_read32_retry(int node,int pcie_port,int bus,int dev,int func,int reg)895 static uint32_t cvmx_pcie_config_read32_retry(int node, int pcie_port, int bus, int dev, int func,
896 int reg)
897 {
898 /*
899 * Read the PCI config register until we get a valid value. Some cards
900 * require time after link up to return data. Wait at most 3 seconds
901 */
902 u64 timeout = 300;
903 u32 val;
904
905 do {
906 /* Read PCI capability pointer */
907 val = __cvmx_pcie_config_read32(node, pcie_port, bus, dev, func, reg, 0);
908
909 /* Check the read succeeded */
910 if (val != 0xffffffff)
911 return val;
912 /* Failed, wait a little and try again */
913 mdelay(10);
914 } while (--timeout);
915
916 debug("N%d.PCIe%d: Config read failed, can't communicate with device\n",
917 node, pcie_port);
918
919 return -1;
920 }
921
922 /**
923 * @INTERNAL
924 * Initialize a host mode PCIe gen 2 link. This function takes a PCIe
925 * port from reset to a link up state. Software can then begin
926 * configuring the rest of the link.
927 *
928 * @param node node
929 * @param pcie_port PCIe port to initialize
930 *
931 * @return Zero on success
932 */
__cvmx_pcie_rc_initialize_link_gen2(int node,int pcie_port)933 static int __cvmx_pcie_rc_initialize_link_gen2(int node, int pcie_port)
934 {
935 u64 start_cycle;
936
937 cvmx_pemx_ctl_status_t pem_ctl_status;
938 cvmx_pciercx_cfg032_t pciercx_cfg032;
939 cvmx_pciercx_cfg448_t pciercx_cfg448;
940
941 if (OCTEON_IS_OCTEON3()) {
942 if (CVMX_WAIT_FOR_FIELD64_NODE(node, CVMX_PEMX_ON(pcie_port), cvmx_pemx_on_t,
943 pemoor, ==, 1, 100000)) {
944 printf("%d:PCIe: Port %d PEM not on, skipping\n", node, pcie_port);
945 return -1;
946 }
947 }
948
949 /* Bring up the link */
950 pem_ctl_status.u64 = CVMX_READ_CSR(CVMX_PEMX_CTL_STATUS(pcie_port));
951 pem_ctl_status.s.lnk_enb = 1;
952 CVMX_WRITE_CSR(CVMX_PEMX_CTL_STATUS(pcie_port), pem_ctl_status.u64);
953
954 /* Wait for the link to come up */
955 start_cycle = get_timer(0);
956 do {
957 if (get_timer(start_cycle) > 1000)
958 return -1;
959
960 udelay(1000);
961 pciercx_cfg032.u32 = CVMX_PCIE_CFGX_READ(pcie_port,
962 CVMX_PCIERCX_CFG032(pcie_port));
963 } while ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1));
964
965 /* Update the Replay Time Limit. Empirically, some PCIe devices take a
966 * little longer to respond than expected under load. As a workaround
967 * for this we configure the Replay Time Limit to the value expected
968 * for a 512 byte MPS instead of our actual 256 byte MPS. The numbers
969 * below are directly from the PCIe spec table 3-4
970 */
971 pciercx_cfg448.u32 = CVMX_PCIE_CFGX_READ(pcie_port,
972 CVMX_PCIERCX_CFG448(pcie_port));
973 switch (pciercx_cfg032.s.nlw) {
974 case 1: /* 1 lane */
975 pciercx_cfg448.s.rtl = 1677;
976 break;
977 case 2: /* 2 lanes */
978 pciercx_cfg448.s.rtl = 867;
979 break;
980 case 4: /* 4 lanes */
981 pciercx_cfg448.s.rtl = 462;
982 break;
983 case 8: /* 8 lanes */
984 pciercx_cfg448.s.rtl = 258;
985 break;
986 }
987 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG448(pcie_port),
988 pciercx_cfg448.u32);
989
990 return 0;
991 }
992
993 extern int octeon_pcie_get_qlm_from_fdt(int numa_node, int pcie_port);
994
__cvmx_pcie_check_pcie_port(int node,int pcie_port,enum cvmx_qlm_mode mode)995 static int __cvmx_pcie_check_pcie_port(int node, int pcie_port, enum cvmx_qlm_mode mode)
996 {
997 if (mode == CVMX_QLM_MODE_SRIO_1X4 || mode == CVMX_QLM_MODE_SRIO_2X2 ||
998 mode == CVMX_QLM_MODE_SRIO_4X1) {
999 printf("%d:PCIe: Port %d is SRIO, skipping.\n", node, pcie_port);
1000 return -1;
1001 } else if (mode == CVMX_QLM_MODE_SGMII) {
1002 printf("%d:PCIe: Port %d is SGMII, skipping.\n", node, pcie_port);
1003 return -1;
1004 } else if (mode == CVMX_QLM_MODE_XAUI || mode == CVMX_QLM_MODE_RXAUI) {
1005 printf("%d:PCIe: Port %d is XAUI, skipping.\n", node, pcie_port);
1006 return -1;
1007 } else if (mode == CVMX_QLM_MODE_ILK) {
1008 printf("%d:PCIe: Port %d is ILK, skipping.\n", node, pcie_port);
1009 return -1;
1010 } else if (mode != CVMX_QLM_MODE_PCIE &&
1011 mode != CVMX_QLM_MODE_PCIE_1X8 &&
1012 mode != CVMX_QLM_MODE_PCIE_1X2 &&
1013 mode != CVMX_QLM_MODE_PCIE_2X1 &&
1014 mode != CVMX_QLM_MODE_PCIE_1X1) {
1015 printf("%d:PCIe: Port %d is unknown, skipping.\n",
1016 node, pcie_port);
1017 return -1;
1018 }
1019 return 0;
1020 }
1021
__cvmx_pcie_check_qlm_mode(int node,int pcie_port,int qlm)1022 static int __cvmx_pcie_check_qlm_mode(int node, int pcie_port, int qlm)
1023 {
1024 enum cvmx_qlm_mode mode = CVMX_QLM_MODE_DISABLED;
1025
1026 if (qlm < 0)
1027 return -1;
1028
1029 /* Make sure this interface is PCIe */
1030 if (OCTEON_IS_MODEL(OCTEON_CN70XX)) {
1031 if (cvmx_qlm_get_dlm_mode(1, pcie_port) ==
1032 CVMX_QLM_MODE_DISABLED) {
1033 printf("PCIe: Port %d not in PCIe mode, skipping\n",
1034 pcie_port);
1035 return -1;
1036 }
1037 } else if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
1038 /*
1039 * Requires reading the MIO_QLMX_CFG register to figure
1040 * out the port type.
1041 */
1042 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
1043 qlm = 3 - (pcie_port * 2);
1044 } else if (OCTEON_IS_MODEL(OCTEON_CN61XX)) {
1045 cvmx_mio_qlmx_cfg_t qlm_cfg;
1046
1047 qlm_cfg.u64 = csr_rd(CVMX_MIO_QLMX_CFG(1));
1048 if (qlm_cfg.s.qlm_cfg == 1)
1049 qlm = 1;
1050 else
1051 qlm = pcie_port;
1052 } else if (OCTEON_IS_MODEL(OCTEON_CN66XX) ||
1053 OCTEON_IS_MODEL(OCTEON_CN63XX)) {
1054 qlm = pcie_port;
1055 }
1056
1057 /*
1058 * PCIe is allowed only in QLM1, 1 PCIe port in x2 or
1059 * 2 PCIe ports in x1
1060 */
1061 else if (OCTEON_IS_MODEL(OCTEON_CNF71XX))
1062 qlm = 1;
1063
1064 mode = cvmx_qlm_get_mode(qlm);
1065
1066 __cvmx_pcie_check_pcie_port(node, pcie_port, mode);
1067 }
1068 return 0;
1069 }
1070
__cvmx_pcie_sli_config(int node,int pcie_port)1071 static void __cvmx_pcie_sli_config(int node, int pcie_port)
1072 {
1073 cvmx_pemx_bar_ctl_t pemx_bar_ctl;
1074 cvmx_pemx_ctl_status_t pemx_ctl_status;
1075 cvmx_sli_ctl_portx_t sli_ctl_portx;
1076 cvmx_sli_mem_access_ctl_t sli_mem_access_ctl;
1077 cvmx_sli_mem_access_subidx_t mem_access_subid;
1078 cvmx_pemx_bar1_indexx_t bar1_index;
1079 int i;
1080
1081 /* Store merge control (SLI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
1082 sli_mem_access_ctl.u64 = CVMX_READ_CSR(CVMX_PEXP_SLI_MEM_ACCESS_CTL);
1083 sli_mem_access_ctl.s.max_word = 0; /* Allow 16 words to combine */
1084 sli_mem_access_ctl.s.timer = 127; /* Wait up to 127 cycles for more data */
1085 CVMX_WRITE_CSR(CVMX_PEXP_SLI_MEM_ACCESS_CTL, sli_mem_access_ctl.u64);
1086
1087 /* Setup Mem access SubDIDs */
1088 mem_access_subid.u64 = 0;
1089 mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
1090 mem_access_subid.s.nmerge = 0; /* Allow merging as it works on CN6XXX. */
1091 mem_access_subid.s.esr = _CVMX_PCIE_ES; /* Endian-swap for Reads. */
1092 mem_access_subid.s.esw = _CVMX_PCIE_ES; /* Endian-swap for Writes. */
1093 mem_access_subid.s.wtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
1094 mem_access_subid.s.rtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
1095 /* PCIe Address Bits <63:34>. */
1096 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
1097 mem_access_subid.cn68xx.ba = 0;
1098 else
1099 mem_access_subid.cn63xx.ba = 0;
1100
1101 /* Setup mem access 12-15 for port 0, 16-19 for port 1, supplying 36
1102 * bits of address space
1103 */
1104 for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
1105 CVMX_WRITE_CSR(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
1106 /* Set each SUBID to extend the addressable range */
1107 __cvmx_increment_ba(&mem_access_subid);
1108 }
1109
1110 if (OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) ||
1111 OCTEON_IS_MODEL(OCTEON_CN68XX) ||
1112 (OCTEON_IS_OCTEON3() && !OCTEON_IS_MODEL(OCTEON_CN70XX))) {
1113 /* Disable the peer to peer forwarding register. This must be
1114 * setup by the OS after it enumerates the bus and assigns
1115 * addresses to the PCIe busses
1116 */
1117 for (i = 0; i < 4; i++) {
1118 CVMX_WRITE_CSR(CVMX_PEMX_P2P_BARX_START(i, pcie_port), -1);
1119 CVMX_WRITE_CSR(CVMX_PEMX_P2P_BARX_END(i, pcie_port), -1);
1120 }
1121 }
1122
1123 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
1124 CVMX_WRITE_CSR(CVMX_PEMX_P2N_BAR0_START(pcie_port), 0);
1125
1126 /* Set Octeon's BAR2 to decode 0-2^41. Bar0 and Bar1 take precedence
1127 * where they overlap. It also overlaps with the device addresses, so
1128 * make sure the peer to peer forwarding is set right
1129 */
1130 CVMX_WRITE_CSR(CVMX_PEMX_P2N_BAR2_START(pcie_port), 0);
1131
1132 /* Setup BAR2 attributes */
1133 /* Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM]) */
1134 /* - PTLP_RO,CTLP_RO should normally be set (except for debug). */
1135 /* - WAIT_COM=0 will likely work for all applications. */
1136 /* Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM]) */
1137 pemx_bar_ctl.u64 = CVMX_READ_CSR(CVMX_PEMX_BAR_CTL(pcie_port));
1138 pemx_bar_ctl.s.bar1_siz = 3; /* 256MB BAR1 */
1139 pemx_bar_ctl.s.bar2_enb = 1;
1140 pemx_bar_ctl.s.bar2_esx = _CVMX_PCIE_ES;
1141 pemx_bar_ctl.s.bar2_cax = 0;
1142 CVMX_WRITE_CSR(CVMX_PEMX_BAR_CTL(pcie_port), pemx_bar_ctl.u64);
1143 sli_ctl_portx.u64 = CVMX_READ_CSR(CVMX_PEXP_SLI_CTL_PORTX(pcie_port));
1144 sli_ctl_portx.s.ptlp_ro = 1;
1145 sli_ctl_portx.s.ctlp_ro = 1;
1146 sli_ctl_portx.s.wait_com = 0;
1147 sli_ctl_portx.s.waitl_com = 0;
1148 CVMX_WRITE_CSR(CVMX_PEXP_SLI_CTL_PORTX(pcie_port), sli_ctl_portx.u64);
1149
1150 /* BAR1 follows BAR2 */
1151 CVMX_WRITE_CSR(CVMX_PEMX_P2N_BAR1_START(pcie_port),
1152 CVMX_PCIE_BAR1_RC_BASE);
1153
1154 bar1_index.u64 = 0;
1155 bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
1156 bar1_index.s.ca = 1; /* Not Cached */
1157 bar1_index.s.end_swp = _CVMX_PCIE_ES; /* Endian Swap mode */
1158 bar1_index.s.addr_v = 1; /* Valid entry */
1159
1160 for (i = 0; i < 16; i++) {
1161 CVMX_WRITE_CSR(CVMX_PEMX_BAR1_INDEXX(i, pcie_port),
1162 bar1_index.u64);
1163 /* 256MB / 16 >> 22 == 4 */
1164 bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
1165 }
1166
1167 /* Wait for 200ms */
1168 pemx_ctl_status.u64 = CVMX_READ_CSR(CVMX_PEMX_CTL_STATUS(pcie_port));
1169 pemx_ctl_status.cn63xx.cfg_rtry = cfg_retries();
1170 CVMX_WRITE_CSR(CVMX_PEMX_CTL_STATUS(pcie_port), pemx_ctl_status.u64);
1171
1172 /*
1173 * Here is the second part of the config retry changes. Wait for 700ms
1174 * after setting up the link before continuing. PCIe says the devices
1175 * may need up to 900ms to come up. 700ms plus 200ms from above gives
1176 * us a total of 900ms
1177 */
1178 if (OCTEON_IS_OCTEON2() || OCTEON_IS_MODEL(OCTEON_CN70XX))
1179 udelay(PCIE_DEVICE_READY_WAIT_DELAY_MICROSECONDS);
1180 }
1181
1182 /**
1183 * Initialize a PCIe gen 2 port for use in host(RC) mode. It doesn't enumerate
1184 * the bus.
1185 *
1186 * @param pcie_port PCIe port to initialize
1187 *
1188 * @return Zero on success
1189 */
__cvmx_pcie_rc_initialize_gen2(int pcie_port)1190 static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
1191 {
1192 cvmx_ciu_soft_prst_t ciu_soft_prst;
1193 cvmx_mio_rst_ctlx_t mio_rst_ctl;
1194 cvmx_pemx_bist_status_t pemx_bist_status;
1195 cvmx_pemx_bist_status2_t pemx_bist_status2;
1196 cvmx_pciercx_cfg032_t pciercx_cfg032;
1197 cvmx_pciercx_cfg515_t pciercx_cfg515;
1198 u64 ciu_soft_prst_reg, rst_ctl_reg;
1199 int ep_mode;
1200 int qlm = 0;
1201 int node = (pcie_port >> 4) & 0x3;
1202
1203 pcie_port &= 0x3;
1204
1205 if (pcie_port >= CVMX_PCIE_PORTS) {
1206 //debug("Invalid PCIe%d port\n", pcie_port);
1207 return -1;
1208 }
1209
1210 if (__cvmx_pcie_check_qlm_mode(node, pcie_port, qlm))
1211 return -1;
1212
1213 /* Make sure we aren't trying to setup a target mode interface in host
1214 * mode
1215 */
1216 if (OCTEON_IS_OCTEON3()) {
1217 ciu_soft_prst_reg = CVMX_RST_SOFT_PRSTX(pcie_port);
1218 rst_ctl_reg = CVMX_RST_CTLX(pcie_port);
1219 } else {
1220 ciu_soft_prst_reg = (pcie_port) ? CVMX_CIU_SOFT_PRST1 : CVMX_CIU_SOFT_PRST;
1221 rst_ctl_reg = CVMX_MIO_RST_CTLX(pcie_port);
1222 }
1223 mio_rst_ctl.u64 = CVMX_READ_CSR(rst_ctl_reg);
1224
1225 ep_mode = ((OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)) ?
1226 (mio_rst_ctl.s.prtmode != 1) :
1227 (!mio_rst_ctl.s.host_mode));
1228
1229 if (OCTEON_IS_MODEL(OCTEON_CN70XX) && pcie_port) {
1230 cvmx_pemx_cfg_t pemx_cfg;
1231
1232 pemx_cfg.u64 = csr_rd(CVMX_PEMX_CFG(0));
1233 if ((pemx_cfg.s.md & 3) == 2) {
1234 printf("PCIe: Port %d in 1x4 mode.\n", pcie_port);
1235 return -1;
1236 }
1237 }
1238
1239 if (ep_mode) {
1240 printf("%d:PCIe: Port %d in endpoint mode.\n", node, pcie_port);
1241 return -1;
1242 }
1243
1244 /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be
1245 * programmed
1246 */
1247 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0)) {
1248 if (pcie_port) {
1249 cvmx_ciu_qlm1_t ciu_qlm;
1250
1251 ciu_qlm.u64 = csr_rd(CVMX_CIU_QLM1);
1252 ciu_qlm.s.txbypass = 1;
1253 ciu_qlm.s.txdeemph = 5;
1254 ciu_qlm.s.txmargin = 0x17;
1255 csr_wr(CVMX_CIU_QLM1, ciu_qlm.u64);
1256 } else {
1257 cvmx_ciu_qlm0_t ciu_qlm;
1258
1259 ciu_qlm.u64 = csr_rd(CVMX_CIU_QLM0);
1260 ciu_qlm.s.txbypass = 1;
1261 ciu_qlm.s.txdeemph = 5;
1262 ciu_qlm.s.txmargin = 0x17;
1263 csr_wr(CVMX_CIU_QLM0, ciu_qlm.u64);
1264 }
1265 }
1266
1267 /* Bring the PCIe out of reset */
1268 ciu_soft_prst.u64 = CVMX_READ_CSR(ciu_soft_prst_reg);
1269 /* After a chip reset the PCIe will also be in reset. If it
1270 * isn't, most likely someone is trying to init it again
1271 * without a proper PCIe reset.
1272 */
1273 if (ciu_soft_prst.s.soft_prst == 0) {
1274 /* Reset the port */
1275 ciu_soft_prst.s.soft_prst = 1;
1276 CVMX_WRITE_CSR(ciu_soft_prst_reg, ciu_soft_prst.u64);
1277
1278 /* Read to make sure write happens */
1279 ciu_soft_prst.u64 = CVMX_READ_CSR(ciu_soft_prst_reg);
1280
1281 /* Keep PERST asserted for 2 ms */
1282 udelay(2000);
1283 }
1284
1285 /* Deassert PERST */
1286 ciu_soft_prst.u64 = CVMX_READ_CSR(ciu_soft_prst_reg);
1287 ciu_soft_prst.s.soft_prst = 0;
1288 CVMX_WRITE_CSR(ciu_soft_prst_reg, ciu_soft_prst.u64);
1289 ciu_soft_prst.u64 = CVMX_READ_CSR(ciu_soft_prst_reg);
1290
1291 /* Wait 1ms for PCIe reset to complete */
1292 udelay(1000);
1293
1294 /* Set MPLL multiplier as per Errata 20669. */
1295 if (OCTEON_IS_MODEL(OCTEON_CN70XX)) {
1296 int qlm = __cvmx_pcie_get_qlm(0, pcie_port);
1297 enum cvmx_qlm_mode mode;
1298 int old_mult;
1299 u64 meas_refclock = cvmx_qlm_measure_clock(qlm);
1300
1301 if (meas_refclock > 99000000 && meas_refclock < 101000000) {
1302 old_mult = 35;
1303 } else if (meas_refclock > 124000000 &&
1304 meas_refclock < 126000000) {
1305 old_mult = 56;
1306 } else if (meas_refclock > 156000000 &&
1307 meas_refclock < 156500000) {
1308 old_mult = 45;
1309 } else {
1310 printf("%s: Invalid reference clock for qlm %d\n",
1311 __func__, qlm);
1312 return -1;
1313 }
1314 mode = cvmx_qlm_get_mode(qlm);
1315 __cvmx_qlm_set_mult(qlm, 2500, old_mult);
1316 /* Adjust mplls for both dlms when configured as pcie 1x4 */
1317 if (mode == CVMX_QLM_MODE_PCIE && pcie_port == 0)
1318 __cvmx_qlm_set_mult(qlm + 1, 2500, old_mult);
1319 }
1320
1321 /*
1322 * Check and make sure PCIe came out of reset. If it doesn't the board
1323 * probably hasn't wired the clocks up and the interface should be
1324 * skipped
1325 */
1326 if (CVMX_WAIT_FOR_FIELD64_NODE(node, rst_ctl_reg, cvmx_mio_rst_ctlx_t,
1327 rst_done, ==, 1, 10000)) {
1328 printf("%d:PCIe: Port %d stuck in reset, skipping.\n", node, pcie_port);
1329 return -1;
1330 }
1331
1332 /* Check BIST status */
1333 pemx_bist_status.u64 = CVMX_READ_CSR(CVMX_PEMX_BIST_STATUS(pcie_port));
1334 if (pemx_bist_status.u64)
1335 printf("%d:PCIe: BIST FAILED for port %d (0x%016llx)\n", node, pcie_port,
1336 CAST64(pemx_bist_status.u64));
1337 pemx_bist_status2.u64 = CVMX_READ_CSR(CVMX_PEMX_BIST_STATUS2(pcie_port));
1338
1339 /*
1340 * Errata PCIE-14766 may cause the lower 6 bits to be randomly set on
1341 * CN63XXp1
1342 */
1343 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
1344 pemx_bist_status2.u64 &= ~0x3full;
1345
1346 if (pemx_bist_status2.u64) {
1347 printf("%d:PCIe: BIST2 FAILED for port %d (0x%016llx)\n",
1348 node, pcie_port, CAST64(pemx_bist_status2.u64));
1349 }
1350
1351 /* Initialize the config space CSRs */
1352 __cvmx_pcie_rc_initialize_config_space(node, pcie_port);
1353
1354 /* Enable gen2 speed selection */
1355 pciercx_cfg515.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG515(pcie_port));
1356 pciercx_cfg515.s.dsc = 1;
1357 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG515(pcie_port), pciercx_cfg515.u32);
1358
1359 /* Bring the link up */
1360 if (__cvmx_pcie_rc_initialize_link_gen2(node, pcie_port)) {
1361 /* Some gen1 devices don't handle the gen 2 training correctly.
1362 * Disable gen2 and try again with only gen1
1363 */
1364 cvmx_pciercx_cfg031_t pciercx_cfg031;
1365
1366 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG031(pcie_port));
1367 pciercx_cfg031.s.mls = 1;
1368 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG031(pcie_port), pciercx_cfg031.u32);
1369 if (__cvmx_pcie_rc_initialize_link_gen2(node, pcie_port)) {
1370 printf("PCIe: Link timeout on port %d, probably the slot is empty\n",
1371 pcie_port);
1372 return -1;
1373 }
1374 }
1375
1376 __cvmx_pcie_sli_config(node, pcie_port);
1377
1378 /* Display the link status */
1379 pciercx_cfg032.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
1380 printf("PCIe: Port %d link active, %d lanes, speed gen%d\n", pcie_port,
1381 pciercx_cfg032.s.nlw, pciercx_cfg032.s.ls);
1382
1383 pcie_link_initialized[node][pcie_port] = true;
1384 return 0;
1385 }
1386
1387 /**
1388 * @INTERNAL
1389 * Initialize a host mode PCIe gen 2 link. This function takes a PCIe
1390 * port from reset to a link up state. Software can then begin
1391 * configuring the rest of the link.
1392 *
1393 * @param node node
1394 * @param pcie_port PCIe port to initialize
1395 *
1396 * @return Zero on success
1397 */
__cvmx_pcie_rc_initialize_link_gen2_v3(int node,int pcie_port)1398 static int __cvmx_pcie_rc_initialize_link_gen2_v3(int node, int pcie_port)
1399 {
1400 u8 ltssm_history[LTSSM_HISTORY_SIZE];
1401 int ltssm_history_loc;
1402 cvmx_pemx_ctl_status_t pem_ctl_status;
1403 cvmx_pciercx_cfg006_t pciercx_cfg006;
1404 cvmx_pciercx_cfg031_t pciercx_cfg031;
1405 cvmx_pciercx_cfg032_t pciercx_cfg032;
1406 cvmx_pciercx_cfg068_t pciercx_cfg068;
1407 cvmx_pciercx_cfg448_t pciercx_cfg448;
1408 cvmx_pciercx_cfg515_t pciercx_cfg515;
1409 int max_gen, max_width;
1410 u64 hold_time;
1411 u64 bounce_allow_time;
1412 u64 timeout, good_time, current_time;
1413 int neg_gen, neg_width, bus, dev_gen, dev_width;
1414 unsigned int cap, cap_next;
1415 int ltssm_state, desired_gen;
1416 int desired_width;
1417 int i, need_speed_change, need_lane_change;
1418 int do_retry_speed = 0;
1419 int link_up = 0, is_loop_done = 0;
1420
1421 if (CVMX_WAIT_FOR_FIELD64_NODE(node, CVMX_PEMX_ON(pcie_port), cvmx_pemx_on_t, pemoor, ==, 1,
1422 100000)) {
1423 printf("N%d:PCIe: Port %d PEM not on, skipping\n", node, pcie_port);
1424 return -1;
1425 }
1426
1427 /* Record starting LTSSM state for debug */
1428 memset(ltssm_history, -1, sizeof(ltssm_history));
1429 ltssm_history[0] = __cvmx_pcie_rc_get_ltssm_state(node, pcie_port);
1430 ltssm_history_loc = 0;
1431
1432 pciercx_cfg031.u32 = CVMX_PCIE_CFGX_READ(pcie_port,
1433 CVMX_PCIERCX_CFG031(pcie_port));
1434 /* Max speed of PEM from config (1-3) */
1435 max_gen = pciercx_cfg031.s.mls;
1436 /* Max lane width of PEM (1-3) */
1437 max_width = pciercx_cfg031.s.mlw;
1438 #ifdef DEBUG_PCIE
1439 printf("N%d.PCIe%d: Link supports up to %d lanes, speed gen%d\n",
1440 node, pcie_port, max_width, max_gen);
1441 #endif
1442
1443 /* Bring up the link */
1444 #ifdef DEBUG_PCIE
1445 printf("N%d.PCIe%d: Enabling the link\n", node, pcie_port);
1446 #endif
1447 pem_ctl_status.u64 = CVMX_READ_CSR(CVMX_PEMX_CTL_STATUS(pcie_port));
1448 pem_ctl_status.s.lnk_enb = 1;
1449 CVMX_WRITE_CSR(CVMX_PEMX_CTL_STATUS(pcie_port), pem_ctl_status.u64);
1450
1451 /*
1452 * Configure SLI after enabling PCIe link. Is required for reading
1453 * PCIe card capabilities.
1454 */
1455 __cvmx_pcie_sli_config(node, pcie_port);
1456
1457 /*
1458 * After the link is enabled no prints until link up or error,
1459 * Otherwise will miss link state captures
1460 */
1461
1462 retry_speed:
1463 /* Clear RC Correctable Error Status Register */
1464 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG068(pcie_port), -1);
1465
1466 /* Wait for the link to come up and link training to be complete */
1467 #ifdef DEBUG_PCIE
1468 printf("N%d.PCIe%d: Waiting for link\n", node, pcie_port);
1469 #endif
1470
1471 /* Timeout of 2 secs */
1472 timeout = get_timer(0) + 2000;
1473
1474 /* Records when the link first went good */
1475 good_time = 0;
1476
1477 do {
1478 pciercx_cfg032.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
1479 /*
1480 * Errata PEM-31375 PEM RSL access to PCLK registers can
1481 * timeout during speed change. Check for temporary hardware
1482 * timeout, and rety if happens
1483 */
1484 if (pciercx_cfg032.u32 == 0xffffffff)
1485 continue;
1486
1487 /* Record LTSSM state for debug */
1488 ltssm_state = __cvmx_pcie_rc_get_ltssm_state(node, pcie_port);
1489
1490 if (ltssm_history[ltssm_history_loc] != ltssm_state) {
1491 ltssm_history_loc = (ltssm_history_loc + 1) & (LTSSM_HISTORY_SIZE - 1);
1492 ltssm_history[ltssm_history_loc] = ltssm_state;
1493 }
1494
1495 /* Check if the link is up */
1496 // current_time = cvmx_get_cycle();
1497 current_time = get_timer(0);
1498 link_up = (pciercx_cfg032.s.dlla && !pciercx_cfg032.s.lt);
1499
1500 if (link_up) {
1501 /* Is this the first link up? */
1502 if (!good_time) {
1503 /* Mark the time when the link transitioned to good */
1504 good_time = current_time;
1505 } else {
1506 /* Check for a link error */
1507 pciercx_cfg068.u32 = CVMX_PCIE_CFGX_READ(
1508 pcie_port, CVMX_PCIERCX_CFG068(pcie_port));
1509 if (pciercx_cfg068.s.res) {
1510 /*
1511 * Ignore errors before we've been
1512 * stable for bounce_allow_time
1513 */
1514 if (good_time + bounce_allow_time <=
1515 current_time) {
1516 #ifdef DEBUG_PCIE
1517 printf("N%d.PCIe%d: Link errors after link up\n",
1518 node, pcie_port);
1519 #endif
1520 /* Link error, signal a retry */
1521 return 1;
1522 }
1523
1524 /*
1525 * Clear RC Correctable Error
1526 * Status Register
1527 */
1528 CVMX_PCIE_CFGX_WRITE(pcie_port,
1529 CVMX_PCIERCX_CFG068(pcie_port),
1530 -1);
1531 #ifdef DEBUG_PCIE
1532 printf("N%d.PCIe%d: Ignored error during settling time\n",
1533 node, pcie_port);
1534 #endif
1535 }
1536 }
1537 } else if (good_time) {
1538 if (good_time + bounce_allow_time <= current_time) {
1539 /*
1540 * We allow bounces for bounce_allow_time after
1541 * the link is good. Once this time passes any
1542 * bounce requires a retry
1543 */
1544 #ifdef DEBUG_PCIE
1545 printf("N%d.PCIe%d: Link bounce detected\n",
1546 node, pcie_port);
1547 #endif
1548 return 1; /* Link bounce, signal a retry */
1549 }
1550
1551 #ifdef DEBUG_PCIE
1552 printf("N%d.PCIe%d: Ignored bounce during settling time\n",
1553 node, pcie_port);
1554 #endif
1555 }
1556
1557 /* Determine if we've hit the timeout */
1558 is_loop_done = (current_time >= timeout);
1559
1560 /*
1561 * Determine if we've had a good link for the required hold
1562 * time
1563 */
1564 is_loop_done |= link_up && (good_time + hold_time <=
1565 current_time);
1566 } while (!is_loop_done);
1567
1568 /* Trace the LTSSM state */
1569 #ifdef DEBUG_PCIE
1570 printf("N%d.PCIe%d: LTSSM History\n", node, pcie_port);
1571 #endif
1572 for (i = 0; i < LTSSM_HISTORY_SIZE; i++) {
1573 ltssm_history_loc = (ltssm_history_loc + 1) & (LTSSM_HISTORY_SIZE - 1);
1574 #ifdef DEBUG_PCIE
1575 if (ltssm_history[ltssm_history_loc] != 0xff)
1576 printf("N%d.PCIe%d: %s\n", node, pcie_port,
1577 cvmx_pcie_get_ltssm_string(ltssm_history[ltssm_history_loc]));
1578 #endif
1579 }
1580
1581 if (!link_up) {
1582 ltssm_state = __cvmx_pcie_rc_get_ltssm_state(node, pcie_port);
1583 #ifdef DEBUG_PCIE
1584 printf("N%d.PCIe%d: Link down, Data link layer %s(DLLA=%d), Link training %s(LT=%d), LTSSM %s\n",
1585 node, pcie_port, pciercx_cfg032.s.dlla ? "active" : "down",
1586 pciercx_cfg032.s.dlla, pciercx_cfg032.s.lt ? "active" : "complete",
1587 pciercx_cfg032.s.lt, cvmx_pcie_get_ltssm_string(ltssm_state));
1588 #endif
1589 return 1; /* Link down, signal a retry */
1590 }
1591
1592 /* Report the negotiated link speed and width */
1593 neg_gen = pciercx_cfg032.s.ls; /* Current speed of PEM (1-3) */
1594 neg_width = pciercx_cfg032.s.nlw; /* Current lane width of PEM (1-8) */
1595 #ifdef DEBUG_PCIE
1596 printf("N%d.PCIe%d: Link negotiated %d lanes, speed gen%d\n", node, pcie_port, neg_width,
1597 neg_gen);
1598 #endif
1599 /* Determine PCIe bus number the directly attached device uses */
1600 pciercx_cfg006.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG006(pcie_port));
1601 bus = pciercx_cfg006.s.sbnum;
1602
1603 /* The SLI has to be initialized so we can read the downstream devices */
1604 dev_gen = 1; /* Device max speed (1-3) */
1605 dev_width = 1; /* Device max lane width (1-16) */
1606 #ifdef DEBUG_PCIE
1607 printf("N%d.PCIe%d: Reading Bus %d device max speed and width\n", node, pcie_port, bus);
1608 #endif
1609
1610 /*
1611 * Here is the second part of the config retry changes. Wait for 700ms
1612 * after setting up the link before continuing. PCIe says the devices
1613 * may need up to 900ms to come up. 700ms plus 200ms from above gives
1614 * us a total of 900ms
1615 */
1616 udelay(PCIE_DEVICE_READY_WAIT_DELAY_MICROSECONDS);
1617
1618 /* Read PCI capability pointer at offset 0x34 of target */
1619 cap = cvmx_pcie_config_read32_retry(node, pcie_port, bus, 0, 0, 0x34);
1620
1621 /* Check if we were able to read capabilities pointer */
1622 if (cap == 0xffffffff)
1623 return 1; /* Signal retry needed */
1624
1625 /* Read device max speed and width */
1626 cap_next = cap & 0xff;
1627 while (cap_next) {
1628 cap = cvmx_pcie_config_read32_retry(node, pcie_port, bus,
1629 0, 0, cap_next);
1630 if (cap == 0xffffffff)
1631 return 1; /* Signal retry needed */
1632
1633 /* Is this a PCIe capability (0x10)? */
1634 if ((cap & 0xff) == 0x10) {
1635 #ifdef DEBUG_PCIE
1636 printf("N%d.PCIe%d: Found PCIe capability at offset 0x%x\n",
1637 node, pcie_port, cap_next);
1638 #endif
1639 /* Offset 0xc contains the max link info */
1640 cap = cvmx_pcie_config_read32_retry(node, pcie_port, bus, 0, 0,
1641 cap_next + 0xc);
1642 if (cap == 0xffffffff)
1643 return 1; /* Signal retry needed */
1644 dev_gen = cap & 0xf; /* Max speed of PEM from config (1-3) */
1645 dev_width = (cap >> 4) & 0x3f; /* Max lane width of PEM (1-16) */
1646 #ifdef DEBUG_PCIE
1647 printf("N%d.PCIe%d: Device supports %d lanes, speed gen%d\n", node,
1648 pcie_port, dev_width, dev_gen);
1649 #endif
1650 break;
1651 }
1652 /* Move to next capability */
1653 cap_next = (cap >> 8) & 0xff;
1654 }
1655
1656 /*
1657 * Desired link speed and width is either limited by the device or our
1658 * PEM configuration. Choose the most restrictive limit
1659 */
1660 desired_gen = (dev_gen < max_gen) ? dev_gen : max_gen;
1661 desired_width = (dev_width < max_width) ? dev_width : max_width;
1662
1663 /*
1664 * We need a change if we don't match the desired speed or width.
1665 * Note that we allow better than expected in case the device lied
1666 * about its capabilities
1667 */
1668 need_speed_change = (neg_gen < desired_gen);
1669 need_lane_change = (neg_width < desired_width);
1670
1671 if (need_lane_change) {
1672 /* We didn't get the maximum number of lanes */
1673 #ifdef DEBUG_PCIE
1674 printf("N%d.PCIe%d: Link width (%d) less that supported (%d)\n",
1675 node, pcie_port, neg_width, desired_width);
1676 #endif
1677 return 2; /* Link wrong width, signal a retry */
1678 } else if (need_speed_change) {
1679 if (do_retry_speed) {
1680 #ifdef DEBUG_PCIE
1681 printf("N%d.PCIe%d: Link speed (gen%d) less that supported (gen%d)\n", node,
1682 pcie_port, neg_gen, desired_gen);
1683 #endif
1684 return 1; /* Link at width, but speed low. Request a retry */
1685 }
1686
1687 /* We didn't get the maximum speed. Request a speed change */
1688 #ifdef DEBUG_PCIE
1689 printf("N%d.PCIe%d: Link speed (gen%d) less that supported (gen%d), requesting a speed change\n",
1690 node, pcie_port, neg_gen, desired_gen);
1691 #endif
1692 pciercx_cfg515.u32 =
1693 CVMX_PCIE_CFGX_READ(pcie_port,
1694 CVMX_PCIERCX_CFG515(pcie_port));
1695 pciercx_cfg515.s.dsc = 1;
1696 CVMX_PCIE_CFGX_WRITE(pcie_port,
1697 CVMX_PCIERCX_CFG515(pcie_port),
1698 pciercx_cfg515.u32);
1699 mdelay(100);
1700 do_retry_speed = true;
1701 goto retry_speed;
1702 } else {
1703 #ifdef DEBUG_PCIE
1704 printf("N%d.PCIe%d: Link at best speed and width\n",
1705 node, pcie_port);
1706 #endif
1707 /* For gen3 links check if we are getting errors over the link */
1708 if (neg_gen == 3) {
1709 /* Read RC Correctable Error Status Register */
1710 pciercx_cfg068.u32 =
1711 CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG068(pcie_port));
1712 if (pciercx_cfg068.s.res) {
1713 #ifdef DEBUG_PCIE
1714 printf("N%d.PCIe%d: Link reporting error status\n", node,
1715 pcie_port);
1716 #endif
1717 return 1; /* Getting receiver errors, request a retry */
1718 }
1719 }
1720 return 0; /* Link at correct speed and width */
1721 }
1722
1723 /* Update the Replay Time Limit. Empirically, some PCIe devices take a
1724 * little longer to respond than expected under load. As a workaround
1725 * for this we configure the Replay Time Limit to the value expected
1726 * for a 512 byte MPS instead of our actual 256 byte MPS. The numbers
1727 * below are directly from the PCIe spec table 3-4
1728 */
1729 pciercx_cfg448.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
1730 switch (pciercx_cfg032.s.nlw) {
1731 case 1: /* 1 lane */
1732 pciercx_cfg448.s.rtl = 1677;
1733 break;
1734 case 2: /* 2 lanes */
1735 pciercx_cfg448.s.rtl = 867;
1736 break;
1737 case 4: /* 4 lanes */
1738 pciercx_cfg448.s.rtl = 462;
1739 break;
1740 case 8: /* 8 lanes */
1741 pciercx_cfg448.s.rtl = 258;
1742 break;
1743 }
1744 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), pciercx_cfg448.u32);
1745
1746 return 0;
1747 }
1748
__cvmx_pcie_rc_initialize_gen2_v3(int pcie_port)1749 static int __cvmx_pcie_rc_initialize_gen2_v3(int pcie_port)
1750 {
1751 cvmx_rst_ctlx_t rst_ctl;
1752 cvmx_rst_soft_prstx_t rst_soft_prst;
1753 cvmx_pciercx_cfg031_t pciercx_cfg031;
1754 cvmx_pciercx_cfg032_t pciercx_cfg032;
1755 cvmx_pciercx_cfg038_t pciercx_cfg038;
1756 cvmx_pciercx_cfg040_t pciercx_cfg040;
1757 cvmx_pciercx_cfg515_t pciercx_cfg515;
1758 cvmx_pciercx_cfg548_t pciercx_cfg548;
1759 cvmx_pemx_bist_status_t pemx_bist_status;
1760 u64 rst_soft_prst_reg;
1761 int qlm;
1762 int node = (pcie_port >> 4) & 0x3;
1763 bool requires_pem_reset = 0;
1764 enum cvmx_qlm_mode mode = CVMX_QLM_MODE_DISABLED;
1765 int retry_count = 0;
1766 int result = 0;
1767
1768 pcie_port &= 0x3;
1769
1770 /* Assume link down until proven up */
1771 pcie_link_initialized[node][pcie_port] = false;
1772
1773 /* Attempt link initialization up to 3 times */
1774 while (retry_count <= MAX_RETRIES) {
1775 #ifdef DEBUG_PCIE
1776 if (retry_count)
1777 printf("N%d:PCIE%d: Starting link retry %d\n", node, pcie_port,
1778 retry_count);
1779 #endif
1780 if (pcie_port >= CVMX_PCIE_PORTS) {
1781 #ifdef DEBUG_PCIE
1782 printf("Invalid PCIe%d port\n", pcie_port);
1783 #endif
1784 return -1;
1785 }
1786
1787 qlm = __cvmx_pcie_get_qlm(node, pcie_port);
1788
1789 if (qlm < 0)
1790 return -1;
1791
1792 mode = cvmx_qlm_get_mode(qlm);
1793 if (__cvmx_pcie_check_pcie_port(node, pcie_port, mode))
1794 return -1;
1795
1796 rst_soft_prst_reg = CVMX_RST_SOFT_PRSTX(pcie_port);
1797 rst_ctl.u64 = CVMX_READ_CSR(CVMX_RST_CTLX(pcie_port));
1798
1799 if (OCTEON_IS_MODEL(OCTEON_CN78XX)) {
1800 CVMX_WRITE_CSR(CVMX_DTX_PEMX_SELX(0, pcie_port), 0x17);
1801 CVMX_WRITE_CSR(CVMX_DTX_PEMX_SELX(1, pcie_port), 0);
1802 }
1803
1804 if (!rst_ctl.s.host_mode) {
1805 printf("N%d:PCIE: Port %d in endpoint mode.\n",
1806 node, pcie_port);
1807 return -1;
1808 }
1809
1810 /* Bring the PCIe out of reset */
1811 rst_soft_prst.u64 = CVMX_READ_CSR(rst_soft_prst_reg);
1812
1813 /*
1814 * After a chip reset the PCIe will also be in reset. If it
1815 * isn't, most likely someone is trying to init it again
1816 * without a proper PCIe reset.
1817 */
1818 if (rst_soft_prst.s.soft_prst == 0) {
1819 /* Disable the MAC controller before resetting */
1820 __cvmx_pcie_config_pemon(node, pcie_port, 0);
1821
1822 /* Reset the port */
1823 rst_soft_prst.s.soft_prst = 1;
1824 CVMX_WRITE_CSR(rst_soft_prst_reg, rst_soft_prst.u64);
1825
1826 /* Read to make sure write happens */
1827 rst_soft_prst.u64 = CVMX_READ_CSR(rst_soft_prst_reg);
1828
1829 /* Keep PERST asserted for 2 ms */
1830 udelay(2000);
1831
1832 /* Reset GSER_PHY to put in a clean state */
1833 __cvmx_pcie_gser_phy_config(node, pcie_port, qlm);
1834 requires_pem_reset = 1;
1835
1836 /* Enable MAC controller before taking pcie out of reset */
1837 __cvmx_pcie_config_pemon(node, pcie_port, 1);
1838 }
1839
1840 /* Deassert PERST */
1841 rst_soft_prst.u64 = CVMX_READ_CSR(rst_soft_prst_reg);
1842 rst_soft_prst.s.soft_prst = 0;
1843 CVMX_WRITE_CSR(rst_soft_prst_reg, rst_soft_prst.u64);
1844 rst_soft_prst.u64 = CVMX_READ_CSR(rst_soft_prst_reg);
1845
1846 /* Check if PLLs are locked after GSER_PHY reset. */
1847 if (requires_pem_reset) {
1848 cvmx_pemx_cfg_t pemx_cfg;
1849
1850 pemx_cfg.u64 = csr_rd(CVMX_PEMX_CFG(pcie_port));
1851 if (CVMX_WAIT_FOR_FIELD64(CVMX_GSERX_QLM_STAT(qlm), cvmx_gserx_qlm_stat_t,
1852 rst_rdy, ==, 1, 10000)) {
1853 printf("QLM%d: Timeout waiting for GSERX_QLM_STAT[rst_rdy]\n", qlm);
1854 return -1;
1855 }
1856 if (pemx_cfg.cn78xx.lanes8 &&
1857 (CVMX_WAIT_FOR_FIELD64(CVMX_GSERX_QLM_STAT(qlm + 1),
1858 cvmx_gserx_qlm_stat_t, rst_rdy, ==, 1, 10000))) {
1859 printf("QLM%d: Timeout waiting for GSERX_QLM_STAT[rst_rdy]\n",
1860 qlm + 1);
1861 return -1;
1862 }
1863 }
1864
1865 /* Wait 1ms for PCIe reset to complete */
1866 udelay(1000);
1867
1868 /*
1869 * Check and make sure PCIe came out of reset. If it doesn't
1870 * the board probably hasn't wired the clocks up and the
1871 * interface should be skipped
1872 */
1873 if (CVMX_WAIT_FOR_FIELD64_NODE(node, CVMX_RST_CTLX(pcie_port),
1874 cvmx_rst_ctlx_t,
1875 rst_done, ==, 1, 10000)) {
1876 printf("N%d:PCIE: Port %d stuck in reset, skipping.\n", node, pcie_port);
1877 return -1;
1878 }
1879
1880 /* Check BIST status */
1881 pemx_bist_status.u64 = CVMX_READ_CSR(CVMX_PEMX_BIST_STATUS(pcie_port));
1882 if (pemx_bist_status.u64)
1883 printf("N%d:PCIE: BIST FAILED for port %d (0x%016llx)\n", node, pcie_port,
1884 CAST64(pemx_bist_status.u64));
1885
1886 /* Initialize the config space CSRs */
1887 #ifdef DEBUG_PCIE
1888 printf("N%d:PCIE%d Initialize Config Space\n", node, pcie_port);
1889 #endif
1890 __cvmx_pcie_rc_initialize_config_space(node, pcie_port);
1891
1892 /* Enable gen2 speed selection */
1893 pciercx_cfg515.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG515(pcie_port));
1894 pciercx_cfg515.s.dsc = 1;
1895 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG515(pcie_port), pciercx_cfg515.u32);
1896
1897 /* Do the link retries on the PCIe interface */
1898 if (retry_count == MAX_RETRIES) {
1899 /*
1900 * This has to be done AFTER the QLM/PHY interface
1901 * initialized
1902 */
1903 pciercx_cfg031.u32 =
1904 CVMX_PCIE_CFGX_READ(pcie_port,
1905 CVMX_PCIERCX_CFG031(pcie_port));
1906 /*
1907 * Drop speed to gen2 if link bouncing
1908 * Result = -1 PEM in reset
1909 * Result = 0: link speed and width ok no retry needed
1910 * Result = 1: link errors or speed change needed
1911 * Result = 2: lane width error
1912 */
1913 if (pciercx_cfg031.s.mls == 3 && result != 2) {
1914 #ifdef DEBUG_PCIE
1915 printf("N%d:PCIE%d: Dropping speed to gen2\n", node, pcie_port);
1916 #endif
1917 pciercx_cfg031.s.mls = 2;
1918 CVMX_PCIE_CFGX_WRITE(pcie_port,
1919 CVMX_PCIERCX_CFG031(pcie_port),
1920 pciercx_cfg031.u32);
1921
1922 /* Set the target link speed */
1923 pciercx_cfg040.u32 = CVMX_PCIE_CFGX_READ(
1924 pcie_port, CVMX_PCIERCX_CFG040(pcie_port));
1925 pciercx_cfg040.s.tls = 2;
1926 CVMX_PCIE_CFGX_WRITE(pcie_port,
1927 CVMX_PCIERCX_CFG040(pcie_port),
1928 pciercx_cfg040.u32);
1929 }
1930 }
1931
1932 /* Bring the link up */
1933 result = __cvmx_pcie_rc_initialize_link_gen2_v3(node, pcie_port);
1934 if (result == 0) {
1935 #ifdef DEBUG_PCIE
1936 printf("N%d:PCIE%d: Link does not need a retry\n", node, pcie_port);
1937 #endif
1938 break;
1939 } else if (result > 0) {
1940 if (retry_count >= MAX_RETRIES) {
1941 int link_up;
1942 #ifdef DEBUG_PCIE
1943 printf("N%d:PCIE%d: Link requested a retry, but hit the max retries\n",
1944 node, pcie_port);
1945 #endif
1946 /* If the link is down, report failure */
1947 pciercx_cfg032.u32 = CVMX_PCIE_CFGX_READ(
1948 pcie_port,
1949 CVMX_PCIERCX_CFG032(pcie_port));
1950 link_up = (pciercx_cfg032.s.dlla && !pciercx_cfg032.s.lt);
1951 if (!link_up)
1952 result = -1;
1953 }
1954 #ifdef DEBUG_PCIE
1955 else
1956 printf("N%d.PCIE%d: Link requested a retry\n", node, pcie_port);
1957 #endif
1958 }
1959 if (result < 0) {
1960 int ltssm_state = __cvmx_pcie_rc_get_ltssm_state(node, pcie_port);
1961
1962 printf("N%d:PCIE%d: Link timeout, probably the slot is empty (LTSSM %s)\n",
1963 node, pcie_port, cvmx_pcie_get_ltssm_string(ltssm_state));
1964 return -1;
1965 }
1966 retry_count++;
1967 }
1968
1969 pciercx_cfg032.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
1970 /*
1971 * Errata PEM-28816: Link retrain initiated at GEN1 can cause PCIE
1972 * link to hang. For Gen1 links we must disable equalization
1973 */
1974 if (pciercx_cfg032.s.ls == 1) {
1975 #ifdef DEBUG_PCIE
1976 printf("N%d:PCIE%d: Disabling equalization for GEN1 Link\n", node, pcie_port);
1977 #endif
1978 pciercx_cfg548.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG548(pcie_port));
1979 pciercx_cfg548.s.ed = 1;
1980 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG548(pcie_port), pciercx_cfg548.u32);
1981 }
1982
1983 /* Errata PCIE-29440: Atomic operations to work properly */
1984 pciercx_cfg038.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG038(pcie_port));
1985 pciercx_cfg038.s.atom_op_eb = 0;
1986 pciercx_cfg038.s.atom_op = 1;
1987 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG038(pcie_port), pciercx_cfg038.u32);
1988
1989 /* Errata PCIE-29566 PEM Link Hangs after going into L1 */
1990 pciercx_cfg548.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG548(pcie_port));
1991 pciercx_cfg548.s.grizdnc = 0;
1992 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIERCX_CFG548(pcie_port), pciercx_cfg548.u32);
1993
1994 if (result < 0)
1995 return result;
1996
1997 /* Display the link status */
1998 pciercx_cfg032.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
1999 printf("N%d:PCIe: Port %d link active, %d lanes, speed gen%d\n", node, pcie_port,
2000 pciercx_cfg032.s.nlw, pciercx_cfg032.s.ls);
2001
2002 pcie_link_initialized[node][pcie_port] = true;
2003 return 0;
2004 }
2005
2006 /**
2007 * Initialize a PCIe port for use in host(RC) mode. It doesn't enumerate the bus.
2008 *
2009 * @param pcie_port PCIe port to initialize for a node
2010 *
2011 * @return Zero on success
2012 */
cvmx_pcie_rc_initialize(int pcie_port)2013 int cvmx_pcie_rc_initialize(int pcie_port)
2014 {
2015 int result;
2016
2017 if (OCTEON_IS_OCTEON2() || OCTEON_IS_MODEL(OCTEON_CN70XX))
2018 result = __cvmx_pcie_rc_initialize_gen2(pcie_port);
2019 else
2020 result = __cvmx_pcie_rc_initialize_gen2_v3(pcie_port);
2021
2022 if (result == 0)
2023 cvmx_error_enable_group(CVMX_ERROR_GROUP_PCI, pcie_port);
2024 return result;
2025 }
2026
2027 /**
2028 * Shutdown a PCIe port and put it in reset
2029 *
2030 * @param pcie_port PCIe port to shutdown for a node
2031 *
2032 * @return Zero on success
2033 */
cvmx_pcie_rc_shutdown(int pcie_port)2034 int cvmx_pcie_rc_shutdown(int pcie_port)
2035 {
2036 u64 ciu_soft_prst_reg;
2037 cvmx_ciu_soft_prst_t ciu_soft_prst;
2038 int node;
2039
2040 /* Shutdown only if PEM is in RC mode */
2041 if (!cvmx_pcie_is_host_mode(pcie_port))
2042 return -1;
2043
2044 node = (pcie_port >> 4) & 0x3;
2045 pcie_port &= 0x3;
2046 cvmx_error_disable_group(CVMX_ERROR_GROUP_PCI, pcie_port);
2047 /* Wait for all pending operations to complete */
2048 if (CVMX_WAIT_FOR_FIELD64_NODE(node, CVMX_PEMX_CPL_LUT_VALID(pcie_port),
2049 cvmx_pemx_cpl_lut_valid_t, tag, ==,
2050 0, 2000))
2051 debug("PCIe: Port %d shutdown timeout\n", pcie_port);
2052
2053 if (OCTEON_IS_OCTEON3()) {
2054 ciu_soft_prst_reg = CVMX_RST_SOFT_PRSTX(pcie_port);
2055 } else {
2056 ciu_soft_prst_reg = (pcie_port) ? CVMX_CIU_SOFT_PRST1 :
2057 CVMX_CIU_SOFT_PRST;
2058 }
2059
2060 /* Force reset */
2061 ciu_soft_prst.u64 = CVMX_READ_CSR(ciu_soft_prst_reg);
2062 ciu_soft_prst.s.soft_prst = 1;
2063 CVMX_WRITE_CSR(ciu_soft_prst_reg, ciu_soft_prst.u64);
2064
2065 return 0;
2066 }
2067
2068 /**
2069 * @INTERNAL
2070 * Build a PCIe config space request address for a device
2071 *
2072 * @param node node
2073 * @param port PCIe port (relative to the node) to access
2074 * @param bus Sub bus
2075 * @param dev Device ID
2076 * @param fn Device sub function
2077 * @param reg Register to access
2078 *
2079 * @return 64bit Octeon IO address
2080 */
__cvmx_pcie_build_config_addr(int node,int port,int bus,int dev,int fn,int reg)2081 static uint64_t __cvmx_pcie_build_config_addr(int node, int port, int bus, int dev, int fn, int reg)
2082 {
2083 cvmx_pcie_address_t pcie_addr;
2084 cvmx_pciercx_cfg006_t pciercx_cfg006;
2085
2086 pciercx_cfg006.u32 = cvmx_pcie_cfgx_read_node(node, port,
2087 CVMX_PCIERCX_CFG006(port));
2088 if (bus <= pciercx_cfg006.s.pbnum && dev != 0)
2089 return 0;
2090
2091 pcie_addr.u64 = 0;
2092 pcie_addr.config.upper = 2;
2093 pcie_addr.config.io = 1;
2094 pcie_addr.config.did = 3;
2095 pcie_addr.config.subdid = 1;
2096 pcie_addr.config.node = node;
2097 pcie_addr.config.es = _CVMX_PCIE_ES;
2098 pcie_addr.config.port = port;
2099 /* Always use config type 0 */
2100 if (pciercx_cfg006.s.pbnum == 0)
2101 pcie_addr.config.ty = (bus > pciercx_cfg006.s.pbnum + 1);
2102 else
2103 pcie_addr.config.ty = (bus > pciercx_cfg006.s.pbnum);
2104 pcie_addr.config.bus = bus;
2105 pcie_addr.config.dev = dev;
2106 pcie_addr.config.func = fn;
2107 pcie_addr.config.reg = reg;
2108 return pcie_addr.u64;
2109 }
2110
2111 /**
2112 * Read 8bits from a Device's config space
2113 *
2114 * @param pcie_port PCIe port the device is on
2115 * @param bus Sub bus
2116 * @param dev Device ID
2117 * @param fn Device sub function
2118 * @param reg Register to access
2119 *
2120 * @return Result of the read
2121 */
cvmx_pcie_config_read8(int pcie_port,int bus,int dev,int fn,int reg)2122 uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev, int fn, int reg)
2123 {
2124 u64 address;
2125 int node = (pcie_port >> 4) & 0x3;
2126
2127 pcie_port &= 0x3;
2128 address = __cvmx_pcie_build_config_addr(node, pcie_port, bus, dev, fn, reg);
2129 if (address)
2130 return cvmx_read64_uint8(address);
2131 else
2132 return 0xff;
2133 }
2134
2135 /**
2136 * Read 16bits from a Device's config space
2137 *
2138 * @param pcie_port PCIe port the device is on
2139 * @param bus Sub bus
2140 * @param dev Device ID
2141 * @param fn Device sub function
2142 * @param reg Register to access
2143 *
2144 * @return Result of the read
2145 */
cvmx_pcie_config_read16(int pcie_port,int bus,int dev,int fn,int reg)2146 uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev, int fn, int reg)
2147 {
2148 u64 address;
2149 int node = (pcie_port >> 4) & 0x3;
2150
2151 pcie_port &= 0x3;
2152 address = __cvmx_pcie_build_config_addr(node, pcie_port, bus, dev, fn, reg);
2153 if (address)
2154 return le16_to_cpu(cvmx_read64_uint16(address));
2155 else
2156 return 0xffff;
2157 }
2158
__cvmx_pcie_config_read32(int node,int pcie_port,int bus,int dev,int func,int reg,int lst)2159 static uint32_t __cvmx_pcie_config_read32(int node, int pcie_port, int bus, int dev, int func,
2160 int reg, int lst)
2161 {
2162 u64 address;
2163
2164 address = __cvmx_pcie_build_config_addr(node, pcie_port, bus, dev, func, reg);
2165 if (lst) {
2166 if (address && pcie_link_initialized[node][pcie_port])
2167 return le32_to_cpu(cvmx_read64_uint32(address));
2168 else
2169 return 0xffffffff;
2170 } else if (address) {
2171 return le32_to_cpu(cvmx_read64_uint32(address));
2172 } else {
2173 return 0xffffffff;
2174 }
2175 }
2176
2177 /**
2178 * Read 32bits from a Device's config space
2179 *
2180 * @param pcie_port PCIe port the device is on
2181 * @param bus Sub bus
2182 * @param dev Device ID
2183 * @param fn Device sub function
2184 * @param reg Register to access
2185 *
2186 * @return Result of the read
2187 */
cvmx_pcie_config_read32(int pcie_port,int bus,int dev,int fn,int reg)2188 uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev, int fn, int reg)
2189 {
2190 int node = (pcie_port >> 4) & 0x3;
2191
2192 pcie_port &= 0x3;
2193 return __cvmx_pcie_config_read32(node, pcie_port, bus, dev, fn, reg,
2194 pcie_link_initialized[node][pcie_port]);
2195 }
2196
2197 /**
2198 * Write 8bits to a Device's config space
2199 *
2200 * @param pcie_port PCIe port the device is on
2201 * @param bus Sub bus
2202 * @param dev Device ID
2203 * @param fn Device sub function
2204 * @param reg Register to access
2205 * @param val Value to write
2206 */
cvmx_pcie_config_write8(int pcie_port,int bus,int dev,int fn,int reg,uint8_t val)2207 void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn, int reg, uint8_t val)
2208 {
2209 u64 address;
2210 int node = (pcie_port >> 4) & 0x3;
2211
2212 pcie_port &= 0x3;
2213 address = __cvmx_pcie_build_config_addr(node, pcie_port, bus, dev, fn, reg);
2214 if (address)
2215 cvmx_write64_uint8(address, val);
2216 }
2217
2218 /**
2219 * Write 16bits to a Device's config space
2220 *
2221 * @param pcie_port PCIe port the device is on
2222 * @param bus Sub bus
2223 * @param dev Device ID
2224 * @param fn Device sub function
2225 * @param reg Register to access
2226 * @param val Value to write
2227 */
cvmx_pcie_config_write16(int pcie_port,int bus,int dev,int fn,int reg,uint16_t val)2228 void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn, int reg, uint16_t val)
2229 {
2230 u64 address;
2231 int node = (pcie_port >> 4) & 0x3;
2232
2233 pcie_port &= 0x3;
2234 address = __cvmx_pcie_build_config_addr(node, pcie_port, bus, dev, fn, reg);
2235 if (address)
2236 cvmx_write64_uint16(address, cpu_to_le16(val));
2237 }
2238
2239 /**
2240 * Write 32bits to a Device's config space
2241 *
2242 * @param pcie_port PCIe port the device is on
2243 * @param bus Sub bus
2244 * @param dev Device ID
2245 * @param fn Device sub function
2246 * @param reg Register to access
2247 * @param val Value to write
2248 */
cvmx_pcie_config_write32(int pcie_port,int bus,int dev,int fn,int reg,uint32_t val)2249 void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn, int reg, uint32_t val)
2250 {
2251 u64 address;
2252 int node = (pcie_port >> 4) & 0x3;
2253
2254 pcie_port &= 0x3;
2255 address = __cvmx_pcie_build_config_addr(node, pcie_port, bus, dev, fn, reg);
2256 if (address)
2257 cvmx_write64_uint32(address, cpu_to_le32(val));
2258 }
2259
2260 /**
2261 * Read a PCIe config space register indirectly. This is used for
2262 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
2263 *
2264 * @param pcie_port PCIe port to read from
2265 * @param cfg_offset Address to read
2266 *
2267 * @return Value read
2268 */
cvmx_pcie_cfgx_read(int pcie_port,uint32_t cfg_offset)2269 uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
2270 {
2271 return cvmx_pcie_cfgx_read_node(0, pcie_port, cfg_offset);
2272 }
2273
cvmx_pcie_cfgx_read_node(int node,int pcie_port,uint32_t cfg_offset)2274 uint32_t cvmx_pcie_cfgx_read_node(int node, int pcie_port, uint32_t cfg_offset)
2275 {
2276 cvmx_pemx_cfg_rd_t pemx_cfg_rd;
2277
2278 pemx_cfg_rd.u64 = 0;
2279 pemx_cfg_rd.s.addr = cfg_offset;
2280 CVMX_WRITE_CSR(CVMX_PEMX_CFG_RD(pcie_port), pemx_cfg_rd.u64);
2281 pemx_cfg_rd.u64 = CVMX_READ_CSR(CVMX_PEMX_CFG_RD(pcie_port));
2282
2283 return pemx_cfg_rd.s.data;
2284 }
2285
2286 /**
2287 * Write a PCIe config space register indirectly. This is used for
2288 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
2289 *
2290 * @param pcie_port PCIe port to write to
2291 * @param cfg_offset Address to write
2292 * @param val Value to write
2293 */
cvmx_pcie_cfgx_write(int pcie_port,uint32_t cfg_offset,uint32_t val)2294 void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset, uint32_t val)
2295 {
2296 cvmx_pcie_cfgx_write_node(0, pcie_port, cfg_offset, val);
2297 }
2298
cvmx_pcie_cfgx_write_node(int node,int pcie_port,uint32_t cfg_offset,uint32_t val)2299 void cvmx_pcie_cfgx_write_node(int node, int pcie_port, uint32_t cfg_offset, uint32_t val)
2300 {
2301 cvmx_pemx_cfg_wr_t pemx_cfg_wr;
2302
2303 pemx_cfg_wr.u64 = 0;
2304 pemx_cfg_wr.s.addr = cfg_offset;
2305 pemx_cfg_wr.s.data = val;
2306 CVMX_WRITE_CSR(CVMX_PEMX_CFG_WR(pcie_port), pemx_cfg_wr.u64);
2307 }
2308
2309 extern int cvmx_pcie_is_host_mode(int pcie_port);
2310
2311 /**
2312 * Initialize a PCIe port for use in target(EP) mode.
2313 *
2314 * @param pcie_port PCIe port to initialize for a node
2315 *
2316 * @return Zero on success
2317 */
cvmx_pcie_ep_initialize(int pcie_port)2318 int cvmx_pcie_ep_initialize(int pcie_port)
2319 {
2320 int node = (pcie_port >> 4) & 0x3;
2321
2322 if (cvmx_pcie_is_host_mode(pcie_port))
2323 return -1;
2324
2325 pcie_port &= 0x3;
2326
2327 /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be
2328 * programmed
2329 */
2330 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0)) {
2331 if (pcie_port) {
2332 cvmx_ciu_qlm1_t ciu_qlm;
2333
2334 ciu_qlm.u64 = csr_rd(CVMX_CIU_QLM1);
2335 ciu_qlm.s.txbypass = 1;
2336 ciu_qlm.s.txdeemph = 5;
2337 ciu_qlm.s.txmargin = 0x17;
2338 csr_wr(CVMX_CIU_QLM1, ciu_qlm.u64);
2339 } else {
2340 cvmx_ciu_qlm0_t ciu_qlm;
2341
2342 ciu_qlm.u64 = csr_rd(CVMX_CIU_QLM0);
2343 ciu_qlm.s.txbypass = 1;
2344 ciu_qlm.s.txdeemph = 5;
2345 ciu_qlm.s.txmargin = 0x17;
2346 csr_wr(CVMX_CIU_QLM0, ciu_qlm.u64);
2347 }
2348 }
2349
2350 /* Enable bus master and memory */
2351 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIEEPX_CFG001(pcie_port), 0x6);
2352
2353 /* Max Payload Size (PCIE*_CFG030[MPS]) */
2354 /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
2355 /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
2356 /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
2357 {
2358 cvmx_pcieepx_cfg030_t pcieepx_cfg030;
2359
2360 pcieepx_cfg030.u32 = CVMX_PCIE_CFGX_READ(pcie_port, CVMX_PCIEEPX_CFG030(pcie_port));
2361 pcieepx_cfg030.s.mps = MPS_CN6XXX;
2362 pcieepx_cfg030.s.mrrs = MRRS_CN6XXX;
2363 pcieepx_cfg030.s.ro_en = 1; /* Enable relaxed ordering. */
2364 pcieepx_cfg030.s.ns_en = 1; /* Enable no snoop. */
2365 pcieepx_cfg030.s.ce_en = 1; /* Correctable error reporting enable. */
2366 pcieepx_cfg030.s.nfe_en = 1; /* Non-fatal error reporting enable. */
2367 pcieepx_cfg030.s.fe_en = 1; /* Fatal error reporting enable. */
2368 pcieepx_cfg030.s.ur_en = 1; /* Unsupported request reporting enable. */
2369 CVMX_PCIE_CFGX_WRITE(pcie_port, CVMX_PCIEEPX_CFG030(pcie_port), pcieepx_cfg030.u32);
2370 }
2371
2372 /* Max Payload Size (DPI_SLI_PRTX_CFG[MPS]) must match
2373 * PCIE*_CFG030[MPS]
2374 */
2375 /* Max Read Request Size (DPI_SLI_PRTX_CFG[MRRS]) must not
2376 * exceed PCIE*_CFG030[MRRS]
2377 */
2378 cvmx_dpi_sli_prtx_cfg_t prt_cfg;
2379 cvmx_sli_s2m_portx_ctl_t sli_s2m_portx_ctl;
2380
2381 prt_cfg.u64 = CVMX_READ_CSR(CVMX_DPI_SLI_PRTX_CFG(pcie_port));
2382 prt_cfg.s.mps = MPS_CN6XXX;
2383 prt_cfg.s.mrrs = MRRS_CN6XXX;
2384 /* Max outstanding load request. */
2385 prt_cfg.s.molr = 32;
2386 CVMX_WRITE_CSR(CVMX_DPI_SLI_PRTX_CFG(pcie_port), prt_cfg.u64);
2387
2388 sli_s2m_portx_ctl.u64 = CVMX_READ_CSR(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port));
2389 if (!(OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN73XX) ||
2390 OCTEON_IS_MODEL(OCTEON_CNF75XX)))
2391 sli_s2m_portx_ctl.cn61xx.mrrs = MRRS_CN6XXX;
2392 CVMX_WRITE_CSR(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port), sli_s2m_portx_ctl.u64);
2393
2394 /* Setup Mem access SubDID 12 to access Host memory */
2395 cvmx_sli_mem_access_subidx_t mem_access_subid;
2396
2397 mem_access_subid.u64 = 0;
2398 mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
2399 mem_access_subid.s.nmerge = 0; /* Merging is allowed in this window. */
2400 mem_access_subid.s.esr = 0; /* Endian-swap for Reads. */
2401 mem_access_subid.s.esw = 0; /* Endian-swap for Writes. */
2402 mem_access_subid.s.wtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
2403 mem_access_subid.s.rtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
2404 /* PCIe Address Bits <63:34>. */
2405 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
2406 mem_access_subid.cn68xx.ba = 0;
2407 else
2408 mem_access_subid.cn63xx.ba = 0;
2409 CVMX_WRITE_CSR(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(12 + pcie_port * 4), mem_access_subid.u64);
2410
2411 return 0;
2412 }
2413
2414 /**
2415 * Wait for posted PCIe read/writes to reach the other side of
2416 * the internal PCIe switch. This will insure that core
2417 * read/writes are posted before anything after this function
2418 * is called. This may be necessary when writing to memory that
2419 * will later be read using the DMA/PKT engines.
2420 *
2421 * @param pcie_port PCIe port to wait for
2422 */
cvmx_pcie_wait_for_pending(int pcie_port)2423 void cvmx_pcie_wait_for_pending(int pcie_port)
2424 {
2425 cvmx_sli_data_out_cnt_t sli_data_out_cnt;
2426 int a;
2427 int b;
2428 int c;
2429
2430 sli_data_out_cnt.u64 = csr_rd(CVMX_PEXP_SLI_DATA_OUT_CNT);
2431 if (pcie_port) {
2432 if (!sli_data_out_cnt.s.p1_fcnt)
2433 return;
2434 a = sli_data_out_cnt.s.p1_ucnt;
2435 b = (a + sli_data_out_cnt.s.p1_fcnt - 1) & 0xffff;
2436 } else {
2437 if (!sli_data_out_cnt.s.p0_fcnt)
2438 return;
2439 a = sli_data_out_cnt.s.p0_ucnt;
2440 b = (a + sli_data_out_cnt.s.p0_fcnt - 1) & 0xffff;
2441 }
2442
2443 while (1) {
2444 sli_data_out_cnt.u64 = csr_rd(CVMX_PEXP_SLI_DATA_OUT_CNT);
2445 c = (pcie_port) ? sli_data_out_cnt.s.p1_ucnt :
2446 sli_data_out_cnt.s.p0_ucnt;
2447 if (a <= b) {
2448 if (c < a || c > b)
2449 return;
2450 } else {
2451 if (c > b && c < a)
2452 return;
2453 }
2454 }
2455 }
2456
2457 /**
2458 * Returns if a PCIe port is in host or target mode.
2459 *
2460 * @param pcie_port PCIe port number (PEM number)
2461 *
2462 * @return 0 if PCIe port is in target mode, !0 if in host mode.
2463 */
cvmx_pcie_is_host_mode(int pcie_port)2464 int cvmx_pcie_is_host_mode(int pcie_port)
2465 {
2466 int node = (pcie_port >> 4) & 0x3;
2467 cvmx_mio_rst_ctlx_t mio_rst_ctl;
2468
2469 pcie_port &= 0x3;
2470 if (OCTEON_IS_MODEL(OCTEON_CN78XX) || OCTEON_IS_MODEL(OCTEON_CN73XX)) {
2471 cvmx_pemx_strap_t strap;
2472
2473 strap.u64 = CVMX_READ_CSR(CVMX_PEMX_STRAP(pcie_port));
2474 return (strap.cn78xx.pimode == 3);
2475 } else if (OCTEON_IS_MODEL(OCTEON_CN70XX)) {
2476 cvmx_rst_ctlx_t rst_ctl;
2477
2478 rst_ctl.u64 = csr_rd(CVMX_RST_CTLX(pcie_port));
2479 return !!rst_ctl.s.host_mode;
2480 }
2481
2482 mio_rst_ctl.u64 = csr_rd(CVMX_MIO_RST_CTLX(pcie_port));
2483 if (OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))
2484 return mio_rst_ctl.s.prtmode != 0;
2485 else
2486 return !!mio_rst_ctl.s.host_mode;
2487 }
2488