1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Based on da830evm.c. Original Copyrights follow:
6 *
7 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
8 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
9 */
10
11 #include <common.h>
12 #include <dm.h>
13 #include <env.h>
14 #include <i2c.h>
15 #include <init.h>
16 #include <net.h>
17 #include <spi.h>
18 #include <spi_flash.h>
19 #include <asm/arch/hardware.h>
20 #include <asm/global_data.h>
21 #include <asm/ti-common/davinci_nand.h>
22 #include <asm/arch/emac_defs.h>
23 #include <asm/arch/pinmux_defs.h>
24 #include <asm/io.h>
25 #include <asm/arch/davinci_misc.h>
26 #include <linux/errno.h>
27 #include <hwconfig.h>
28 #include <asm/mach-types.h>
29 #include <asm/gpio.h>
30
31 #ifdef CONFIG_MMC_DAVINCI
32 #include <mmc.h>
33 #include <asm/arch/sdmmc_defs.h>
34 #endif
35
36 DECLARE_GLOBAL_DATA_PTR;
37
38 #ifdef CONFIG_DRIVER_TI_EMAC
39 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
40 #define HAS_RMII 1
41 #else
42 #define HAS_RMII 0
43 #endif
44 #endif /* CONFIG_DRIVER_TI_EMAC */
45
46 #define CFG_MAC_ADDR_SPI_BUS 0
47 #define CFG_MAC_ADDR_SPI_CS 0
48 #define CFG_MAC_ADDR_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
49 #define CFG_MAC_ADDR_SPI_MODE SPI_MODE_3
50
51 #define CFG_MAC_ADDR_OFFSET (flash->size - SZ_64K)
52
53 #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
get_mac_addr(u8 * addr)54 static int get_mac_addr(u8 *addr)
55 {
56 struct spi_flash *flash;
57 int ret;
58
59 flash = spi_flash_probe(CFG_MAC_ADDR_SPI_BUS, CFG_MAC_ADDR_SPI_CS,
60 CFG_MAC_ADDR_SPI_MAX_HZ, CFG_MAC_ADDR_SPI_MODE);
61 if (!flash) {
62 printf("Error - unable to probe SPI flash.\n");
63 return -1;
64 }
65
66 ret = spi_flash_read(flash, (CFG_MAC_ADDR_OFFSET), 6, addr);
67 if (ret) {
68 printf("Error - unable to read MAC address from SPI flash.\n");
69 return -1;
70 }
71
72 return ret;
73 }
74 #endif
75
dsp_lpsc_on(unsigned domain,unsigned int id)76 void dsp_lpsc_on(unsigned domain, unsigned int id)
77 {
78 dv_reg_p mdstat, mdctl, ptstat, ptcmd;
79 struct davinci_psc_regs *psc_regs;
80
81 psc_regs = davinci_psc0_regs;
82 mdstat = &psc_regs->psc0.mdstat[id];
83 mdctl = &psc_regs->psc0.mdctl[id];
84 ptstat = &psc_regs->ptstat;
85 ptcmd = &psc_regs->ptcmd;
86
87 while (*ptstat & (0x1 << domain))
88 ;
89
90 if ((*mdstat & 0x1f) == 0x03)
91 return; /* Already on and enabled */
92
93 *mdctl |= 0x03;
94
95 *ptcmd = 0x1 << domain;
96
97 while (*ptstat & (0x1 << domain))
98 ;
99 while ((*mdstat & 0x1f) != 0x03)
100 ; /* Probably an overkill... */
101 }
102
dspwake(void)103 static void dspwake(void)
104 {
105 unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
106 u32 val;
107
108 /* if the device is ARM only, return */
109 if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10)
110 return;
111
112 if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL))
113 return;
114
115 *resetvect++ = 0x1E000; /* DSP Idle */
116 /* clear out the next 10 words as NOP */
117 memset(resetvect, 0, sizeof(unsigned) *10);
118
119 /* setup the DSP reset vector */
120 writel(DAVINCI_L3CBARAM_BASE, HOST1CFG);
121
122 dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
123 val = readl(PSC0_MDCTL + (15 * 4));
124 val |= 0x100;
125 writel(val, (PSC0_MDCTL + (15 * 4)));
126 }
127
misc_init_r(void)128 int misc_init_r(void)
129 {
130 dspwake();
131
132 #if defined(CONFIG_MAC_ADDR_IN_SPIFLASH) || defined(CONFIG_MAC_ADDR_IN_EEPROM)
133
134 uchar env_enetaddr[6];
135 int enetaddr_found;
136
137 enetaddr_found = eth_env_get_enetaddr("ethaddr", env_enetaddr);
138
139 #endif
140
141 #ifdef CONFIG_MAC_ADDR_IN_SPIFLASH
142 int spi_mac_read;
143 uchar buff[6];
144
145 spi_mac_read = get_mac_addr(buff);
146 buff[0] = 0;
147
148 /*
149 * MAC address not present in the environment
150 * try and read the MAC address from SPI flash
151 * and set it.
152 */
153 if (!enetaddr_found) {
154 if (!spi_mac_read) {
155 if (is_valid_ethaddr(buff)) {
156 if (eth_env_set_enetaddr("ethaddr", buff)) {
157 printf("Warning: Failed to "
158 "set MAC address from SPI flash\n");
159 }
160 } else {
161 printf("Warning: Invalid "
162 "MAC address read from SPI flash\n");
163 }
164 }
165 } else {
166 /*
167 * MAC address present in environment compare it with
168 * the MAC address in SPI flash and warn on mismatch
169 */
170 if (!spi_mac_read && is_valid_ethaddr(buff) &&
171 memcmp(env_enetaddr, buff, 6))
172 printf("Warning: MAC address in SPI flash don't match "
173 "with the MAC address in the environment\n");
174 printf("Default using MAC address from environment\n");
175 }
176
177 #elif defined(CONFIG_MAC_ADDR_IN_EEPROM)
178 uint8_t enetaddr[8];
179 int eeprom_mac_read;
180
181 /* Read Ethernet MAC address from EEPROM */
182 eeprom_mac_read = dvevm_read_mac_address(enetaddr);
183
184 /*
185 * MAC address not present in the environment
186 * try and read the MAC address from EEPROM flash
187 * and set it.
188 */
189 if (!enetaddr_found) {
190 if (eeprom_mac_read)
191 /* Set Ethernet MAC address from EEPROM */
192 davinci_sync_env_enetaddr(enetaddr);
193 } else {
194 /*
195 * MAC address present in environment compare it with
196 * the MAC address in EEPROM and warn on mismatch
197 */
198 if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6))
199 printf("Warning: MAC address in EEPROM don't match "
200 "with the MAC address in the environment\n");
201 printf("Default using MAC address from environment\n");
202 }
203
204 #endif
205 return 0;
206 }
207
208 static const struct pinmux_config gpio_pins[] = {
209 #ifdef CONFIG_MTD_NOR_FLASH
210 /* GP0[11] is required for NOR to work on Rev 3 EVMs */
211 { pinmux(0), 8, 4 }, /* GP0[11] */
212 #endif
213 #ifdef CONFIG_MMC_DAVINCI
214 /* GP0[11] is required for SD to work on Rev 3 EVMs */
215 { pinmux(0), 8, 4 }, /* GP0[11] */
216 #endif
217 };
218
219 const struct pinmux_resource pinmuxes[] = {
220 #ifdef CONFIG_DRIVER_TI_EMAC
221 PINMUX_ITEM(emac_pins_mdio),
222 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
223 PINMUX_ITEM(emac_pins_rmii),
224 #else
225 PINMUX_ITEM(emac_pins_mii),
226 #endif
227 #endif
228 #ifdef CONFIG_SPI_FLASH
229 PINMUX_ITEM(spi1_pins_base),
230 PINMUX_ITEM(spi1_pins_scs0),
231 #endif
232 PINMUX_ITEM(uart2_pins_txrx),
233 PINMUX_ITEM(uart2_pins_rtscts),
234 PINMUX_ITEM(i2c0_pins),
235 #ifdef CONFIG_NAND_DAVINCI
236 PINMUX_ITEM(emifa_pins_cs3),
237 PINMUX_ITEM(emifa_pins_cs4),
238 PINMUX_ITEM(emifa_pins_nand),
239 #elif defined(CONFIG_MTD_NOR_FLASH)
240 PINMUX_ITEM(emifa_pins_cs2),
241 PINMUX_ITEM(emifa_pins_nor),
242 #endif
243 PINMUX_ITEM(gpio_pins),
244 #ifdef CONFIG_MMC_DAVINCI
245 PINMUX_ITEM(mmc0_pins),
246 #endif
247 };
248
249 const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
250
251 const struct lpsc_resource lpsc[] = {
252 { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
253 { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
254 { DAVINCI_LPSC_EMAC }, /* image download */
255 { DAVINCI_LPSC_UART2 }, /* console */
256 { DAVINCI_LPSC_GPIO },
257 #ifdef CONFIG_MMC_DAVINCI
258 { DAVINCI_LPSC_MMC_SD },
259 #endif
260 };
261
262 const int lpsc_size = ARRAY_SIZE(lpsc);
263
264 #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
265 #define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000
266 #endif
267
268 #define REV_AM18X_EVM 0x100
269
270 /*
271 * get_board_rev() - setup to pass kernel board revision information
272 * Returns:
273 * bit[0-3] Maximum cpu clock rate supported by onboard SoC
274 * 0000b - 300 MHz
275 * 0001b - 372 MHz
276 * 0010b - 408 MHz
277 * 0011b - 456 MHz
278 */
get_board_rev(void)279 u32 get_board_rev(void)
280 {
281 char *s;
282 u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
283 u32 rev = 0;
284
285 s = env_get("maxcpuclk");
286 if (s)
287 maxcpuclk = simple_strtoul(s, NULL, 10);
288
289 if (maxcpuclk >= 456000000)
290 rev = 3;
291 else if (maxcpuclk >= 408000000)
292 rev = 2;
293 else if (maxcpuclk >= 372000000)
294 rev = 1;
295 return rev;
296 }
297
board_early_init_f(void)298 int board_early_init_f(void)
299 {
300 /*
301 * Power on required peripherals
302 * ARM does not have access by default to PSC0 and PSC1
303 * assuming here that the DSP bootloader has set the IOPU
304 * such that PSC access is available to ARM
305 */
306 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
307 return 1;
308
309 return 0;
310 }
311
board_init(void)312 int board_init(void)
313 {
314 irq_init();
315
316 #ifdef CONFIG_NAND_DAVINCI
317 /*
318 * NAND CS setup - cycle counts based on da850evm NAND timings in the
319 * Linux kernel @ 25MHz EMIFA
320 */
321 writel((DAVINCI_ABCR_WSETUP(2) |
322 DAVINCI_ABCR_WSTROBE(2) |
323 DAVINCI_ABCR_WHOLD(1) |
324 DAVINCI_ABCR_RSETUP(1) |
325 DAVINCI_ABCR_RSTROBE(4) |
326 DAVINCI_ABCR_RHOLD(0) |
327 DAVINCI_ABCR_TA(1) |
328 DAVINCI_ABCR_ASIZE_8BIT),
329 &davinci_emif_regs->ab2cr); /* CS3 */
330 #endif
331
332 /* arch number of the board */
333 gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
334
335 /* address of boot parameters */
336 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
337
338 /* setup the SUSPSRC for ARM to control emulation suspend */
339 writel(readl(&davinci_syscfg_regs->suspsrc) &
340 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
341 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
342 DAVINCI_SYSCFG_SUSPSRC_UART2),
343 &davinci_syscfg_regs->suspsrc);
344
345 #ifdef CONFIG_MTD_NOR_FLASH
346 /* Set the GPIO direction as output */
347 clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
348
349 /* Set the output as low */
350 writel(0x01 << 11, GPIO_BANK0_REG_CLR_ADDR);
351 #endif
352
353 #ifdef CONFIG_MMC_DAVINCI
354 /* Set the GPIO direction as output */
355 clrbits_le32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
356
357 /* Set the output as high */
358 writel(0x01 << 11, GPIO_BANK0_REG_SET_ADDR);
359 #endif
360
361 #ifdef CONFIG_DRIVER_TI_EMAC
362 davinci_emac_mii_mode_sel(HAS_RMII);
363 #endif /* CONFIG_DRIVER_TI_EMAC */
364
365 return 0;
366 }
367
368 #ifdef CONFIG_DRIVER_TI_EMAC
369
370 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
371 /**
372 * rmii_hw_init
373 *
374 * DA850/OMAP-L138 EVM can interface to a daughter card for
375 * additional features. This card has an I2C GPIO Expander TCA6416
376 * to select the required functions like camera, RMII Ethernet,
377 * character LCD, video.
378 *
379 * Initialization of the expander involves configuring the
380 * polarity and direction of the ports. P07-P05 are used here.
381 * These ports are connected to a Mux chip which enables only one
382 * functionality at a time.
383 *
384 * For RMII phy to respond, the MII MDIO clock has to be disabled
385 * since both the PHY devices have address as zero. The MII MDIO
386 * clock is controlled via GPIO2[6].
387 *
388 * This code is valid for Beta version of the hardware
389 */
rmii_hw_init(void)390 int rmii_hw_init(void)
391 {
392 const struct pinmux_config gpio_pins[] = {
393 { pinmux(6), 8, 1 }
394 };
395 u_int8_t buf[2];
396 unsigned int temp;
397 int ret;
398
399 /* PinMux for GPIO */
400 if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
401 return 1;
402
403 /* I2C Exapnder configuration */
404 /* Set polarity to non-inverted */
405 buf[0] = 0x0;
406 buf[1] = 0x0;
407 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
408 if (ret) {
409 printf("\nExpander @ 0x%02x write FAILED!!!\n",
410 CONFIG_SYS_I2C_EXPANDER_ADDR);
411 return ret;
412 }
413
414 /* Configure P07-P05 as outputs */
415 buf[0] = 0x1f;
416 buf[1] = 0xff;
417 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
418 if (ret) {
419 printf("\nExpander @ 0x%02x write FAILED!!!\n",
420 CONFIG_SYS_I2C_EXPANDER_ADDR);
421 }
422
423 /* For Ethernet RMII selection
424 * P07(SelA)=0
425 * P06(SelB)=1
426 * P05(SelC)=1
427 */
428 if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
429 printf("\nExpander @ 0x%02x read FAILED!!!\n",
430 CONFIG_SYS_I2C_EXPANDER_ADDR);
431 }
432
433 buf[0] &= 0x1f;
434 buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
435 if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
436 printf("\nExpander @ 0x%02x write FAILED!!!\n",
437 CONFIG_SYS_I2C_EXPANDER_ADDR);
438 }
439
440 /* Set the output as high */
441 temp = REG(GPIO_BANK2_REG_SET_ADDR);
442 temp |= (0x01 << 6);
443 REG(GPIO_BANK2_REG_SET_ADDR) = temp;
444
445 /* Set the GPIO direction as output */
446 temp = REG(GPIO_BANK2_REG_DIR_ADDR);
447 temp &= ~(0x01 << 6);
448 REG(GPIO_BANK2_REG_DIR_ADDR) = temp;
449
450 return 0;
451 }
452 #endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
453
454 /*
455 * Initializes on-board ethernet controllers.
456 */
board_eth_init(struct bd_info * bis)457 int board_eth_init(struct bd_info *bis)
458 {
459 #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
460 /* Select RMII fucntion through the expander */
461 if (rmii_hw_init())
462 printf("RMII hardware init failed!!!\n");
463 #endif
464 return 0;
465 }
466 #endif /* CONFIG_DRIVER_TI_EMAC */
467