1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * K3: R5 MPU region definitions
4 *
5 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
7 */
8
9 #include <common.h>
10 #include <asm/io.h>
11 #include <linux/kernel.h>
12 #include "common.h"
13
14 struct mpu_region_config k3_mpu_regions[16] = {
15 /*
16 * Make all 4GB as Device Memory and not executable. We are overriding
17 * it with next region for any requirement.
18 */
19 {0x00000000, REGION_0, XN_EN, PRIV_RW_USR_RW, SHARED_WRITE_BUFFERED,
20 REGION_4GB},
21
22 /* SPL code area marking it as WB and Write allocate. */
23 {CONFIG_SPL_TEXT_BASE, REGION_1, XN_DIS, PRIV_RW_USR_RW,
24 O_I_WB_RD_WR_ALLOC, REGION_8MB},
25
26 /* U-Boot's code area marking it as WB and Write allocate */
27 {CONFIG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW,
28 O_I_WB_RD_WR_ALLOC, REGION_2GB},
29 /* mcu_r5fss0_core0 BTCM area marking it as WB and Write allocate. */
30 {0x41010000, 3, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC,
31 REGION_8MB},
32 {0x0, 4, 0x0, 0x0, 0x0, 0x0},
33 {0x0, 5, 0x0, 0x0, 0x0, 0x0},
34 {0x0, 6, 0x0, 0x0, 0x0, 0x0},
35 {0x0, 7, 0x0, 0x0, 0x0, 0x0},
36 {0x0, 8, 0x0, 0x0, 0x0, 0x0},
37 {0x0, 9, 0x0, 0x0, 0x0, 0x0},
38 {0x0, 10, 0x0, 0x0, 0x0, 0x0},
39 {0x0, 11, 0x0, 0x0, 0x0, 0x0},
40 {0x0, 12, 0x0, 0x0, 0x0, 0x0},
41 {0x0, 13, 0x0, 0x0, 0x0, 0x0},
42 {0x0, 14, 0x0, 0x0, 0x0, 0x0},
43 {0x0, 15, 0x0, 0x0, 0x0, 0x0},
44 };
45
setup_k3_mpu_regions(void)46 void setup_k3_mpu_regions(void)
47 {
48 setup_mpu_regions(k3_mpu_regions, ARRAY_SIZE(k3_mpu_regions));
49 }
50