1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2019 Toradex
4 */
5
6 #include <common.h>
7 #include <cpu_func.h>
8 #include <init.h>
9 #include <asm/global_data.h>
10
11 #include <asm/arch/clock.h>
12 #include <asm/arch/imx8-pins.h>
13 #include <asm/arch/iomux.h>
14 #include <asm/arch/sci/sci.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/gpio.h>
17 #include <asm/io.h>
18 #include <env.h>
19 #include <errno.h>
20 #include <linux/libfdt.h>
21
22 #include "../common/tdx-cfg-block.h"
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
27 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
28 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
29 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
30
31 static iomux_cfg_t uart1_pads[] = {
32 SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
33 SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
34 };
35
setup_iomux_uart(void)36 static void setup_iomux_uart(void)
37 {
38 imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
39 }
40
board_mem_get_layout(u64 * phys_sdram_1_start,u64 * phys_sdram_1_size,u64 * phys_sdram_2_start,u64 * phys_sdram_2_size)41 void board_mem_get_layout(u64 *phys_sdram_1_start,
42 u64 *phys_sdram_1_size,
43 u64 *phys_sdram_2_start,
44 u64 *phys_sdram_2_size)
45 {
46 u32 is_quadplus = 0, val = 0;
47 sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val);
48
49 if (scierr == SC_ERR_NONE) {
50 /* QP has one A72 core disabled */
51 is_quadplus = ((val >> 4) & 0x3) != 0x0;
52 }
53
54 *phys_sdram_1_start = PHYS_SDRAM_1;
55 *phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
56 *phys_sdram_2_start = PHYS_SDRAM_2;
57 if (is_quadplus)
58 /* Our QP based SKUs only have 2 GB RAM (PHYS_SDRAM_1_SIZE) */
59 *phys_sdram_2_size = 0x0UL;
60 else
61 *phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
62 }
63
board_early_init_f(void)64 int board_early_init_f(void)
65 {
66 sc_pm_clock_rate_t rate = SC_80MHZ;
67 sc_err_t err = 0;
68
69 /* Set UART1 clock root to 80 MHz and enable it */
70 err = sc_pm_setup_uart(SC_R_UART_1, rate);
71 if (err != SC_ERR_NONE)
72 return 0;
73
74 setup_iomux_uart();
75
76 return 0;
77 }
78
79 #if CONFIG_IS_ENABLED(DM_GPIO)
board_gpio_init(void)80 static void board_gpio_init(void)
81 {
82 /* TODO */
83 }
84 #else
board_gpio_init(void)85 static inline void board_gpio_init(void) {}
86 #endif
87
88 #if IS_ENABLED(CONFIG_FEC_MXC)
89 #include <miiphy.h>
90
board_phy_config(struct phy_device * phydev)91 int board_phy_config(struct phy_device *phydev)
92 {
93 if (phydev->drv->config)
94 phydev->drv->config(phydev);
95
96 return 0;
97 }
98 #endif
99
checkboard(void)100 int checkboard(void)
101 {
102 puts("Model: Toradex Apalis iMX8\n");
103
104 build_info();
105 print_bootinfo();
106
107 return 0;
108 }
109
board_init(void)110 int board_init(void)
111 {
112 board_gpio_init();
113
114 return 0;
115 }
116
117 /*
118 * Board specific reset that is system reset.
119 */
reset_cpu(void)120 void reset_cpu(void)
121 {
122 /* TODO */
123 }
124
125 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,struct bd_info * bd)126 int ft_board_setup(void *blob, struct bd_info *bd)
127 {
128 return ft_common_board_setup(blob, bd);
129 }
130 #endif
131
board_mmc_get_env_dev(int devno)132 int board_mmc_get_env_dev(int devno)
133 {
134 return devno;
135 }
136
board_late_init(void)137 int board_late_init(void)
138 {
139 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
140 /* TODO move to common */
141 env_set("board_name", "Apalis iMX8QM");
142 env_set("board_rev", "v1.0");
143 #endif
144
145 return 0;
146 }
147