1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2015 - 2016 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
5 */
6 #include <common.h>
7 #include <dm.h>
8 #include <ahci.h>
9 #include <log.h>
10 #include <scsi.h>
11 #include <asm/io.h>
12 #include <linux/ioport.h>
13
14 /* Vendor Specific Register Offsets */
15 #define AHCI_VEND_PCFG 0xA4
16 #define AHCI_VEND_PPCFG 0xA8
17 #define AHCI_VEND_PP2C 0xAC
18 #define AHCI_VEND_PP3C 0xB0
19 #define AHCI_VEND_PP4C 0xB4
20 #define AHCI_VEND_PP5C 0xB8
21 #define AHCI_VEND_AXICC 0xBc
22 #define AHCI_VEND_PAXIC 0xC0
23 #define AHCI_VEND_PTC 0xC8
24
25 /* Vendor Specific Register bit definitions */
26 #define PAXIC_ADBW_BW64 0x1
27 #define PAXIC_MAWIDD (1 << 8)
28 #define PAXIC_MARIDD (1 << 16)
29 #define PAXIC_OTL (0x4 << 20)
30
31 #define PCFG_TPSS_VAL (0x32 << 16)
32 #define PCFG_TPRS_VAL (0x2 << 12)
33 #define PCFG_PAD_VAL 0x2
34
35 #define PPCFG_TTA 0x1FFFE
36 #define PPCFG_PSSO_EN (1 << 28)
37 #define PPCFG_PSS_EN (1 << 29)
38 #define PPCFG_ESDF_EN (1 << 31)
39
40 #define PP2C_CIBGMN 0x0F
41 #define PP2C_CIBGMX (0x25 << 8)
42 #define PP2C_CIBGN (0x18 << 16)
43 #define PP2C_CINMP (0x29 << 24)
44
45 #define PP3C_CWBGMN 0x04
46 #define PP3C_CWBGMX (0x0B << 8)
47 #define PP3C_CWBGN (0x08 << 16)
48 #define PP3C_CWNMP (0x0F << 24)
49
50 #define PP4C_BMX 0x0a
51 #define PP4C_BNM (0x08 << 8)
52 #define PP4C_SFD (0x4a << 16)
53 #define PP4C_PTST (0x06 << 24)
54
55 #define PP5C_RIT 0x60216
56 #define PP5C_RCT (0x7f0 << 20)
57
58 #define PTC_RX_WM_VAL 0x40
59 #define PTC_RSVD (1 << 27)
60
61 #define PORT0_BASE 0x100
62 #define PORT1_BASE 0x180
63
64 /* Port Control Register Bit Definitions */
65 #define PORT_SCTL_SPD_GEN3 (0x3 << 4)
66 #define PORT_SCTL_SPD_GEN2 (0x2 << 4)
67 #define PORT_SCTL_SPD_GEN1 (0x1 << 4)
68 #define PORT_SCTL_IPM (0x3 << 8)
69
70 #define PORT_BASE 0x100
71 #define PORT_OFFSET 0x80
72 #define NR_PORTS 2
73 #define DRV_NAME "ahci-ceva"
74 #define CEVA_FLAG_BROKEN_GEN2 1
75
76 /* flag bit definition */
77 #define FLAG_COHERENT 1
78
79 /* register config value */
80 #define CEVA_PHY1_CFG 0xa003fffe
81 #define CEVA_PHY2_CFG 0x28184d1f
82 #define CEVA_PHY3_CFG 0x0e081509
83 #define CEVA_TRANS_CFG 0x08000029
84 #define CEVA_AXICC_CFG 0x3fffffff
85
86 /* for ls1021a */
87 #define LS1021_AHCI_VEND_AXICC 0xC0
88 #define LS1021_CEVA_PHY2_CFG 0x28183414
89 #define LS1021_CEVA_PHY3_CFG 0x0e080e06
90 #define LS1021_CEVA_PHY4_CFG 0x064a080b
91 #define LS1021_CEVA_PHY5_CFG 0x2aa86470
92
93 /* ecc val pair */
94 #define ECC_DIS_VAL_CH1 0x00020000
95 #define ECC_DIS_VAL_CH2 0x80000000
96 #define ECC_DIS_VAL_CH3 0x40000000
97
98 enum ceva_soc {
99 CEVA_1V84,
100 CEVA_LS1012A,
101 CEVA_LS1021A,
102 CEVA_LS1028A,
103 CEVA_LS1043A,
104 CEVA_LS1046A,
105 CEVA_LS1088A,
106 CEVA_LS2080A,
107 };
108
109 struct ceva_sata_priv {
110 ulong base;
111 ulong ecc_base;
112 enum ceva_soc soc;
113 ulong flag;
114 };
115
ceva_init_sata(struct ceva_sata_priv * priv)116 static int ceva_init_sata(struct ceva_sata_priv *priv)
117 {
118 ulong ecc_addr = priv->ecc_base;
119 ulong base = priv->base;
120 ulong tmp;
121
122 switch (priv->soc) {
123 case CEVA_1V84:
124 tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
125 writel(tmp, base + AHCI_VEND_PAXIC);
126 tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | PCFG_PAD_VAL;
127 writel(tmp, base + AHCI_VEND_PCFG);
128 tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
129 writel(tmp, base + AHCI_VEND_PPCFG);
130 tmp = PTC_RX_WM_VAL | PTC_RSVD;
131 writel(tmp, base + AHCI_VEND_PTC);
132 break;
133
134 case CEVA_LS1021A:
135 if (!ecc_addr)
136 return -EINVAL;
137 writel(ECC_DIS_VAL_CH1, ecc_addr);
138 writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
139 writel(LS1021_CEVA_PHY2_CFG, base + AHCI_VEND_PP2C);
140 writel(LS1021_CEVA_PHY3_CFG, base + AHCI_VEND_PP3C);
141 writel(LS1021_CEVA_PHY4_CFG, base + AHCI_VEND_PP4C);
142 writel(LS1021_CEVA_PHY5_CFG, base + AHCI_VEND_PP5C);
143 writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
144 break;
145
146 case CEVA_LS1012A:
147 case CEVA_LS1043A:
148 case CEVA_LS1046A:
149 if (!ecc_addr)
150 return -EINVAL;
151 writel(ECC_DIS_VAL_CH2, ecc_addr);
152 /* fallthrough */
153 case CEVA_LS2080A:
154 writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
155 writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
156 break;
157
158 case CEVA_LS1028A:
159 case CEVA_LS1088A:
160 if (!ecc_addr)
161 return -EINVAL;
162 writel(ECC_DIS_VAL_CH3, ecc_addr);
163 writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
164 writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
165 break;
166 }
167
168 if (priv->flag & FLAG_COHERENT)
169 writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);
170
171 return 0;
172 }
173
sata_ceva_bind(struct udevice * dev)174 static int sata_ceva_bind(struct udevice *dev)
175 {
176 struct udevice *scsi_dev;
177
178 return ahci_bind_scsi(dev, &scsi_dev);
179 }
180
sata_ceva_probe(struct udevice * dev)181 static int sata_ceva_probe(struct udevice *dev)
182 {
183 struct ceva_sata_priv *priv = dev_get_priv(dev);
184
185 ceva_init_sata(priv);
186
187 return ahci_probe_scsi(dev, priv->base);
188 }
189
190 static const struct udevice_id sata_ceva_ids[] = {
191 { .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
192 { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
193 { .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A },
194 { .compatible = "fsl,ls1028a-ahci", .data = CEVA_LS1028A },
195 { .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A },
196 { .compatible = "fsl,ls1046a-ahci", .data = CEVA_LS1046A },
197 { .compatible = "fsl,ls1088a-ahci", .data = CEVA_LS1088A },
198 { .compatible = "fsl,ls2080a-ahci", .data = CEVA_LS2080A },
199 { }
200 };
201
sata_ceva_of_to_plat(struct udevice * dev)202 static int sata_ceva_of_to_plat(struct udevice *dev)
203 {
204 struct ceva_sata_priv *priv = dev_get_priv(dev);
205 struct resource res_regs;
206 int ret;
207
208 if (dev_read_bool(dev, "dma-coherent"))
209 priv->flag |= FLAG_COHERENT;
210
211 priv->base = dev_read_addr(dev);
212 if (priv->base == FDT_ADDR_T_NONE)
213 return -EINVAL;
214
215 ret = dev_read_resource_byname(dev, "ecc-addr", &res_regs);
216 if (ret)
217 priv->ecc_base = 0;
218 else
219 priv->ecc_base = res_regs.start;
220
221 priv->soc = dev_get_driver_data(dev);
222
223 debug("ccsr-sata-base %lx\t ecc-base %lx\n",
224 priv->base,
225 priv->ecc_base);
226
227 return 0;
228 }
229
230 U_BOOT_DRIVER(ceva_host_blk) = {
231 .name = "ceva_sata",
232 .id = UCLASS_AHCI,
233 .of_match = sata_ceva_ids,
234 .bind = sata_ceva_bind,
235 .ops = &scsi_ops,
236 .priv_auto = sizeof(struct ceva_sata_priv),
237 .probe = sata_ceva_probe,
238 .of_to_plat = sata_ceva_of_to_plat,
239 };
240