1// SPDX-License-Identifier: GPL-2.0+ OR X11 2/* 3 * NXP ls1028a SOC common device tree source 4 * 5 * Copyright 2019-2020 NXP 6 * 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "fsl,ls1028a"; 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 sysclk: sysclk { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 clock-frequency = <100000000>; 21 clock-output-names = "sysclk"; 22 }; 23 24 clockgen: clocking@1300000 { 25 compatible = "fsl,ls1028a-clockgen"; 26 reg = <0x0 0x1300000 0x0 0xa0000>; 27 #clock-cells = <2>; 28 clocks = <&sysclk>; 29 }; 30 31 memory@01080000 { 32 device_type = "memory"; 33 reg = <0x00000000 0x01080000 0 0x80000000>; 34 /* DRAM space - 1, size : 2 GB DRAM */ 35 }; 36 37 gic: interrupt-controller@6000000 { 38 compatible = "arm,gic-v3"; 39 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 40 <0x0 0x06040000 0 0x40000>; 41 #interrupt-cells = <3>; 42 interrupt-controller; 43 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 44 IRQ_TYPE_LEVEL_LOW)>; 45 }; 46 47 gic_lpi_base: syscon@0x80000000 { 48 compatible = "gic-lpi-base"; 49 reg = <0x0 0x80000000 0x0 0x100000>; 50 max-gic-redistributors = <2>; 51 }; 52 53 timer { 54 compatible = "arm,armv8-timer"; 55 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 56 IRQ_TYPE_LEVEL_LOW)>, 57 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 58 IRQ_TYPE_LEVEL_LOW)>, 59 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 60 IRQ_TYPE_LEVEL_LOW)>, 61 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 62 IRQ_TYPE_LEVEL_LOW)>; 63 }; 64 65 fspi: flexspi@20c0000 { 66 compatible = "nxp,lx2160a-fspi"; 67 #address-cells = <1>; 68 #size-cells = <0>; 69 reg = <0x0 0x20c0000 0x0 0x10000>, 70 <0x0 0x20000000 0x0 0x10000000>; 71 reg-names = "fspi_base", "fspi_mmap"; 72 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 73 clock-names = "fspi_en", "fspi"; 74 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 75 status = "disabled"; 76 }; 77 78 serial0: serial@21c0500 { 79 device_type = "serial"; 80 compatible = "fsl,ns16550", "ns16550a"; 81 reg = <0x0 0x21c0500 0x0 0x100>; 82 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 83 status = "disabled"; 84 }; 85 86 serial1: serial@21c0600 { 87 device_type = "serial"; 88 compatible = "fsl,ns16550", "ns16550a"; 89 reg = <0x0 0x21c0600 0x0 0x100>; 90 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 91 status = "disabled"; 92 }; 93 94 pcie1: pcie@3400000 { 95 compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; 96 reg = <0x00 0x03400000 0x0 0x80000 97 0x00 0x03480000 0x0 0x40000 /* lut registers */ 98 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ 99 0x80 0x00000000 0x0 0x20000>; /* configuration space */ 100 reg-names = "dbi", "lut", "ctrl", "config"; 101 #address-cells = <3>; 102 #size-cells = <2>; 103 device_type = "pci"; 104 num-lanes = <4>; 105 bus-range = <0x0 0xff>; 106 ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */ 107 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 108 }; 109 110 pcie2: pcie@3500000 { 111 compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; 112 reg = <0x00 0x03500000 0x0 0x80000 113 0x00 0x03580000 0x0 0x40000 /* lut registers */ 114 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */ 115 0x88 0x00000000 0x0 0x20000>; /* configuration space */ 116 reg-names = "dbi", "lut", "ctrl", "config"; 117 #address-cells = <3>; 118 #size-cells = <2>; 119 device_type = "pci"; 120 num-lanes = <4>; 121 bus-range = <0x0 0xff>; 122 ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */ 123 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 124 }; 125 126 pcie@1f0000000 { 127 compatible = "pci-host-ecam-generic"; 128 /* ECAM bus 0, HW has more space reserved but not populated */ 129 bus-range = <0x0 0x0>; 130 reg = <0x01 0xf0000000 0x0 0x100000>; 131 #address-cells = <3>; 132 #size-cells = <2>; 133 device_type = "pci"; 134 ranges= <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>; 135 enetc0: pci@0,0 { 136 reg = <0x000000 0 0 0 0>; 137 status = "disabled"; 138 }; 139 enetc1: pci@0,1 { 140 reg = <0x000100 0 0 0 0>; 141 status = "disabled"; 142 }; 143 enetc2: pci@0,2 { 144 reg = <0x000200 0 0 0 0>; 145 status = "okay"; 146 phy-mode = "internal"; 147 }; 148 mdio0: pci@0,3 { 149 #address-cells=<0>; 150 #size-cells=<1>; 151 reg = <0x000300 0 0 0 0>; 152 status = "disabled"; 153 }; 154 155 mscc_felix: pci@0,5 { 156 reg = <0x000500 0 0 0 0>; 157 status = "disabled"; 158 159 ports { 160 #address-cells = <1>; 161 #size-cells = <0>; 162 163 mscc_felix_port0: port@0 { 164 reg = <0>; 165 status = "disabled"; 166 }; 167 168 mscc_felix_port1: port@1 { 169 reg = <1>; 170 status = "disabled"; 171 }; 172 173 mscc_felix_port2: port@2 { 174 reg = <2>; 175 status = "disabled"; 176 }; 177 178 mscc_felix_port3: port@3 { 179 reg = <3>; 180 status = "disabled"; 181 }; 182 183 mscc_felix_port4: port@4 { 184 reg = <4>; 185 phy-mode = "internal"; 186 status = "disabled"; 187 188 fixed-link { 189 speed = <2500>; 190 full-duplex; 191 }; 192 }; 193 194 mscc_felix_port5: port@5 { 195 reg = <5>; 196 phy-mode = "internal"; 197 status = "disabled"; 198 199 fixed-link { 200 speed = <1000>; 201 full-duplex; 202 }; 203 204 }; 205 }; 206 }; 207 208 enetc6: pci@0,6 { 209 reg = <0x000600 0 0 0 0>; 210 status = "disabled"; 211 phy-mode = "internal"; 212 }; 213 }; 214 215 i2c0: i2c@2000000 { 216 compatible = "fsl,vf610-i2c"; 217 #address-cells = <1>; 218 #size-cells = <0>; 219 reg = <0x0 0x2000000 0x0 0x10000>; 220 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 221 clock-names = "i2c"; 222 clocks = <&clockgen 4 0>; 223 status = "disabled"; 224 }; 225 226 i2c1: i2c@2010000 { 227 compatible = "fsl,vf610-i2c"; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 reg = <0x0 0x2010000 0x0 0x10000>; 231 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 232 clock-names = "i2c"; 233 clocks = <&clockgen 4 0>; 234 status = "disabled"; 235 }; 236 237 i2c2: i2c@2020000 { 238 compatible = "fsl,vf610-i2c"; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 reg = <0x0 0x2020000 0x0 0x10000>; 242 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 243 clock-names = "i2c"; 244 clocks = <&clockgen 4 0>; 245 status = "disabled"; 246 }; 247 248 i2c3: i2c@2030000 { 249 compatible = "fsl,vf610-i2c"; 250 #address-cells = <1>; 251 #size-cells = <0>; 252 reg = <0x0 0x2030000 0x0 0x10000>; 253 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 254 clock-names = "i2c"; 255 clocks = <&clockgen 4 0>; 256 status = "disabled"; 257 }; 258 259 i2c4: i2c@2040000 { 260 compatible = "fsl,vf610-i2c"; 261 #address-cells = <1>; 262 #size-cells = <0>; 263 reg = <0x0 0x2040000 0x0 0x10000>; 264 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 265 clock-names = "i2c"; 266 clocks = <&clockgen 4 0>; 267 status = "disabled"; 268 }; 269 270 i2c5: i2c@2050000 { 271 compatible = "fsl,vf610-i2c"; 272 #address-cells = <1>; 273 #size-cells = <0>; 274 reg = <0x0 0x2050000 0x0 0x10000>; 275 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 276 clock-names = "i2c"; 277 clocks = <&clockgen 4 0>; 278 status = "disabled"; 279 }; 280 281 i2c6: i2c@2060000 { 282 compatible = "fsl,vf610-i2c"; 283 #address-cells = <1>; 284 #size-cells = <0>; 285 reg = <0x0 0x2060000 0x0 0x10000>; 286 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 287 clock-names = "i2c"; 288 clocks = <&clockgen 4 0>; 289 status = "disabled"; 290 }; 291 292 i2c7: i2c@2070000 { 293 compatible = "fsl,vf610-i2c"; 294 #address-cells = <1>; 295 #size-cells = <0>; 296 reg = <0x0 0x2070000 0x0 0x10000>; 297 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 298 clock-names = "i2c"; 299 clocks = <&clockgen 4 0>; 300 status = "disabled"; 301 }; 302 303 lpuart0: serial@2260000 { 304 compatible = "fsl,ls1021a-lpuart"; 305 reg = <0x0 0x2260000 0x0 0x1000>; 306 interrupts = <0 232 0x4>; 307 clocks = <&sysclk>; 308 clock-names = "ipg"; 309 little-endian; 310 status = "disabled"; 311 }; 312 313 lpuart1: serial@2270000 { 314 compatible = "fsl,ls1021a-lpuart"; 315 reg = <0x0 0x2270000 0x0 0x1000>; 316 interrupts = <0 233 0x4>; 317 clocks = <&sysclk>; 318 clock-names = "ipg"; 319 little-endian; 320 status = "disabled"; 321 }; 322 323 lpuart2: serial@2280000 { 324 compatible = "fsl,ls1021a-lpuart"; 325 reg = <0x0 0x2280000 0x0 0x1000>; 326 interrupts = <0 234 0x4>; 327 clocks = <&sysclk>; 328 clock-names = "ipg"; 329 little-endian; 330 status = "disabled"; 331 }; 332 333 lpuart3: serial@2290000 { 334 compatible = "fsl,ls1021a-lpuart"; 335 reg = <0x0 0x2290000 0x0 0x1000>; 336 interrupts = <0 235 0x4>; 337 clocks = <&sysclk>; 338 clock-names = "ipg"; 339 little-endian; 340 status = "disabled"; 341 }; 342 343 lpuart4: serial@22a0000 { 344 compatible = "fsl,ls1021a-lpuart"; 345 reg = <0x0 0x22a0000 0x0 0x1000>; 346 interrupts = <0 236 0x4>; 347 clocks = <&sysclk>; 348 clock-names = "ipg"; 349 little-endian; 350 status = "disabled"; 351 }; 352 353 lpuart5: serial@22b0000 { 354 compatible = "fsl,ls1021a-lpuart"; 355 reg = <0x0 0x22b0000 0x0 0x1000>; 356 interrupts = <0 237 0x4>; 357 clocks = <&sysclk>; 358 clock-names = "ipg"; 359 little-endian; 360 status = "disabled"; 361 }; 362 363 usb1: usb3@3100000 { 364 compatible = "fsl,layerscape-dwc3"; 365 reg = <0x0 0x3100000 0x0 0x10000>; 366 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 367 dr_mode = "host"; 368 status = "disabled"; 369 }; 370 371 usb2: usb3@3110000 { 372 compatible = "fsl,layerscape-dwc3"; 373 reg = <0x0 0x3110000 0x0 0x10000>; 374 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 375 dr_mode = "host"; 376 status = "disabled"; 377 }; 378 379 dspi0: dspi@2100000 { 380 compatible = "fsl,vf610-dspi"; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 reg = <0x0 0x2100000 0x0 0x10000>; 384 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 385 clock-names = "dspi"; 386 clocks = <&clockgen 4 0>; 387 num-cs = <5>; 388 litte-endian; 389 status = "disabled"; 390 }; 391 392 dspi1: dspi@2110000 { 393 compatible = "fsl,vf610-dspi"; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 reg = <0x0 0x2110000 0x0 0x10000>; 397 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 398 clock-names = "dspi"; 399 clocks = <&clockgen 4 0>; 400 num-cs = <5>; 401 little-endian; 402 status = "disabled"; 403 }; 404 405 dspi2: dspi@2120000 { 406 compatible = "fsl,vf610-dspi"; 407 #address-cells = <1>; 408 #size-cells = <0>; 409 reg = <0x0 0x2120000 0x0 0x10000>; 410 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 411 clock-names = "dspi"; 412 clocks = <&clockgen 4 0>; 413 num-cs = <5>; 414 little-endian; 415 status = "disabled"; 416 }; 417 418 esdhc0: esdhc@2140000 { 419 compatible = "fsl,esdhc"; 420 reg = <0x0 0x2140000 0x0 0x10000>; 421 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 422 big-endian; 423 bus-width = <4>; 424 status = "disabled"; 425 }; 426 427 esdhc1: esdhc@2150000 { 428 compatible = "fsl,esdhc"; 429 reg = <0x0 0x2150000 0x0 0x10000>; 430 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 431 big-endian; 432 non-removable; 433 bus-width = <4>; 434 status = "disabled"; 435 }; 436 437 gpio0: gpio@2300000 { 438 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 439 reg = <0x0 0x2300000 0x0 0x10000>; 440 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 441 gpio-controller; 442 #gpio-cells = <2>; 443 interrupt-controller; 444 #interrupt-cells = <2>; 445 little-endian; 446 }; 447 448 gpio1: gpio@2310000 { 449 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 450 reg = <0x0 0x2310000 0x0 0x10000>; 451 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 452 gpio-controller; 453 #gpio-cells = <2>; 454 interrupt-controller; 455 #interrupt-cells = <2>; 456 little-endian; 457 }; 458 459 gpio2: gpio@2320000 { 460 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 461 reg = <0x0 0x2320000 0x0 0x10000>; 462 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 463 gpio-controller; 464 #gpio-cells = <2>; 465 interrupt-controller; 466 #interrupt-cells = <2>; 467 little-endian; 468 }; 469 470 sata: sata@3200000 { 471 compatible = "fsl,ls1028a-ahci"; 472 reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ 473 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/ 474 reg-names = "sata-base", "ecc-addr"; 475 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 476 status = "disabled"; 477 }; 478 479 cluster1_core0_watchdog: wdt@c000000 { 480 compatible = "arm,sp805-wdt"; 481 reg = <0x0 0xc000000 0x0 0x1000>; 482 }; 483}; 484