1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 4 * 5 * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. 6 */ 7 8 #ifndef __ASM_ARCH_MX35_H 9 #define __ASM_ARCH_MX35_H 10 11 #define ARCH_MXC 12 13 /* 14 * IRAM 15 */ 16 #define IRAM_BASE_ADDR 0x10000000 /* internal ram */ 17 #define IRAM_SIZE 0x00020000 /* 128 KB */ 18 19 #define LOW_LEVEL_SRAM_STACK 0x1001E000 20 21 /* 22 * AIPS 1 23 */ 24 #define AIPS1_BASE_ADDR 0x43F00000 25 #define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR 26 #define MAX_BASE_ADDR 0x43F04000 27 #define EVTMON_BASE_ADDR 0x43F08000 28 #define CLKCTL_BASE_ADDR 0x43F0C000 29 #define I2C1_BASE_ADDR 0x43F80000 30 #define I2C3_BASE_ADDR 0x43F84000 31 #define ATA_BASE_ADDR 0x43F8C000 32 #define UART1_BASE 0x43F90000 33 #define UART2_BASE 0x43F94000 34 #define I2C2_BASE_ADDR 0x43F98000 35 #define CSPI1_BASE_ADDR 0x43FA4000 36 #define IOMUXC_BASE_ADDR 0x43FAC000 37 38 /* 39 * SPBA 40 */ 41 #define SPBA_BASE_ADDR 0x50000000 42 #define UART3_BASE 0x5000C000 43 #define CSPI2_BASE_ADDR 0x50010000 44 #define ATA_DMA_BASE_ADDR 0x50020000 45 #define FEC_BASE_ADDR 0x50038000 46 #define SPBA_CTRL_BASE_ADDR 0x5003C000 47 48 /* 49 * AIPS 2 50 */ 51 #define AIPS2_BASE_ADDR 0x53F00000 52 #define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR 53 #define CCM_BASE_ADDR 0x53F80000 54 #define GPT1_BASE_ADDR 0x53F90000 55 #define EPIT1_BASE_ADDR 0x53F94000 56 #define EPIT2_BASE_ADDR 0x53F98000 57 #define GPIO3_BASE_ADDR 0x53FA4000 58 #define MMC_SDHC1_BASE_ADDR 0x53FB4000 59 #define MMC_SDHC2_BASE_ADDR 0x53FB8000 60 #define MMC_SDHC3_BASE_ADDR 0x53FBC000 61 #define IPU_CTRL_BASE_ADDR 0x53FC0000 62 #define GPIO1_BASE_ADDR 0x53FCC000 63 #define GPIO2_BASE_ADDR 0x53FD0000 64 #define SDMA_BASE_ADDR 0x53FD4000 65 #define RTC_BASE_ADDR 0x53FD8000 66 #define WDOG1_BASE_ADDR 0x53FDC000 67 #define PWM_BASE_ADDR 0x53FE0000 68 #define RTIC_BASE_ADDR 0x53FEC000 69 #define IIM_BASE_ADDR 0x53FF0000 70 #define IMX_USB_BASE 0x53FF4000 71 #define IMX_USB_PORT_OFFSET 0x400 72 73 #define IMX_CCM_BASE CCM_BASE_ADDR 74 75 /* 76 * ROMPATCH and AVIC 77 */ 78 #define ROMPATCH_BASE_ADDR 0x60000000 79 #define AVIC_BASE_ADDR 0x68000000 80 81 /* 82 * NAND, SDRAM, WEIM, M3IF, EMI controllers 83 */ 84 #define EXT_MEM_CTRL_BASE 0xB8000000 85 #define ESDCTL_BASE_ADDR 0xB8001000 86 #define WEIM_BASE_ADDR 0xB8002000 87 #define WEIM_CTRL_CS0 WEIM_BASE_ADDR 88 #define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10) 89 #define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20) 90 #define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30) 91 #define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40) 92 #define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50) 93 #define M3IF_BASE_ADDR 0xB8003000 94 #define EMI_BASE_ADDR 0xB8004000 95 96 #define NFC_BASE_ADDR 0xBB000000 97 98 /* 99 * Memory regions and CS 100 */ 101 #define IPU_MEM_BASE_ADDR 0x70000000 102 #define CSD0_BASE_ADDR 0x80000000 103 #define CSD1_BASE_ADDR 0x90000000 104 #define CS0_BASE_ADDR 0xA0000000 105 #define CS1_BASE_ADDR 0xA8000000 106 #define CS2_BASE_ADDR 0xB0000000 107 #define CS3_BASE_ADDR 0xB2000000 108 #define CS4_BASE_ADDR 0xB4000000 109 #define CS5_BASE_ADDR 0xB6000000 110 111 /* 112 * IRQ Controller Register Definitions. 113 */ 114 #define AVIC_NIMASK 0x04 115 #define AVIC_INTTYPEH 0x18 116 #define AVIC_INTTYPEL 0x1C 117 118 /* L210 */ 119 #define L2CC_BASE_ADDR 0x30000000 120 #define L2_CACHE_LINE_SIZE 32 121 #define L2_CACHE_CTL_REG 0x100 122 #define L2_CACHE_AUX_CTL_REG 0x104 123 #define L2_CACHE_SYNC_REG 0x730 124 #define L2_CACHE_INV_LINE_REG 0x770 125 #define L2_CACHE_INV_WAY_REG 0x77C 126 #define L2_CACHE_CLEAN_LINE_REG 0x7B0 127 #define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0 128 #define L2_CACHE_DBG_CTL_REG 0xF40 129 130 #define CLKMODE_AUTO 0 131 #define CLKMODE_CONSUMER 1 132 133 #define PLL_PD(x) (((x) & 0xf) << 26) 134 #define PLL_MFD(x) (((x) & 0x3ff) << 16) 135 #define PLL_MFI(x) (((x) & 0xf) << 10) 136 #define PLL_MFN(x) (((x) & 0x3ff) << 0) 137 138 #define _PLL_BRM(x) ((x) << 31) 139 #define _PLL_PD(x) (((x) - 1) << 26) 140 #define _PLL_MFD(x) (((x) - 1) << 16) 141 #define _PLL_MFI(x) ((x) << 10) 142 #define _PLL_MFN(x) (x) 143 #define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \ 144 (_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\ 145 _PLL_MFN(mfn)) 146 147 #define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1) 148 #define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5) 149 #define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1) 150 151 #define CSCR_U(x) (WEIM_CTRL_CS#x + 0) 152 #define CSCR_L(x) (WEIM_CTRL_CS#x + 4) 153 #define CSCR_A(x) (WEIM_CTRL_CS#x + 8) 154 155 #define IIM_SREV 0x24 156 #define ROMPATCH_REV 0x40 157 158 #define IPU_CONF IPU_CTRL_BASE_ADDR 159 160 #define IPU_CONF_PXL_ENDIAN (1<<8) 161 #define IPU_CONF_DU_EN (1<<7) 162 #define IPU_CONF_DI_EN (1<<6) 163 #define IPU_CONF_ADC_EN (1<<5) 164 #define IPU_CONF_SDC_EN (1<<4) 165 #define IPU_CONF_PF_EN (1<<3) 166 #define IPU_CONF_ROT_EN (1<<2) 167 #define IPU_CONF_IC_EN (1<<1) 168 #define IPU_CONF_CSI_EN (1<<0) 169 170 /* 171 * CSPI register definitions 172 */ 173 #define MXC_SPI_BASE_ADDRESSES \ 174 0x43fa4000, \ 175 0x50010000, 176 177 #define GPIO_PORT_NUM 3 178 #define GPIO_NUM_PIN 32 179 180 #define CHIP_REV_1_0 0x10 181 #define CHIP_REV_2_0 0x20 182 183 #define BOARD_REV_1_0 0x0 184 #define BOARD_REV_2_0 0x1 185 186 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 187 #include <asm/types.h> 188 189 /* Clock Control Module (CCM) registers */ 190 struct ccm_regs { 191 u32 ccmr; /* Control */ 192 u32 pdr0; /* Post divider 0 */ 193 u32 pdr1; /* Post divider 1 */ 194 u32 pdr2; /* Post divider 2 */ 195 u32 pdr3; /* Post divider 3 */ 196 u32 pdr4; /* Post divider 4 */ 197 u32 rcsr; /* CCM Status */ 198 u32 mpctl; /* Core PLL Control */ 199 u32 ppctl; /* Peripheral PLL Control */ 200 u32 acmr; /* Audio clock mux */ 201 u32 cosr; /* Clock out source */ 202 u32 cgr0; /* Clock Gating Control 0 */ 203 u32 cgr1; /* Clock Gating Control 1 */ 204 u32 cgr2; /* Clock Gating Control 2 */ 205 u32 cgr3; /* Clock Gating Control 3 */ 206 u32 reserved; 207 u32 dcvr0; /* DPTC Comparator 0 */ 208 u32 dcvr1; /* DPTC Comparator 0 */ 209 u32 dcvr2; /* DPTC Comparator 0 */ 210 u32 dcvr3; /* DPTC Comparator 0 */ 211 u32 ltr0; /* Load Tracking 0 */ 212 u32 ltr1; /* Load Tracking 1 */ 213 u32 ltr2; /* Load Tracking 2 */ 214 u32 ltr3; /* Load Tracking 3 */ 215 u32 ltbr0; /* Load Tracking Buffer 0 */ 216 }; 217 218 /* IIM control registers */ 219 struct iim_regs { 220 u32 iim_stat; 221 u32 iim_statm; 222 u32 iim_err; 223 u32 iim_emask; 224 u32 iim_fctl; 225 u32 iim_ua; 226 u32 iim_la; 227 u32 iim_sdat; 228 u32 iim_prev; 229 u32 iim_srev; 230 u32 iim_prg_p; 231 u32 iim_scs0; 232 u32 iim_scs1; 233 u32 iim_scs2; 234 u32 iim_scs3; 235 u32 res1[0x1f1]; 236 struct fuse_bank { 237 u32 fuse_regs[0x20]; 238 u32 fuse_rsvd[0xe0]; 239 } bank[3]; 240 }; 241 242 struct fuse_bank0_regs { 243 u32 fuse0_7[8]; 244 u32 uid[8]; 245 u32 fuse16_31[0x10]; 246 }; 247 248 struct fuse_bank1_regs { 249 u32 fuse0_21[0x16]; 250 u32 usr; 251 u32 fuse23_31[9]; 252 }; 253 254 /* General Purpose Timer (GPT) registers */ 255 struct gpt_regs { 256 u32 ctrl; /* control */ 257 u32 pre; /* prescaler */ 258 u32 stat; /* status */ 259 u32 intr; /* interrupt */ 260 u32 cmp[3]; /* output compare 1-3 */ 261 u32 capt[2]; /* input capture 1-2 */ 262 u32 counter; /* counter */ 263 }; 264 265 struct esdc_regs { 266 u32 esdctl0; 267 u32 esdcfg0; 268 u32 esdctl1; 269 u32 esdcfg1; 270 u32 esdmisc; 271 u32 reserved[4]; 272 u32 esdcdly[5]; 273 u32 esdcdlyl; 274 }; 275 276 #define ESDC_MISC_RST (1 << 1) 277 #define ESDC_MISC_MDDR_EN (1 << 2) 278 #define ESDC_MISC_MDDR_DL_RST (1 << 3) 279 #define ESDC_MISC_DDR_EN (1 << 8) 280 #define ESDC_MISC_DDR2_EN (1 << 9) 281 282 /* Multi-Layer AHB Crossbar Switch (MAX) registers */ 283 struct max_regs { 284 u32 mpr0; 285 u32 pad00[3]; 286 u32 sgpcr0; 287 u32 pad01[59]; 288 u32 mpr1; 289 u32 pad02[3]; 290 u32 sgpcr1; 291 u32 pad03[59]; 292 u32 mpr2; 293 u32 pad04[3]; 294 u32 sgpcr2; 295 u32 pad05[59]; 296 u32 mpr3; 297 u32 pad06[3]; 298 u32 sgpcr3; 299 u32 pad07[59]; 300 u32 mpr4; 301 u32 pad08[3]; 302 u32 sgpcr4; 303 u32 pad09[251]; 304 u32 mgpcr0; 305 u32 pad10[63]; 306 u32 mgpcr1; 307 u32 pad11[63]; 308 u32 mgpcr2; 309 u32 pad12[63]; 310 u32 mgpcr3; 311 u32 pad13[63]; 312 u32 mgpcr4; 313 u32 pad14[63]; 314 u32 mgpcr5; 315 }; 316 317 /* AHB <-> IP-Bus Interface (AIPS) */ 318 struct aips_regs { 319 u32 mpr_0_7; 320 u32 mpr_8_15; 321 u32 pad0[6]; 322 u32 pacr_0_7; 323 u32 pacr_8_15; 324 u32 pacr_16_23; 325 u32 pacr_24_31; 326 u32 pad1[4]; 327 u32 opacr_0_7; 328 u32 opacr_8_15; 329 u32 opacr_16_23; 330 u32 opacr_24_31; 331 u32 opacr_32_39; 332 }; 333 334 /* 335 * NFMS bit in RCSR register for pagesize of nandflash 336 */ 337 #define NFMS_BIT 8 338 #define NFMS_NF_DWIDTH 14 339 #define NFMS_NF_PG_SZ 8 340 341 #define CCM_RCSR_NF_16BIT_SEL (1 << 14) 342 343 #endif 344 345 /* 346 * Generic timer support 347 */ 348 #ifdef CONFIG_MX35_CLK32 349 #define CONFIG_SYS_TIMER_RATE CONFIG_MX35_CLK32 350 #else 351 #define CONFIG_SYS_TIMER_RATE 32768 352 #endif 353 354 #define CONFIG_SYS_TIMER_COUNTER (GPT1_BASE_ADDR+36) 355 356 #endif /* __ASM_ARCH_MX35_H */ 357