1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2020 Marvell International Ltd. 4 */ 5 6 /* 7 * Header file containing the ABI with the bootloader. 8 */ 9 10 #ifndef __CVMX_BOOTINFO_H__ 11 #define __CVMX_BOOTINFO_H__ 12 13 #include "cvmx-coremask.h" 14 15 /* 16 * Current major and minor versions of the CVMX bootinfo block that is 17 * passed from the bootloader to the application. This is versioned 18 * so that applications can properly handle multiple bootloader 19 * versions. 20 */ 21 #define CVMX_BOOTINFO_MAJ_VER 1 22 #define CVMX_BOOTINFO_MIN_VER 4 23 24 #if (CVMX_BOOTINFO_MAJ_VER == 1) 25 #define CVMX_BOOTINFO_OCTEON_SERIAL_LEN 20 26 /* 27 * This structure is populated by the bootloader. For binary 28 * compatibility the only changes that should be made are 29 * adding members to the end of the structure, and the minor 30 * version should be incremented at that time. 31 * If an incompatible change is made, the major version 32 * must be incremented, and the minor version should be reset 33 * to 0. 34 */ 35 struct cvmx_bootinfo { 36 u32 major_version; 37 u32 minor_version; 38 39 u64 stack_top; 40 u64 heap_base; 41 u64 heap_end; 42 u64 desc_vaddr; 43 44 u32 exception_base_addr; 45 u32 stack_size; 46 u32 flags; 47 u32 core_mask; 48 /* DRAM size in megabytes */ 49 u32 dram_size; 50 /* physical address of free memory descriptor block*/ 51 u32 phy_mem_desc_addr; 52 /* used to pass flags from app to debugger */ 53 u32 debugger_flags_base_addr; 54 55 /* CPU clock speed, in hz */ 56 u32 eclock_hz; 57 58 /* DRAM clock speed, in hz */ 59 u32 dclock_hz; 60 61 u32 reserved0; 62 u16 board_type; 63 u8 board_rev_major; 64 u8 board_rev_minor; 65 u16 reserved1; 66 u8 reserved2; 67 u8 reserved3; 68 char board_serial_number[CVMX_BOOTINFO_OCTEON_SERIAL_LEN]; 69 u8 mac_addr_base[6]; 70 u8 mac_addr_count; 71 #if (CVMX_BOOTINFO_MIN_VER >= 1) 72 /* 73 * Several boards support compact flash on the Octeon boot 74 * bus. The CF memory spaces may be mapped to different 75 * addresses on different boards. These are the physical 76 * addresses, so care must be taken to use the correct 77 * XKPHYS/KSEG0 addressing depending on the application's 78 * ABI. These values will be 0 if CF is not present. 79 */ 80 u64 compact_flash_common_base_addr; 81 u64 compact_flash_attribute_base_addr; 82 /* 83 * Base address of the LED display (as on EBT3000 board) 84 * This will be 0 if LED display not present. 85 */ 86 u64 led_display_base_addr; 87 #endif 88 #if (CVMX_BOOTINFO_MIN_VER >= 2) 89 /* DFA reference clock in hz (if applicable)*/ 90 u32 dfa_ref_clock_hz; 91 92 /* 93 * flags indicating various configuration options. These 94 * flags supercede the 'flags' variable and should be used 95 * instead if available. 96 */ 97 u32 config_flags; 98 #endif 99 #if (CVMX_BOOTINFO_MIN_VER >= 3) 100 /* 101 * Address of the OF Flattened Device Tree structure 102 * describing the board. 103 */ 104 u64 fdt_addr; 105 #endif 106 #if (CVMX_BOOTINFO_MIN_VER >= 4) 107 /* 108 * Coremask used for processors with more than 32 cores 109 * or with OCI. This replaces core_mask. 110 */ 111 struct cvmx_coremask ext_core_mask; 112 #endif 113 }; 114 115 #define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST (1ull << 0) 116 #define CVMX_BOOTINFO_CFG_FLAG_PCI_TARGET (1ull << 1) 117 #define CVMX_BOOTINFO_CFG_FLAG_DEBUG (1ull << 2) 118 #define CVMX_BOOTINFO_CFG_FLAG_NO_MAGIC (1ull << 3) 119 /* 120 * This flag is set if the TLB mappings are not contained in the 121 * 0x10000000 - 0x20000000 boot bus region. 122 */ 123 #define CVMX_BOOTINFO_CFG_FLAG_OVERSIZE_TLB_MAPPING (1ull << 4) 124 #define CVMX_BOOTINFO_CFG_FLAG_BREAK (1ull << 5) 125 126 #endif /* (CVMX_BOOTINFO_MAJ_VER == 1) */ 127 128 #endif /* __CVMX_BOOTINFO_H__ */ 129