1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (C) 2020 Marvell International Ltd.
4 *
5 * Configuration and status register (CSR) type definitions for
6 * Octeon pemx.
7 */
8
9 #ifndef __CVMX_PEMX_DEFS_H__
10 #define __CVMX_PEMX_DEFS_H__
11
CVMX_PEMX_BAR1_INDEXX(unsigned long offset,unsigned long block_id)12 static inline u64 CVMX_PEMX_BAR1_INDEXX(unsigned long offset, unsigned long block_id)
13 {
14 switch (cvmx_get_octeon_family()) {
15 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
16 return 0x00011800C0000100ull + ((offset) + (block_id) * 0x200000ull) * 8;
17 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
18 return 0x00011800C0000100ull + ((offset) + (block_id) * 0x200000ull) * 8;
19 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
20 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
21 return 0x00011800C0000100ull + ((offset) + (block_id) * 0x200000ull) * 8;
22 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
23 return 0x00011800C0000100ull + ((offset) + (block_id) * 0x200000ull) * 8;
24 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
25 return 0x00011800C0000100ull + ((offset) + (block_id) * 0x200000ull) * 8;
26 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
27 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
28 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
29 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
30 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
31 return 0x00011800C00000A8ull + ((offset) + (block_id) * 0x200000ull) * 8;
32 }
33 return 0x00011800C0000100ull + ((offset) + (block_id) * 0x200000ull) * 8;
34 }
35
CVMX_PEMX_BAR2_MASK(unsigned long offset)36 static inline u64 CVMX_PEMX_BAR2_MASK(unsigned long offset)
37 {
38 switch (cvmx_get_octeon_family()) {
39 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
40 return 0x00011800C00000B0ull + (offset) * 0x1000000ull;
41 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
42 return 0x00011800C00000B0ull + (offset) * 0x1000000ull;
43 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
44 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
45 return 0x00011800C00000B0ull + (offset) * 0x1000000ull;
46 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
47 return 0x00011800C00000B0ull + (offset) * 0x1000000ull;
48 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
49 return 0x00011800C10000B0ull + (offset) * 0x1000000ull - 16777216 * 1;
50 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
51 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
52 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
53 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
54 return 0x00011800C0000130ull + (offset) * 0x1000000ull;
55 }
56 return 0x00011800C00000B0ull + (offset) * 0x1000000ull;
57 }
58
CVMX_PEMX_BAR_CTL(unsigned long offset)59 static inline u64 CVMX_PEMX_BAR_CTL(unsigned long offset)
60 {
61 switch (cvmx_get_octeon_family()) {
62 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
63 return 0x00011800C00000A8ull + (offset) * 0x1000000ull;
64 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
65 return 0x00011800C00000A8ull + (offset) * 0x1000000ull;
66 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
67 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
68 return 0x00011800C00000A8ull + (offset) * 0x1000000ull;
69 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
70 return 0x00011800C00000A8ull + (offset) * 0x1000000ull;
71 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
72 return 0x00011800C10000A8ull + (offset) * 0x1000000ull - 16777216 * 1;
73 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
74 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
75 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
76 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
77 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
78 return 0x00011800C0000128ull + (offset) * 0x1000000ull;
79 }
80 return 0x00011800C00000A8ull + (offset) * 0x1000000ull;
81 }
82
CVMX_PEMX_BIST_STATUS(unsigned long offset)83 static inline u64 CVMX_PEMX_BIST_STATUS(unsigned long offset)
84 {
85 switch (cvmx_get_octeon_family()) {
86 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
87 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
88 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
89 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
90 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
91 return 0x00011800C0000018ull + (offset) * 0x1000000ull;
92 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
93 return 0x00011800C0000018ull + (offset) * 0x1000000ull;
94 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
95 return 0x00011800C0000440ull + (offset) * 0x1000000ull;
96 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
97 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
98 return 0x00011800C0000440ull + (offset) * 0x1000000ull;
99 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
100 return 0x00011800C0000440ull + (offset) * 0x1000000ull;
101 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
102 return 0x00011800C1000440ull + (offset) * 0x1000000ull - 16777216 * 1;
103 }
104 return 0x00011800C0000440ull + (offset) * 0x1000000ull;
105 }
106
CVMX_PEMX_BIST_STATUS2(unsigned long offset)107 static inline u64 CVMX_PEMX_BIST_STATUS2(unsigned long offset)
108 {
109 switch (cvmx_get_octeon_family()) {
110 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
111 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
112 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
113 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
114 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
115 return 0x00011800C0000420ull + (offset) * 0x1000000ull;
116 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
117 return 0x00011800C0000440ull + (offset) * 0x1000000ull;
118 }
119 return 0x00011800C0000420ull + (offset) * 0x1000000ull;
120 }
121
122 #define CVMX_PEMX_CFG(offset) (0x00011800C0000410ull + ((offset) & 3) * 0x1000000ull)
123 #define CVMX_PEMX_CFG_RD(offset) (0x00011800C0000030ull + ((offset) & 3) * 0x1000000ull)
124 #define CVMX_PEMX_CFG_WR(offset) (0x00011800C0000028ull + ((offset) & 3) * 0x1000000ull)
125 #define CVMX_PEMX_CLK_EN(offset) (0x00011800C0000400ull + ((offset) & 3) * 0x1000000ull)
126 #define CVMX_PEMX_CPL_LUT_VALID(offset) (0x00011800C0000098ull + ((offset) & 3) * 0x1000000ull)
127 #define CVMX_PEMX_CTL_STATUS(offset) (0x00011800C0000000ull + ((offset) & 3) * 0x1000000ull)
128 #define CVMX_PEMX_CTL_STATUS2(offset) (0x00011800C0000008ull + ((offset) & 3) * 0x1000000ull)
CVMX_PEMX_DBG_INFO(unsigned long offset)129 static inline u64 CVMX_PEMX_DBG_INFO(unsigned long offset)
130 {
131 switch (cvmx_get_octeon_family()) {
132 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
133 return 0x00011800C00000D0ull + (offset) * 0x1000000ull;
134 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
135 return 0x00011800C00000D0ull + (offset) * 0x1000000ull;
136 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
137 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
138 return 0x00011800C00000D0ull + (offset) * 0x1000000ull;
139 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
140 return 0x00011800C00000D0ull + (offset) * 0x1000000ull;
141 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
142 return 0x00011800C10000D0ull + (offset) * 0x1000000ull - 16777216 * 1;
143 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
144 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
145 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
146 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
147 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
148 return 0x00011800C0000008ull + (offset) * 0x1000000ull;
149 }
150 return 0x00011800C00000D0ull + (offset) * 0x1000000ull;
151 }
152
153 #define CVMX_PEMX_DBG_INFO_EN(offset) (0x00011800C00000A0ull + ((offset) & 3) * 0x1000000ull)
154 #define CVMX_PEMX_DIAG_STATUS(offset) (0x00011800C0000020ull + ((offset) & 3) * 0x1000000ull)
CVMX_PEMX_ECC_ENA(unsigned long offset)155 static inline u64 CVMX_PEMX_ECC_ENA(unsigned long offset)
156 {
157 switch (cvmx_get_octeon_family()) {
158 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
159 return 0x00011800C0000448ull + (offset) * 0x1000000ull;
160 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
161 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
162 return 0x00011800C0000448ull + (offset) * 0x1000000ull;
163 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
164 return 0x00011800C0000448ull + (offset) * 0x1000000ull;
165 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
166 return 0x00011800C1000448ull + (offset) * 0x1000000ull - 16777216 * 1;
167 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
168 return 0x00011800C00000C0ull + (offset) * 0x1000000ull;
169 }
170 return 0x00011800C0000448ull + (offset) * 0x1000000ull;
171 }
172
CVMX_PEMX_ECC_SYND_CTRL(unsigned long offset)173 static inline u64 CVMX_PEMX_ECC_SYND_CTRL(unsigned long offset)
174 {
175 switch (cvmx_get_octeon_family()) {
176 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
177 return 0x00011800C0000450ull + (offset) * 0x1000000ull;
178 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
179 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
180 return 0x00011800C0000450ull + (offset) * 0x1000000ull;
181 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
182 return 0x00011800C0000450ull + (offset) * 0x1000000ull;
183 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
184 return 0x00011800C1000450ull + (offset) * 0x1000000ull - 16777216 * 1;
185 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
186 return 0x00011800C00000C8ull + (offset) * 0x1000000ull;
187 }
188 return 0x00011800C0000450ull + (offset) * 0x1000000ull;
189 }
190
191 #define CVMX_PEMX_ECO(offset) (0x00011800C0000010ull + ((offset) & 3) * 0x1000000ull)
192 #define CVMX_PEMX_FLR_GLBLCNT_CTL(offset) (0x00011800C0000210ull + ((offset) & 3) * 0x1000000ull)
193 #define CVMX_PEMX_FLR_PF0_VF_STOPREQ(offset) (0x00011800C0000220ull + ((offset) & 3) * 0x1000000ull)
194 #define CVMX_PEMX_FLR_PF_STOPREQ(offset) (0x00011800C0000218ull + ((offset) & 3) * 0x1000000ull)
195 #define CVMX_PEMX_FLR_STOPREQ_CTL(offset) (0x00011800C0000238ull + ((offset) & 3) * 0x1000000ull)
196 #define CVMX_PEMX_FLR_ZOMBIE_CTL(offset) (0x00011800C0000230ull + ((offset) & 3) * 0x1000000ull)
CVMX_PEMX_INB_READ_CREDITS(unsigned long offset)197 static inline u64 CVMX_PEMX_INB_READ_CREDITS(unsigned long offset)
198 {
199 switch (cvmx_get_octeon_family()) {
200 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
201 return 0x00011800C00000B8ull + (offset) * 0x1000000ull;
202 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
203 return 0x00011800C00000B8ull + (offset) * 0x1000000ull;
204 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
205 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
206 return 0x00011800C00000B8ull + (offset) * 0x1000000ull;
207 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
208 return 0x00011800C00000B8ull + (offset) * 0x1000000ull;
209 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
210 return 0x00011800C10000B8ull + (offset) * 0x1000000ull - 16777216 * 1;
211 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
212 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
213 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
214 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
215 return 0x00011800C0000138ull + (offset) * 0x1000000ull;
216 }
217 return 0x00011800C00000B8ull + (offset) * 0x1000000ull;
218 }
219
CVMX_PEMX_INT_ENB(unsigned long offset)220 static inline u64 CVMX_PEMX_INT_ENB(unsigned long offset)
221 {
222 switch (cvmx_get_octeon_family()) {
223 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
224 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
225 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
226 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
227 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
228 return 0x00011800C0000410ull + (offset) * 0x1000000ull;
229 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
230 return 0x00011800C0000430ull + (offset) * 0x1000000ull;
231 }
232 return 0x00011800C0000410ull + (offset) * 0x1000000ull;
233 }
234
CVMX_PEMX_INT_ENB_INT(unsigned long offset)235 static inline u64 CVMX_PEMX_INT_ENB_INT(unsigned long offset)
236 {
237 switch (cvmx_get_octeon_family()) {
238 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
239 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
240 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
241 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
242 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
243 return 0x00011800C0000418ull + (offset) * 0x1000000ull;
244 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
245 return 0x00011800C0000438ull + (offset) * 0x1000000ull;
246 }
247 return 0x00011800C0000418ull + (offset) * 0x1000000ull;
248 }
249
CVMX_PEMX_INT_SUM(unsigned long offset)250 static inline u64 CVMX_PEMX_INT_SUM(unsigned long offset)
251 {
252 switch (cvmx_get_octeon_family()) {
253 case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
254 return 0x00011800C0000428ull + (offset) * 0x1000000ull;
255 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
256 return 0x00011800C0000428ull + (offset) * 0x1000000ull;
257 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
258 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
259 return 0x00011800C0000428ull + (offset) * 0x1000000ull;
260 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
261 return 0x00011800C0000428ull + (offset) * 0x1000000ull;
262 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
263 return 0x00011800C1000428ull + (offset) * 0x1000000ull - 16777216 * 1;
264 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
265 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
266 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
267 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
268 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
269 return 0x00011800C0000408ull + (offset) * 0x1000000ull;
270 }
271 return 0x00011800C0000428ull + (offset) * 0x1000000ull;
272 }
273
274 #define CVMX_PEMX_ON(offset) (0x00011800C0000420ull + ((offset) & 3) * 0x1000000ull)
275 #define CVMX_PEMX_P2N_BAR0_START(offset) (0x00011800C0000080ull + ((offset) & 3) * 0x1000000ull)
276 #define CVMX_PEMX_P2N_BAR1_START(offset) (0x00011800C0000088ull + ((offset) & 3) * 0x1000000ull)
277 #define CVMX_PEMX_P2N_BAR2_START(offset) (0x00011800C0000090ull + ((offset) & 3) * 0x1000000ull)
278 #define CVMX_PEMX_P2P_BARX_END(offset, block_id) \
279 (0x00011800C0000048ull + (((offset) & 3) + ((block_id) & 3) * 0x100000ull) * 16)
280 #define CVMX_PEMX_P2P_BARX_START(offset, block_id) \
281 (0x00011800C0000040ull + (((offset) & 3) + ((block_id) & 3) * 0x100000ull) * 16)
282 #define CVMX_PEMX_QLM(offset) (0x00011800C0000418ull + ((offset) & 3) * 0x1000000ull)
283 #define CVMX_PEMX_SPI_CTL(offset) (0x00011800C0000180ull + ((offset) & 3) * 0x1000000ull)
284 #define CVMX_PEMX_SPI_DATA(offset) (0x00011800C0000188ull + ((offset) & 3) * 0x1000000ull)
285 #define CVMX_PEMX_STRAP(offset) (0x00011800C0000408ull + ((offset) & 3) * 0x1000000ull)
286 #define CVMX_PEMX_TLP_CREDITS(offset) (0x00011800C0000038ull + ((offset) & 3) * 0x1000000ull)
287
288 /**
289 * cvmx_pem#_bar1_index#
290 *
291 * This register contains the address index and control bits for access to memory ranges of BAR1.
292 * The index is built from supplied address [25:22].
293 */
294 union cvmx_pemx_bar1_indexx {
295 u64 u64;
296 struct cvmx_pemx_bar1_indexx_s {
297 u64 reserved_24_63 : 40;
298 u64 addr_idx : 20;
299 u64 ca : 1;
300 u64 end_swp : 2;
301 u64 addr_v : 1;
302 } s;
303 struct cvmx_pemx_bar1_indexx_cn61xx {
304 u64 reserved_20_63 : 44;
305 u64 addr_idx : 16;
306 u64 ca : 1;
307 u64 end_swp : 2;
308 u64 addr_v : 1;
309 } cn61xx;
310 struct cvmx_pemx_bar1_indexx_cn61xx cn63xx;
311 struct cvmx_pemx_bar1_indexx_cn61xx cn63xxp1;
312 struct cvmx_pemx_bar1_indexx_cn61xx cn66xx;
313 struct cvmx_pemx_bar1_indexx_cn61xx cn68xx;
314 struct cvmx_pemx_bar1_indexx_cn61xx cn68xxp1;
315 struct cvmx_pemx_bar1_indexx_s cn70xx;
316 struct cvmx_pemx_bar1_indexx_s cn70xxp1;
317 struct cvmx_pemx_bar1_indexx_s cn73xx;
318 struct cvmx_pemx_bar1_indexx_s cn78xx;
319 struct cvmx_pemx_bar1_indexx_s cn78xxp1;
320 struct cvmx_pemx_bar1_indexx_cn61xx cnf71xx;
321 struct cvmx_pemx_bar1_indexx_s cnf75xx;
322 };
323
324 typedef union cvmx_pemx_bar1_indexx cvmx_pemx_bar1_indexx_t;
325
326 /**
327 * cvmx_pem#_bar2_mask
328 *
329 * This register contains the mask pattern that is ANDed with the address from the PCIe core for
330 * BAR2 hits. This allows the effective size of RC BAR2 to be shrunk. Must not be changed
331 * from its reset value in EP mode.
332 */
333 union cvmx_pemx_bar2_mask {
334 u64 u64;
335 struct cvmx_pemx_bar2_mask_s {
336 u64 reserved_45_63 : 19;
337 u64 mask : 42;
338 u64 reserved_0_2 : 3;
339 } s;
340 struct cvmx_pemx_bar2_mask_cn61xx {
341 u64 reserved_38_63 : 26;
342 u64 mask : 35;
343 u64 reserved_0_2 : 3;
344 } cn61xx;
345 struct cvmx_pemx_bar2_mask_cn61xx cn66xx;
346 struct cvmx_pemx_bar2_mask_cn61xx cn68xx;
347 struct cvmx_pemx_bar2_mask_cn61xx cn68xxp1;
348 struct cvmx_pemx_bar2_mask_cn61xx cn70xx;
349 struct cvmx_pemx_bar2_mask_cn61xx cn70xxp1;
350 struct cvmx_pemx_bar2_mask_cn73xx {
351 u64 reserved_42_63 : 22;
352 u64 mask : 39;
353 u64 reserved_0_2 : 3;
354 } cn73xx;
355 struct cvmx_pemx_bar2_mask_s cn78xx;
356 struct cvmx_pemx_bar2_mask_cn73xx cn78xxp1;
357 struct cvmx_pemx_bar2_mask_cn61xx cnf71xx;
358 struct cvmx_pemx_bar2_mask_cn73xx cnf75xx;
359 };
360
361 typedef union cvmx_pemx_bar2_mask cvmx_pemx_bar2_mask_t;
362
363 /**
364 * cvmx_pem#_bar_ctl
365 *
366 * This register contains control for BAR accesses.
367 *
368 */
369 union cvmx_pemx_bar_ctl {
370 u64 u64;
371 struct cvmx_pemx_bar_ctl_s {
372 u64 reserved_7_63 : 57;
373 u64 bar1_siz : 3;
374 u64 bar2_enb : 1;
375 u64 bar2_esx : 2;
376 u64 bar2_cax : 1;
377 } s;
378 struct cvmx_pemx_bar_ctl_s cn61xx;
379 struct cvmx_pemx_bar_ctl_s cn63xx;
380 struct cvmx_pemx_bar_ctl_s cn63xxp1;
381 struct cvmx_pemx_bar_ctl_s cn66xx;
382 struct cvmx_pemx_bar_ctl_s cn68xx;
383 struct cvmx_pemx_bar_ctl_s cn68xxp1;
384 struct cvmx_pemx_bar_ctl_s cn70xx;
385 struct cvmx_pemx_bar_ctl_s cn70xxp1;
386 struct cvmx_pemx_bar_ctl_s cn73xx;
387 struct cvmx_pemx_bar_ctl_s cn78xx;
388 struct cvmx_pemx_bar_ctl_s cn78xxp1;
389 struct cvmx_pemx_bar_ctl_s cnf71xx;
390 struct cvmx_pemx_bar_ctl_s cnf75xx;
391 };
392
393 typedef union cvmx_pemx_bar_ctl cvmx_pemx_bar_ctl_t;
394
395 /**
396 * cvmx_pem#_bist_status
397 *
398 * This register contains results from BIST runs of PEM's memories.
399 *
400 */
401 union cvmx_pemx_bist_status {
402 u64 u64;
403 struct cvmx_pemx_bist_status_s {
404 u64 reserved_16_63 : 48;
405 u64 retryc : 1;
406 u64 reserved_14_14 : 1;
407 u64 rqhdrb0 : 1;
408 u64 rqhdrb1 : 1;
409 u64 rqdatab0 : 1;
410 u64 rqdatab1 : 1;
411 u64 tlpn_d0 : 1;
412 u64 tlpn_d1 : 1;
413 u64 reserved_0_7 : 8;
414 } s;
415 struct cvmx_pemx_bist_status_cn61xx {
416 u64 reserved_8_63 : 56;
417 u64 retry : 1;
418 u64 rqdata0 : 1;
419 u64 rqdata1 : 1;
420 u64 rqdata2 : 1;
421 u64 rqdata3 : 1;
422 u64 rqhdr1 : 1;
423 u64 rqhdr0 : 1;
424 u64 sot : 1;
425 } cn61xx;
426 struct cvmx_pemx_bist_status_cn61xx cn63xx;
427 struct cvmx_pemx_bist_status_cn61xx cn63xxp1;
428 struct cvmx_pemx_bist_status_cn61xx cn66xx;
429 struct cvmx_pemx_bist_status_cn61xx cn68xx;
430 struct cvmx_pemx_bist_status_cn61xx cn68xxp1;
431 struct cvmx_pemx_bist_status_cn70xx {
432 u64 reserved_6_63 : 58;
433 u64 retry : 1;
434 u64 sot : 1;
435 u64 rqhdr0 : 1;
436 u64 rqhdr1 : 1;
437 u64 rqdata0 : 1;
438 u64 rqdata1 : 1;
439 } cn70xx;
440 struct cvmx_pemx_bist_status_cn70xx cn70xxp1;
441 struct cvmx_pemx_bist_status_cn73xx {
442 u64 reserved_16_63 : 48;
443 u64 retryc : 1;
444 u64 sot : 1;
445 u64 rqhdrb0 : 1;
446 u64 rqhdrb1 : 1;
447 u64 rqdatab0 : 1;
448 u64 rqdatab1 : 1;
449 u64 tlpn_d0 : 1;
450 u64 tlpn_d1 : 1;
451 u64 tlpn_ctl : 1;
452 u64 tlpp_d0 : 1;
453 u64 tlpp_d1 : 1;
454 u64 tlpp_ctl : 1;
455 u64 tlpc_d0 : 1;
456 u64 tlpc_d1 : 1;
457 u64 tlpc_ctl : 1;
458 u64 m2s : 1;
459 } cn73xx;
460 struct cvmx_pemx_bist_status_cn73xx cn78xx;
461 struct cvmx_pemx_bist_status_cn73xx cn78xxp1;
462 struct cvmx_pemx_bist_status_cn61xx cnf71xx;
463 struct cvmx_pemx_bist_status_cn73xx cnf75xx;
464 };
465
466 typedef union cvmx_pemx_bist_status cvmx_pemx_bist_status_t;
467
468 /**
469 * cvmx_pem#_bist_status2
470 *
471 * "PEM#_BIST_STATUS2 = PEM BIST Status Register
472 * Results from BIST runs of PEM's memories."
473 */
474 union cvmx_pemx_bist_status2 {
475 u64 u64;
476 struct cvmx_pemx_bist_status2_s {
477 u64 reserved_13_63 : 51;
478 u64 tlpn_d : 1;
479 u64 tlpn_ctl : 1;
480 u64 tlpp_d : 1;
481 u64 reserved_0_9 : 10;
482 } s;
483 struct cvmx_pemx_bist_status2_cn61xx {
484 u64 reserved_10_63 : 54;
485 u64 e2p_cpl : 1;
486 u64 e2p_n : 1;
487 u64 e2p_p : 1;
488 u64 peai_p2e : 1;
489 u64 pef_tpf1 : 1;
490 u64 pef_tpf0 : 1;
491 u64 pef_tnf : 1;
492 u64 pef_tcf1 : 1;
493 u64 pef_tc0 : 1;
494 u64 ppf : 1;
495 } cn61xx;
496 struct cvmx_pemx_bist_status2_cn61xx cn63xx;
497 struct cvmx_pemx_bist_status2_cn61xx cn63xxp1;
498 struct cvmx_pemx_bist_status2_cn61xx cn66xx;
499 struct cvmx_pemx_bist_status2_cn61xx cn68xx;
500 struct cvmx_pemx_bist_status2_cn61xx cn68xxp1;
501 struct cvmx_pemx_bist_status2_cn70xx {
502 u64 reserved_14_63 : 50;
503 u64 peai_p2e : 1;
504 u64 tlpn_d : 1;
505 u64 tlpn_ctl : 1;
506 u64 tlpp_d : 1;
507 u64 tlpp_ctl : 1;
508 u64 tlpc_d : 1;
509 u64 tlpc_ctl : 1;
510 u64 tlpan_d : 1;
511 u64 tlpan_ctl : 1;
512 u64 tlpap_d : 1;
513 u64 tlpap_ctl : 1;
514 u64 tlpac_d : 1;
515 u64 tlpac_ctl : 1;
516 u64 m2s : 1;
517 } cn70xx;
518 struct cvmx_pemx_bist_status2_cn70xx cn70xxp1;
519 struct cvmx_pemx_bist_status2_cn61xx cnf71xx;
520 };
521
522 typedef union cvmx_pemx_bist_status2 cvmx_pemx_bist_status2_t;
523
524 /**
525 * cvmx_pem#_cfg
526 *
527 * Configuration of the PCIe Application.
528 *
529 */
530 union cvmx_pemx_cfg {
531 u64 u64;
532 struct cvmx_pemx_cfg_s {
533 u64 reserved_5_63 : 59;
534 u64 laneswap : 1;
535 u64 reserved_2_3 : 2;
536 u64 md : 2;
537 } s;
538 struct cvmx_pemx_cfg_cn70xx {
539 u64 reserved_5_63 : 59;
540 u64 laneswap : 1;
541 u64 hostmd : 1;
542 u64 md : 3;
543 } cn70xx;
544 struct cvmx_pemx_cfg_cn70xx cn70xxp1;
545 struct cvmx_pemx_cfg_cn73xx {
546 u64 reserved_5_63 : 59;
547 u64 laneswap : 1;
548 u64 lanes8 : 1;
549 u64 hostmd : 1;
550 u64 md : 2;
551 } cn73xx;
552 struct cvmx_pemx_cfg_cn73xx cn78xx;
553 struct cvmx_pemx_cfg_cn73xx cn78xxp1;
554 struct cvmx_pemx_cfg_cn73xx cnf75xx;
555 };
556
557 typedef union cvmx_pemx_cfg cvmx_pemx_cfg_t;
558
559 /**
560 * cvmx_pem#_cfg_rd
561 *
562 * This register allows read access to the configuration in the PCIe core.
563 *
564 */
565 union cvmx_pemx_cfg_rd {
566 u64 u64;
567 struct cvmx_pemx_cfg_rd_s {
568 u64 data : 32;
569 u64 addr : 32;
570 } s;
571 struct cvmx_pemx_cfg_rd_s cn61xx;
572 struct cvmx_pemx_cfg_rd_s cn63xx;
573 struct cvmx_pemx_cfg_rd_s cn63xxp1;
574 struct cvmx_pemx_cfg_rd_s cn66xx;
575 struct cvmx_pemx_cfg_rd_s cn68xx;
576 struct cvmx_pemx_cfg_rd_s cn68xxp1;
577 struct cvmx_pemx_cfg_rd_s cn70xx;
578 struct cvmx_pemx_cfg_rd_s cn70xxp1;
579 struct cvmx_pemx_cfg_rd_s cn73xx;
580 struct cvmx_pemx_cfg_rd_s cn78xx;
581 struct cvmx_pemx_cfg_rd_s cn78xxp1;
582 struct cvmx_pemx_cfg_rd_s cnf71xx;
583 struct cvmx_pemx_cfg_rd_s cnf75xx;
584 };
585
586 typedef union cvmx_pemx_cfg_rd cvmx_pemx_cfg_rd_t;
587
588 /**
589 * cvmx_pem#_cfg_wr
590 *
591 * This register allows write access to the configuration in the PCIe core.
592 *
593 */
594 union cvmx_pemx_cfg_wr {
595 u64 u64;
596 struct cvmx_pemx_cfg_wr_s {
597 u64 data : 32;
598 u64 addr : 32;
599 } s;
600 struct cvmx_pemx_cfg_wr_s cn61xx;
601 struct cvmx_pemx_cfg_wr_s cn63xx;
602 struct cvmx_pemx_cfg_wr_s cn63xxp1;
603 struct cvmx_pemx_cfg_wr_s cn66xx;
604 struct cvmx_pemx_cfg_wr_s cn68xx;
605 struct cvmx_pemx_cfg_wr_s cn68xxp1;
606 struct cvmx_pemx_cfg_wr_s cn70xx;
607 struct cvmx_pemx_cfg_wr_s cn70xxp1;
608 struct cvmx_pemx_cfg_wr_s cn73xx;
609 struct cvmx_pemx_cfg_wr_s cn78xx;
610 struct cvmx_pemx_cfg_wr_s cn78xxp1;
611 struct cvmx_pemx_cfg_wr_s cnf71xx;
612 struct cvmx_pemx_cfg_wr_s cnf75xx;
613 };
614
615 typedef union cvmx_pemx_cfg_wr cvmx_pemx_cfg_wr_t;
616
617 /**
618 * cvmx_pem#_clk_en
619 *
620 * This register contains the clock enable for ECLK and PCE_CLK.
621 *
622 */
623 union cvmx_pemx_clk_en {
624 u64 u64;
625 struct cvmx_pemx_clk_en_s {
626 u64 reserved_2_63 : 62;
627 u64 pceclk_gate : 1;
628 u64 csclk_gate : 1;
629 } s;
630 struct cvmx_pemx_clk_en_s cn70xx;
631 struct cvmx_pemx_clk_en_s cn70xxp1;
632 struct cvmx_pemx_clk_en_s cn73xx;
633 struct cvmx_pemx_clk_en_s cn78xx;
634 struct cvmx_pemx_clk_en_s cn78xxp1;
635 struct cvmx_pemx_clk_en_s cnf75xx;
636 };
637
638 typedef union cvmx_pemx_clk_en cvmx_pemx_clk_en_t;
639
640 /**
641 * cvmx_pem#_cpl_lut_valid
642 *
643 * This register specifies the bit set for an outstanding tag read.
644 *
645 */
646 union cvmx_pemx_cpl_lut_valid {
647 u64 u64;
648 struct cvmx_pemx_cpl_lut_valid_s {
649 u64 tag : 64;
650 } s;
651 struct cvmx_pemx_cpl_lut_valid_cn61xx {
652 u64 reserved_32_63 : 32;
653 u64 tag : 32;
654 } cn61xx;
655 struct cvmx_pemx_cpl_lut_valid_cn61xx cn63xx;
656 struct cvmx_pemx_cpl_lut_valid_cn61xx cn63xxp1;
657 struct cvmx_pemx_cpl_lut_valid_cn61xx cn66xx;
658 struct cvmx_pemx_cpl_lut_valid_cn61xx cn68xx;
659 struct cvmx_pemx_cpl_lut_valid_cn61xx cn68xxp1;
660 struct cvmx_pemx_cpl_lut_valid_cn61xx cn70xx;
661 struct cvmx_pemx_cpl_lut_valid_cn61xx cn70xxp1;
662 struct cvmx_pemx_cpl_lut_valid_s cn73xx;
663 struct cvmx_pemx_cpl_lut_valid_s cn78xx;
664 struct cvmx_pemx_cpl_lut_valid_s cn78xxp1;
665 struct cvmx_pemx_cpl_lut_valid_cn61xx cnf71xx;
666 struct cvmx_pemx_cpl_lut_valid_s cnf75xx;
667 };
668
669 typedef union cvmx_pemx_cpl_lut_valid cvmx_pemx_cpl_lut_valid_t;
670
671 /**
672 * cvmx_pem#_ctl_status
673 *
674 * This is a general control and status register of the PEM.
675 *
676 */
677 union cvmx_pemx_ctl_status {
678 u64 u64;
679 struct cvmx_pemx_ctl_status_s {
680 u64 reserved_51_63 : 13;
681 u64 inv_dpar : 1;
682 u64 inv_hpar : 1;
683 u64 inv_rpar : 1;
684 u64 auto_sd : 1;
685 u64 dnum : 5;
686 u64 pbus : 8;
687 u64 reserved_32_33 : 2;
688 u64 cfg_rtry : 16;
689 u64 reserved_12_15 : 4;
690 u64 pm_xtoff : 1;
691 u64 pm_xpme : 1;
692 u64 ob_p_cmd : 1;
693 u64 reserved_7_8 : 2;
694 u64 nf_ecrc : 1;
695 u64 dly_one : 1;
696 u64 lnk_enb : 1;
697 u64 ro_ctlp : 1;
698 u64 fast_lm : 1;
699 u64 inv_ecrc : 1;
700 u64 inv_lcrc : 1;
701 } s;
702 struct cvmx_pemx_ctl_status_cn61xx {
703 u64 reserved_48_63 : 16;
704 u64 auto_sd : 1;
705 u64 dnum : 5;
706 u64 pbus : 8;
707 u64 reserved_32_33 : 2;
708 u64 cfg_rtry : 16;
709 u64 reserved_12_15 : 4;
710 u64 pm_xtoff : 1;
711 u64 pm_xpme : 1;
712 u64 ob_p_cmd : 1;
713 u64 reserved_7_8 : 2;
714 u64 nf_ecrc : 1;
715 u64 dly_one : 1;
716 u64 lnk_enb : 1;
717 u64 ro_ctlp : 1;
718 u64 fast_lm : 1;
719 u64 inv_ecrc : 1;
720 u64 inv_lcrc : 1;
721 } cn61xx;
722 struct cvmx_pemx_ctl_status_cn61xx cn63xx;
723 struct cvmx_pemx_ctl_status_cn61xx cn63xxp1;
724 struct cvmx_pemx_ctl_status_cn61xx cn66xx;
725 struct cvmx_pemx_ctl_status_cn61xx cn68xx;
726 struct cvmx_pemx_ctl_status_cn61xx cn68xxp1;
727 struct cvmx_pemx_ctl_status_s cn70xx;
728 struct cvmx_pemx_ctl_status_s cn70xxp1;
729 struct cvmx_pemx_ctl_status_cn73xx {
730 u64 reserved_51_63 : 13;
731 u64 inv_dpar : 1;
732 u64 reserved_48_49 : 2;
733 u64 auto_sd : 1;
734 u64 dnum : 5;
735 u64 pbus : 8;
736 u64 reserved_32_33 : 2;
737 u64 cfg_rtry : 16;
738 u64 reserved_12_15 : 4;
739 u64 pm_xtoff : 1;
740 u64 pm_xpme : 1;
741 u64 ob_p_cmd : 1;
742 u64 reserved_7_8 : 2;
743 u64 nf_ecrc : 1;
744 u64 dly_one : 1;
745 u64 lnk_enb : 1;
746 u64 ro_ctlp : 1;
747 u64 fast_lm : 1;
748 u64 inv_ecrc : 1;
749 u64 inv_lcrc : 1;
750 } cn73xx;
751 struct cvmx_pemx_ctl_status_cn73xx cn78xx;
752 struct cvmx_pemx_ctl_status_cn73xx cn78xxp1;
753 struct cvmx_pemx_ctl_status_cn61xx cnf71xx;
754 struct cvmx_pemx_ctl_status_cn73xx cnf75xx;
755 };
756
757 typedef union cvmx_pemx_ctl_status cvmx_pemx_ctl_status_t;
758
759 /**
760 * cvmx_pem#_ctl_status2
761 *
762 * This register contains additional general control and status of the PEM.
763 *
764 */
765 union cvmx_pemx_ctl_status2 {
766 u64 u64;
767 struct cvmx_pemx_ctl_status2_s {
768 u64 reserved_16_63 : 48;
769 u64 no_fwd_prg : 16;
770 } s;
771 struct cvmx_pemx_ctl_status2_s cn73xx;
772 struct cvmx_pemx_ctl_status2_s cn78xx;
773 struct cvmx_pemx_ctl_status2_s cn78xxp1;
774 struct cvmx_pemx_ctl_status2_s cnf75xx;
775 };
776
777 typedef union cvmx_pemx_ctl_status2 cvmx_pemx_ctl_status2_t;
778
779 /**
780 * cvmx_pem#_dbg_info
781 *
782 * This is a debug information register of the PEM.
783 *
784 */
785 union cvmx_pemx_dbg_info {
786 u64 u64;
787 struct cvmx_pemx_dbg_info_s {
788 u64 reserved_62_63 : 2;
789 u64 m2s_c_dbe : 1;
790 u64 m2s_c_sbe : 1;
791 u64 m2s_d_dbe : 1;
792 u64 m2s_d_sbe : 1;
793 u64 qhdr_b1_dbe : 1;
794 u64 qhdr_b1_sbe : 1;
795 u64 qhdr_b0_dbe : 1;
796 u64 qhdr_b0_sbe : 1;
797 u64 rtry_dbe : 1;
798 u64 rtry_sbe : 1;
799 u64 reserved_50_51 : 2;
800 u64 c_d1_dbe : 1;
801 u64 c_d1_sbe : 1;
802 u64 c_d0_dbe : 1;
803 u64 c_d0_sbe : 1;
804 u64 reserved_34_45 : 12;
805 u64 datq_pe : 1;
806 u64 reserved_31_32 : 2;
807 u64 ecrc_e : 1;
808 u64 rawwpp : 1;
809 u64 racpp : 1;
810 u64 ramtlp : 1;
811 u64 rarwdns : 1;
812 u64 caar : 1;
813 u64 racca : 1;
814 u64 racur : 1;
815 u64 rauc : 1;
816 u64 rqo : 1;
817 u64 fcuv : 1;
818 u64 rpe : 1;
819 u64 fcpvwt : 1;
820 u64 dpeoosd : 1;
821 u64 rtwdle : 1;
822 u64 rdwdle : 1;
823 u64 mre : 1;
824 u64 rte : 1;
825 u64 acto : 1;
826 u64 rvdm : 1;
827 u64 rumep : 1;
828 u64 rptamrc : 1;
829 u64 rpmerc : 1;
830 u64 rfemrc : 1;
831 u64 rnfemrc : 1;
832 u64 rcemrc : 1;
833 u64 rpoison : 1;
834 u64 recrce : 1;
835 u64 rtlplle : 1;
836 u64 rtlpmal : 1;
837 u64 spoison : 1;
838 } s;
839 struct cvmx_pemx_dbg_info_cn61xx {
840 u64 reserved_31_63 : 33;
841 u64 ecrc_e : 1;
842 u64 rawwpp : 1;
843 u64 racpp : 1;
844 u64 ramtlp : 1;
845 u64 rarwdns : 1;
846 u64 caar : 1;
847 u64 racca : 1;
848 u64 racur : 1;
849 u64 rauc : 1;
850 u64 rqo : 1;
851 u64 fcuv : 1;
852 u64 rpe : 1;
853 u64 fcpvwt : 1;
854 u64 dpeoosd : 1;
855 u64 rtwdle : 1;
856 u64 rdwdle : 1;
857 u64 mre : 1;
858 u64 rte : 1;
859 u64 acto : 1;
860 u64 rvdm : 1;
861 u64 rumep : 1;
862 u64 rptamrc : 1;
863 u64 rpmerc : 1;
864 u64 rfemrc : 1;
865 u64 rnfemrc : 1;
866 u64 rcemrc : 1;
867 u64 rpoison : 1;
868 u64 recrce : 1;
869 u64 rtlplle : 1;
870 u64 rtlpmal : 1;
871 u64 spoison : 1;
872 } cn61xx;
873 struct cvmx_pemx_dbg_info_cn61xx cn63xx;
874 struct cvmx_pemx_dbg_info_cn61xx cn63xxp1;
875 struct cvmx_pemx_dbg_info_cn61xx cn66xx;
876 struct cvmx_pemx_dbg_info_cn61xx cn68xx;
877 struct cvmx_pemx_dbg_info_cn61xx cn68xxp1;
878 struct cvmx_pemx_dbg_info_cn70xx {
879 u64 reserved_46_63 : 18;
880 u64 c_c_dbe : 1;
881 u64 c_c_sbe : 1;
882 u64 c_d_dbe : 1;
883 u64 c_d_sbe : 1;
884 u64 n_c_dbe : 1;
885 u64 n_c_sbe : 1;
886 u64 n_d_dbe : 1;
887 u64 n_d_sbe : 1;
888 u64 p_c_dbe : 1;
889 u64 p_c_sbe : 1;
890 u64 p_d_dbe : 1;
891 u64 p_d_sbe : 1;
892 u64 datq_pe : 1;
893 u64 hdrq_pe : 1;
894 u64 rtry_pe : 1;
895 u64 ecrc_e : 1;
896 u64 rawwpp : 1;
897 u64 racpp : 1;
898 u64 ramtlp : 1;
899 u64 rarwdns : 1;
900 u64 caar : 1;
901 u64 racca : 1;
902 u64 racur : 1;
903 u64 rauc : 1;
904 u64 rqo : 1;
905 u64 fcuv : 1;
906 u64 rpe : 1;
907 u64 fcpvwt : 1;
908 u64 dpeoosd : 1;
909 u64 rtwdle : 1;
910 u64 rdwdle : 1;
911 u64 mre : 1;
912 u64 rte : 1;
913 u64 acto : 1;
914 u64 rvdm : 1;
915 u64 rumep : 1;
916 u64 rptamrc : 1;
917 u64 rpmerc : 1;
918 u64 rfemrc : 1;
919 u64 rnfemrc : 1;
920 u64 rcemrc : 1;
921 u64 rpoison : 1;
922 u64 recrce : 1;
923 u64 rtlplle : 1;
924 u64 rtlpmal : 1;
925 u64 spoison : 1;
926 } cn70xx;
927 struct cvmx_pemx_dbg_info_cn70xx cn70xxp1;
928 struct cvmx_pemx_dbg_info_cn73xx {
929 u64 reserved_62_63 : 2;
930 u64 m2s_c_dbe : 1;
931 u64 m2s_c_sbe : 1;
932 u64 m2s_d_dbe : 1;
933 u64 m2s_d_sbe : 1;
934 u64 qhdr_b1_dbe : 1;
935 u64 qhdr_b1_sbe : 1;
936 u64 qhdr_b0_dbe : 1;
937 u64 qhdr_b0_sbe : 1;
938 u64 rtry_dbe : 1;
939 u64 rtry_sbe : 1;
940 u64 c_c_dbe : 1;
941 u64 c_c_sbe : 1;
942 u64 c_d1_dbe : 1;
943 u64 c_d1_sbe : 1;
944 u64 c_d0_dbe : 1;
945 u64 c_d0_sbe : 1;
946 u64 n_c_dbe : 1;
947 u64 n_c_sbe : 1;
948 u64 n_d1_dbe : 1;
949 u64 n_d1_sbe : 1;
950 u64 n_d0_dbe : 1;
951 u64 n_d0_sbe : 1;
952 u64 p_c_dbe : 1;
953 u64 p_c_sbe : 1;
954 u64 p_d1_dbe : 1;
955 u64 p_d1_sbe : 1;
956 u64 p_d0_dbe : 1;
957 u64 p_d0_sbe : 1;
958 u64 datq_pe : 1;
959 u64 bmd_e : 1;
960 u64 lofp : 1;
961 u64 ecrc_e : 1;
962 u64 rawwpp : 1;
963 u64 racpp : 1;
964 u64 ramtlp : 1;
965 u64 rarwdns : 1;
966 u64 caar : 1;
967 u64 racca : 1;
968 u64 racur : 1;
969 u64 rauc : 1;
970 u64 rqo : 1;
971 u64 fcuv : 1;
972 u64 rpe : 1;
973 u64 fcpvwt : 1;
974 u64 dpeoosd : 1;
975 u64 rtwdle : 1;
976 u64 rdwdle : 1;
977 u64 mre : 1;
978 u64 rte : 1;
979 u64 acto : 1;
980 u64 rvdm : 1;
981 u64 rumep : 1;
982 u64 rptamrc : 1;
983 u64 rpmerc : 1;
984 u64 rfemrc : 1;
985 u64 rnfemrc : 1;
986 u64 rcemrc : 1;
987 u64 rpoison : 1;
988 u64 recrce : 1;
989 u64 rtlplle : 1;
990 u64 rtlpmal : 1;
991 u64 spoison : 1;
992 } cn73xx;
993 struct cvmx_pemx_dbg_info_cn73xx cn78xx;
994 struct cvmx_pemx_dbg_info_cn78xxp1 {
995 u64 reserved_58_63 : 6;
996 u64 qhdr_b1_dbe : 1;
997 u64 qhdr_b1_sbe : 1;
998 u64 qhdr_b0_dbe : 1;
999 u64 qhdr_b0_sbe : 1;
1000 u64 rtry_dbe : 1;
1001 u64 rtry_sbe : 1;
1002 u64 c_c_dbe : 1;
1003 u64 c_c_sbe : 1;
1004 u64 c_d1_dbe : 1;
1005 u64 c_d1_sbe : 1;
1006 u64 c_d0_dbe : 1;
1007 u64 c_d0_sbe : 1;
1008 u64 n_c_dbe : 1;
1009 u64 n_c_sbe : 1;
1010 u64 n_d1_dbe : 1;
1011 u64 n_d1_sbe : 1;
1012 u64 n_d0_dbe : 1;
1013 u64 n_d0_sbe : 1;
1014 u64 p_c_dbe : 1;
1015 u64 p_c_sbe : 1;
1016 u64 p_d1_dbe : 1;
1017 u64 p_d1_sbe : 1;
1018 u64 p_d0_dbe : 1;
1019 u64 p_d0_sbe : 1;
1020 u64 datq_pe : 1;
1021 u64 reserved_32_32 : 1;
1022 u64 lofp : 1;
1023 u64 ecrc_e : 1;
1024 u64 rawwpp : 1;
1025 u64 racpp : 1;
1026 u64 ramtlp : 1;
1027 u64 rarwdns : 1;
1028 u64 caar : 1;
1029 u64 racca : 1;
1030 u64 racur : 1;
1031 u64 rauc : 1;
1032 u64 rqo : 1;
1033 u64 fcuv : 1;
1034 u64 rpe : 1;
1035 u64 fcpvwt : 1;
1036 u64 dpeoosd : 1;
1037 u64 rtwdle : 1;
1038 u64 rdwdle : 1;
1039 u64 mre : 1;
1040 u64 rte : 1;
1041 u64 acto : 1;
1042 u64 rvdm : 1;
1043 u64 rumep : 1;
1044 u64 rptamrc : 1;
1045 u64 rpmerc : 1;
1046 u64 rfemrc : 1;
1047 u64 rnfemrc : 1;
1048 u64 rcemrc : 1;
1049 u64 rpoison : 1;
1050 u64 recrce : 1;
1051 u64 rtlplle : 1;
1052 u64 rtlpmal : 1;
1053 u64 spoison : 1;
1054 } cn78xxp1;
1055 struct cvmx_pemx_dbg_info_cn61xx cnf71xx;
1056 struct cvmx_pemx_dbg_info_cn73xx cnf75xx;
1057 };
1058
1059 typedef union cvmx_pemx_dbg_info cvmx_pemx_dbg_info_t;
1060
1061 /**
1062 * cvmx_pem#_dbg_info_en
1063 *
1064 * "PEM#_DBG_INFO_EN = PEM Debug Information Enable
1065 * Allows PEM_DBG_INFO to generate interrupts when cooresponding enable bit is set."
1066 */
1067 union cvmx_pemx_dbg_info_en {
1068 u64 u64;
1069 struct cvmx_pemx_dbg_info_en_s {
1070 u64 reserved_46_63 : 18;
1071 u64 tpcdbe1 : 1;
1072 u64 tpcsbe1 : 1;
1073 u64 tpcdbe0 : 1;
1074 u64 tpcsbe0 : 1;
1075 u64 tnfdbe1 : 1;
1076 u64 tnfsbe1 : 1;
1077 u64 tnfdbe0 : 1;
1078 u64 tnfsbe0 : 1;
1079 u64 tpfdbe1 : 1;
1080 u64 tpfsbe1 : 1;
1081 u64 tpfdbe0 : 1;
1082 u64 tpfsbe0 : 1;
1083 u64 datq_pe : 1;
1084 u64 hdrq_pe : 1;
1085 u64 rtry_pe : 1;
1086 u64 ecrc_e : 1;
1087 u64 rawwpp : 1;
1088 u64 racpp : 1;
1089 u64 ramtlp : 1;
1090 u64 rarwdns : 1;
1091 u64 caar : 1;
1092 u64 racca : 1;
1093 u64 racur : 1;
1094 u64 rauc : 1;
1095 u64 rqo : 1;
1096 u64 fcuv : 1;
1097 u64 rpe : 1;
1098 u64 fcpvwt : 1;
1099 u64 dpeoosd : 1;
1100 u64 rtwdle : 1;
1101 u64 rdwdle : 1;
1102 u64 mre : 1;
1103 u64 rte : 1;
1104 u64 acto : 1;
1105 u64 rvdm : 1;
1106 u64 rumep : 1;
1107 u64 rptamrc : 1;
1108 u64 rpmerc : 1;
1109 u64 rfemrc : 1;
1110 u64 rnfemrc : 1;
1111 u64 rcemrc : 1;
1112 u64 rpoison : 1;
1113 u64 recrce : 1;
1114 u64 rtlplle : 1;
1115 u64 rtlpmal : 1;
1116 u64 spoison : 1;
1117 } s;
1118 struct cvmx_pemx_dbg_info_en_cn61xx {
1119 u64 reserved_31_63 : 33;
1120 u64 ecrc_e : 1;
1121 u64 rawwpp : 1;
1122 u64 racpp : 1;
1123 u64 ramtlp : 1;
1124 u64 rarwdns : 1;
1125 u64 caar : 1;
1126 u64 racca : 1;
1127 u64 racur : 1;
1128 u64 rauc : 1;
1129 u64 rqo : 1;
1130 u64 fcuv : 1;
1131 u64 rpe : 1;
1132 u64 fcpvwt : 1;
1133 u64 dpeoosd : 1;
1134 u64 rtwdle : 1;
1135 u64 rdwdle : 1;
1136 u64 mre : 1;
1137 u64 rte : 1;
1138 u64 acto : 1;
1139 u64 rvdm : 1;
1140 u64 rumep : 1;
1141 u64 rptamrc : 1;
1142 u64 rpmerc : 1;
1143 u64 rfemrc : 1;
1144 u64 rnfemrc : 1;
1145 u64 rcemrc : 1;
1146 u64 rpoison : 1;
1147 u64 recrce : 1;
1148 u64 rtlplle : 1;
1149 u64 rtlpmal : 1;
1150 u64 spoison : 1;
1151 } cn61xx;
1152 struct cvmx_pemx_dbg_info_en_cn61xx cn63xx;
1153 struct cvmx_pemx_dbg_info_en_cn61xx cn63xxp1;
1154 struct cvmx_pemx_dbg_info_en_cn61xx cn66xx;
1155 struct cvmx_pemx_dbg_info_en_cn61xx cn68xx;
1156 struct cvmx_pemx_dbg_info_en_cn61xx cn68xxp1;
1157 struct cvmx_pemx_dbg_info_en_s cn70xx;
1158 struct cvmx_pemx_dbg_info_en_s cn70xxp1;
1159 struct cvmx_pemx_dbg_info_en_cn61xx cnf71xx;
1160 };
1161
1162 typedef union cvmx_pemx_dbg_info_en cvmx_pemx_dbg_info_en_t;
1163
1164 /**
1165 * cvmx_pem#_diag_status
1166 *
1167 * This register contains selection control for the core diagnostic bus.
1168 *
1169 */
1170 union cvmx_pemx_diag_status {
1171 u64 u64;
1172 struct cvmx_pemx_diag_status_s {
1173 u64 reserved_9_63 : 55;
1174 u64 pwrdwn : 3;
1175 u64 pm_dst : 3;
1176 u64 pm_stat : 1;
1177 u64 pm_en : 1;
1178 u64 aux_en : 1;
1179 } s;
1180 struct cvmx_pemx_diag_status_cn61xx {
1181 u64 reserved_4_63 : 60;
1182 u64 pm_dst : 1;
1183 u64 pm_stat : 1;
1184 u64 pm_en : 1;
1185 u64 aux_en : 1;
1186 } cn61xx;
1187 struct cvmx_pemx_diag_status_cn61xx cn63xx;
1188 struct cvmx_pemx_diag_status_cn61xx cn63xxp1;
1189 struct cvmx_pemx_diag_status_cn61xx cn66xx;
1190 struct cvmx_pemx_diag_status_cn61xx cn68xx;
1191 struct cvmx_pemx_diag_status_cn61xx cn68xxp1;
1192 struct cvmx_pemx_diag_status_cn70xx {
1193 u64 reserved_63_6 : 58;
1194 u64 pm_dst : 3;
1195 u64 pm_stat : 1;
1196 u64 pm_en : 1;
1197 u64 aux_en : 1;
1198 } cn70xx;
1199 struct cvmx_pemx_diag_status_cn70xx cn70xxp1;
1200 struct cvmx_pemx_diag_status_cn73xx {
1201 u64 reserved_63_9 : 55;
1202 u64 pwrdwn : 3;
1203 u64 pm_dst : 3;
1204 u64 pm_stat : 1;
1205 u64 pm_en : 1;
1206 u64 aux_en : 1;
1207 } cn73xx;
1208 struct cvmx_pemx_diag_status_cn73xx cn78xx;
1209 struct cvmx_pemx_diag_status_cn73xx cn78xxp1;
1210 struct cvmx_pemx_diag_status_cn61xx cnf71xx;
1211 struct cvmx_pemx_diag_status_cn73xx cnf75xx;
1212 };
1213
1214 typedef union cvmx_pemx_diag_status cvmx_pemx_diag_status_t;
1215
1216 /**
1217 * cvmx_pem#_ecc_ena
1218 *
1219 * Contains enables for TLP FIFO ECC RAMs.
1220 *
1221 */
1222 union cvmx_pemx_ecc_ena {
1223 u64 u64;
1224 struct cvmx_pemx_ecc_ena_s {
1225 u64 reserved_35_63 : 29;
1226 u64 qhdr_b1_ena : 1;
1227 u64 qhdr_b0_ena : 1;
1228 u64 rtry_ena : 1;
1229 u64 reserved_11_31 : 21;
1230 u64 m2s_c_ena : 1;
1231 u64 m2s_d_ena : 1;
1232 u64 c_c_ena : 1;
1233 u64 c_d1_ena : 1;
1234 u64 c_d0_ena : 1;
1235 u64 reserved_0_5 : 6;
1236 } s;
1237 struct cvmx_pemx_ecc_ena_cn70xx {
1238 u64 reserved_6_63 : 58;
1239 u64 tlp_nc_ena : 1;
1240 u64 tlp_nd_ena : 1;
1241 u64 tlp_pc_ena : 1;
1242 u64 tlp_pd_ena : 1;
1243 u64 tlp_cc_ena : 1;
1244 u64 tlp_cd_ena : 1;
1245 } cn70xx;
1246 struct cvmx_pemx_ecc_ena_cn70xx cn70xxp1;
1247 struct cvmx_pemx_ecc_ena_cn73xx {
1248 u64 reserved_35_63 : 29;
1249 u64 qhdr_b1_ena : 1;
1250 u64 qhdr_b0_ena : 1;
1251 u64 rtry_ena : 1;
1252 u64 reserved_11_31 : 21;
1253 u64 m2s_c_ena : 1;
1254 u64 m2s_d_ena : 1;
1255 u64 c_c_ena : 1;
1256 u64 c_d1_ena : 1;
1257 u64 c_d0_ena : 1;
1258 u64 n_c_ena : 1;
1259 u64 n_d1_ena : 1;
1260 u64 n_d0_ena : 1;
1261 u64 p_c_ena : 1;
1262 u64 p_d1_ena : 1;
1263 u64 p_d0_ena : 1;
1264 } cn73xx;
1265 struct cvmx_pemx_ecc_ena_cn73xx cn78xx;
1266 struct cvmx_pemx_ecc_ena_cn78xxp1 {
1267 u64 reserved_35_63 : 29;
1268 u64 qhdr_b1_ena : 1;
1269 u64 qhdr_b0_ena : 1;
1270 u64 rtry_ena : 1;
1271 u64 reserved_9_31 : 23;
1272 u64 c_c_ena : 1;
1273 u64 c_d1_ena : 1;
1274 u64 c_d0_ena : 1;
1275 u64 n_c_ena : 1;
1276 u64 n_d1_ena : 1;
1277 u64 n_d0_ena : 1;
1278 u64 p_c_ena : 1;
1279 u64 p_d1_ena : 1;
1280 u64 p_d0_ena : 1;
1281 } cn78xxp1;
1282 struct cvmx_pemx_ecc_ena_cn73xx cnf75xx;
1283 };
1284
1285 typedef union cvmx_pemx_ecc_ena cvmx_pemx_ecc_ena_t;
1286
1287 /**
1288 * cvmx_pem#_ecc_synd_ctrl
1289 *
1290 * This register contains syndrome control for TLP FIFO ECC RAMs.
1291 *
1292 */
1293 union cvmx_pemx_ecc_synd_ctrl {
1294 u64 u64;
1295 struct cvmx_pemx_ecc_synd_ctrl_s {
1296 u64 reserved_38_63 : 26;
1297 u64 qhdr_b1_syn : 2;
1298 u64 qhdr_b0_syn : 2;
1299 u64 rtry_syn : 2;
1300 u64 reserved_22_31 : 10;
1301 u64 m2s_c_syn : 2;
1302 u64 m2s_d_syn : 2;
1303 u64 c_c_syn : 2;
1304 u64 c_d1_syn : 2;
1305 u64 c_d0_syn : 2;
1306 u64 reserved_0_11 : 12;
1307 } s;
1308 struct cvmx_pemx_ecc_synd_ctrl_cn70xx {
1309 u64 reserved_12_63 : 52;
1310 u64 tlp_nc_syn : 2;
1311 u64 tlp_nd_syn : 2;
1312 u64 tlp_pc_syn : 2;
1313 u64 tlp_pd_syn : 2;
1314 u64 tlp_cc_syn : 2;
1315 u64 tlp_cd_syn : 2;
1316 } cn70xx;
1317 struct cvmx_pemx_ecc_synd_ctrl_cn70xx cn70xxp1;
1318 struct cvmx_pemx_ecc_synd_ctrl_cn73xx {
1319 u64 reserved_38_63 : 26;
1320 u64 qhdr_b1_syn : 2;
1321 u64 qhdr_b0_syn : 2;
1322 u64 rtry_syn : 2;
1323 u64 reserved_22_31 : 10;
1324 u64 m2s_c_syn : 2;
1325 u64 m2s_d_syn : 2;
1326 u64 c_c_syn : 2;
1327 u64 c_d1_syn : 2;
1328 u64 c_d0_syn : 2;
1329 u64 n_c_syn : 2;
1330 u64 n_d1_syn : 2;
1331 u64 n_d0_syn : 2;
1332 u64 p_c_syn : 2;
1333 u64 p_d1_syn : 2;
1334 u64 p_d0_syn : 2;
1335 } cn73xx;
1336 struct cvmx_pemx_ecc_synd_ctrl_cn73xx cn78xx;
1337 struct cvmx_pemx_ecc_synd_ctrl_cn78xxp1 {
1338 u64 reserved_38_63 : 26;
1339 u64 qhdr_b1_syn : 2;
1340 u64 qhdr_b0_syn : 2;
1341 u64 rtry_syn : 2;
1342 u64 reserved_18_31 : 14;
1343 u64 c_c_syn : 2;
1344 u64 c_d1_syn : 2;
1345 u64 c_d0_syn : 2;
1346 u64 n_c_syn : 2;
1347 u64 n_d1_syn : 2;
1348 u64 n_d0_syn : 2;
1349 u64 p_c_syn : 2;
1350 u64 p_d1_syn : 2;
1351 u64 p_d0_syn : 2;
1352 } cn78xxp1;
1353 struct cvmx_pemx_ecc_synd_ctrl_cn73xx cnf75xx;
1354 };
1355
1356 typedef union cvmx_pemx_ecc_synd_ctrl cvmx_pemx_ecc_synd_ctrl_t;
1357
1358 /**
1359 * cvmx_pem#_eco
1360 */
1361 union cvmx_pemx_eco {
1362 u64 u64;
1363 struct cvmx_pemx_eco_s {
1364 u64 reserved_8_63 : 56;
1365 u64 eco_rw : 8;
1366 } s;
1367 struct cvmx_pemx_eco_s cn73xx;
1368 struct cvmx_pemx_eco_s cn78xx;
1369 struct cvmx_pemx_eco_s cnf75xx;
1370 };
1371
1372 typedef union cvmx_pemx_eco cvmx_pemx_eco_t;
1373
1374 /**
1375 * cvmx_pem#_flr_glblcnt_ctl
1376 */
1377 union cvmx_pemx_flr_glblcnt_ctl {
1378 u64 u64;
1379 struct cvmx_pemx_flr_glblcnt_ctl_s {
1380 u64 reserved_4_63 : 60;
1381 u64 chge : 1;
1382 u64 inc : 1;
1383 u64 delta : 2;
1384 } s;
1385 struct cvmx_pemx_flr_glblcnt_ctl_s cn73xx;
1386 struct cvmx_pemx_flr_glblcnt_ctl_s cn78xx;
1387 struct cvmx_pemx_flr_glblcnt_ctl_s cnf75xx;
1388 };
1389
1390 typedef union cvmx_pemx_flr_glblcnt_ctl cvmx_pemx_flr_glblcnt_ctl_t;
1391
1392 /**
1393 * cvmx_pem#_flr_pf0_vf_stopreq
1394 *
1395 * Hardware automatically sets the STOPREQ bit for the VF when it enters a
1396 * Function Level Reset (FLR). Software is responsible for clearing the STOPREQ
1397 * bit but must not do so prior to hardware taking down the FLR, which could be
1398 * as long as 100ms. It may be appropriate for software to wait longer before clearing
1399 * STOPREQ, software may need to drain deep DPI queues for example.
1400 * Whenever PEM receives a request mastered by CNXXXX over S2M (i.e. P or NP),
1401 * when STOPREQ is set for the function, PEM will discard the outgoing request
1402 * before sending it to the PCIe core. If a NP, PEM will schedule an immediate
1403 * SWI_RSP_ERROR completion for the request - no timeout is required.
1404 *
1405 * STOPREQ mimics the behavior of PCIEEPVF()_CFG001[ME] for outbound requests that will
1406 * master the PCIe bus (P and NP).
1407 *
1408 * Note that STOPREQ will have no effect on completions returned by CNXXXX over the S2M,
1409 * nor on M2S traffic.
1410 */
1411 union cvmx_pemx_flr_pf0_vf_stopreq {
1412 u64 u64;
1413 struct cvmx_pemx_flr_pf0_vf_stopreq_s {
1414 u64 vf_stopreq : 64;
1415 } s;
1416 struct cvmx_pemx_flr_pf0_vf_stopreq_s cn73xx;
1417 struct cvmx_pemx_flr_pf0_vf_stopreq_s cn78xx;
1418 struct cvmx_pemx_flr_pf0_vf_stopreq_s cnf75xx;
1419 };
1420
1421 typedef union cvmx_pemx_flr_pf0_vf_stopreq cvmx_pemx_flr_pf0_vf_stopreq_t;
1422
1423 /**
1424 * cvmx_pem#_flr_pf_stopreq
1425 *
1426 * Hardware automatically sets the STOPREQ bit for the PF when it enters a
1427 * Function Level Reset (FLR). Software is responsible for clearing the STOPREQ
1428 * bit but must not do so prior to hardware taking down the FLR, which could be
1429 * as long as 100ms. It may be appropriate for software to wait longer before clearing
1430 * STOPREQ, software may need to drain deep DPI queues for example.
1431 * Whenever PEM receives a PF or child VF request mastered by CNXXXX over S2M (i.e. P or NP),
1432 * when STOPREQ is set for the function, PEM will discard the outgoing request
1433 * before sending it to the PCIe core. If a NP, PEM will schedule an immediate
1434 * SWI_RSP_ERROR completion for the request - no timeout is required.
1435 *
1436 * STOPREQ mimics the behavior of PCIEEP()_CFG001[ME] for outbound requests that will
1437 * master the PCIe bus (P and NP).
1438 *
1439 * STOPREQ will have no effect on completions returned by CNXXXX over the S2M,
1440 * nor on M2S traffic.
1441 *
1442 * When a PF()_STOPREQ is set, none of the associated
1443 * PEM()_FLR_PF()_VF_STOPREQ[VF_STOPREQ] will be set.
1444 *
1445 * STOPREQ is reset when the MAC is reset, and is not reset after a chip soft reset.
1446 */
1447 union cvmx_pemx_flr_pf_stopreq {
1448 u64 u64;
1449 struct cvmx_pemx_flr_pf_stopreq_s {
1450 u64 reserved_1_63 : 63;
1451 u64 pf0_stopreq : 1;
1452 } s;
1453 struct cvmx_pemx_flr_pf_stopreq_s cn73xx;
1454 struct cvmx_pemx_flr_pf_stopreq_s cn78xx;
1455 struct cvmx_pemx_flr_pf_stopreq_s cnf75xx;
1456 };
1457
1458 typedef union cvmx_pemx_flr_pf_stopreq cvmx_pemx_flr_pf_stopreq_t;
1459
1460 /**
1461 * cvmx_pem#_flr_stopreq_ctl
1462 */
1463 union cvmx_pemx_flr_stopreq_ctl {
1464 u64 u64;
1465 struct cvmx_pemx_flr_stopreq_ctl_s {
1466 u64 reserved_1_63 : 63;
1467 u64 stopreqclr : 1;
1468 } s;
1469 struct cvmx_pemx_flr_stopreq_ctl_s cn78xx;
1470 struct cvmx_pemx_flr_stopreq_ctl_s cnf75xx;
1471 };
1472
1473 typedef union cvmx_pemx_flr_stopreq_ctl cvmx_pemx_flr_stopreq_ctl_t;
1474
1475 /**
1476 * cvmx_pem#_flr_zombie_ctl
1477 */
1478 union cvmx_pemx_flr_zombie_ctl {
1479 u64 u64;
1480 struct cvmx_pemx_flr_zombie_ctl_s {
1481 u64 reserved_10_63 : 54;
1482 u64 exp : 10;
1483 } s;
1484 struct cvmx_pemx_flr_zombie_ctl_s cn73xx;
1485 struct cvmx_pemx_flr_zombie_ctl_s cn78xx;
1486 struct cvmx_pemx_flr_zombie_ctl_s cnf75xx;
1487 };
1488
1489 typedef union cvmx_pemx_flr_zombie_ctl cvmx_pemx_flr_zombie_ctl_t;
1490
1491 /**
1492 * cvmx_pem#_inb_read_credits
1493 *
1494 * This register contains the number of in-flight read operations from PCIe core to SLI.
1495 *
1496 */
1497 union cvmx_pemx_inb_read_credits {
1498 u64 u64;
1499 struct cvmx_pemx_inb_read_credits_s {
1500 u64 reserved_7_63 : 57;
1501 u64 num : 7;
1502 } s;
1503 struct cvmx_pemx_inb_read_credits_cn61xx {
1504 u64 reserved_6_63 : 58;
1505 u64 num : 6;
1506 } cn61xx;
1507 struct cvmx_pemx_inb_read_credits_cn61xx cn66xx;
1508 struct cvmx_pemx_inb_read_credits_cn61xx cn68xx;
1509 struct cvmx_pemx_inb_read_credits_cn61xx cn70xx;
1510 struct cvmx_pemx_inb_read_credits_cn61xx cn70xxp1;
1511 struct cvmx_pemx_inb_read_credits_s cn73xx;
1512 struct cvmx_pemx_inb_read_credits_s cn78xx;
1513 struct cvmx_pemx_inb_read_credits_s cn78xxp1;
1514 struct cvmx_pemx_inb_read_credits_cn61xx cnf71xx;
1515 struct cvmx_pemx_inb_read_credits_s cnf75xx;
1516 };
1517
1518 typedef union cvmx_pemx_inb_read_credits cvmx_pemx_inb_read_credits_t;
1519
1520 /**
1521 * cvmx_pem#_int_enb
1522 *
1523 * "PEM#_INT_ENB = PEM Interrupt Enable
1524 * Enables interrupt conditions for the PEM to generate an RSL interrupt."
1525 */
1526 union cvmx_pemx_int_enb {
1527 u64 u64;
1528 struct cvmx_pemx_int_enb_s {
1529 u64 reserved_14_63 : 50;
1530 u64 crs_dr : 1;
1531 u64 crs_er : 1;
1532 u64 rdlk : 1;
1533 u64 exc : 1;
1534 u64 un_bx : 1;
1535 u64 un_b2 : 1;
1536 u64 un_b1 : 1;
1537 u64 up_bx : 1;
1538 u64 up_b2 : 1;
1539 u64 up_b1 : 1;
1540 u64 pmem : 1;
1541 u64 pmei : 1;
1542 u64 se : 1;
1543 u64 aeri : 1;
1544 } s;
1545 struct cvmx_pemx_int_enb_s cn61xx;
1546 struct cvmx_pemx_int_enb_s cn63xx;
1547 struct cvmx_pemx_int_enb_s cn63xxp1;
1548 struct cvmx_pemx_int_enb_s cn66xx;
1549 struct cvmx_pemx_int_enb_s cn68xx;
1550 struct cvmx_pemx_int_enb_s cn68xxp1;
1551 struct cvmx_pemx_int_enb_s cn70xx;
1552 struct cvmx_pemx_int_enb_s cn70xxp1;
1553 struct cvmx_pemx_int_enb_s cnf71xx;
1554 };
1555
1556 typedef union cvmx_pemx_int_enb cvmx_pemx_int_enb_t;
1557
1558 /**
1559 * cvmx_pem#_int_enb_int
1560 *
1561 * "PEM#_INT_ENB_INT = PEM Interrupt Enable
1562 * Enables interrupt conditions for the PEM to generate an RSL interrupt."
1563 */
1564 union cvmx_pemx_int_enb_int {
1565 u64 u64;
1566 struct cvmx_pemx_int_enb_int_s {
1567 u64 reserved_14_63 : 50;
1568 u64 crs_dr : 1;
1569 u64 crs_er : 1;
1570 u64 rdlk : 1;
1571 u64 exc : 1;
1572 u64 un_bx : 1;
1573 u64 un_b2 : 1;
1574 u64 un_b1 : 1;
1575 u64 up_bx : 1;
1576 u64 up_b2 : 1;
1577 u64 up_b1 : 1;
1578 u64 pmem : 1;
1579 u64 pmei : 1;
1580 u64 se : 1;
1581 u64 aeri : 1;
1582 } s;
1583 struct cvmx_pemx_int_enb_int_s cn61xx;
1584 struct cvmx_pemx_int_enb_int_s cn63xx;
1585 struct cvmx_pemx_int_enb_int_s cn63xxp1;
1586 struct cvmx_pemx_int_enb_int_s cn66xx;
1587 struct cvmx_pemx_int_enb_int_s cn68xx;
1588 struct cvmx_pemx_int_enb_int_s cn68xxp1;
1589 struct cvmx_pemx_int_enb_int_s cn70xx;
1590 struct cvmx_pemx_int_enb_int_s cn70xxp1;
1591 struct cvmx_pemx_int_enb_int_s cnf71xx;
1592 };
1593
1594 typedef union cvmx_pemx_int_enb_int cvmx_pemx_int_enb_int_t;
1595
1596 /**
1597 * cvmx_pem#_int_sum
1598 *
1599 * This register contains the different interrupt summary bits of the PEM.
1600 *
1601 */
1602 union cvmx_pemx_int_sum {
1603 u64 u64;
1604 struct cvmx_pemx_int_sum_s {
1605 u64 intd : 1;
1606 u64 intc : 1;
1607 u64 intb : 1;
1608 u64 inta : 1;
1609 u64 reserved_14_59 : 46;
1610 u64 crs_dr : 1;
1611 u64 crs_er : 1;
1612 u64 rdlk : 1;
1613 u64 exc : 1;
1614 u64 un_bx : 1;
1615 u64 un_b2 : 1;
1616 u64 un_b1 : 1;
1617 u64 up_bx : 1;
1618 u64 up_b2 : 1;
1619 u64 up_b1 : 1;
1620 u64 pmem : 1;
1621 u64 pmei : 1;
1622 u64 se : 1;
1623 u64 aeri : 1;
1624 } s;
1625 struct cvmx_pemx_int_sum_cn61xx {
1626 u64 reserved_14_63 : 50;
1627 u64 crs_dr : 1;
1628 u64 crs_er : 1;
1629 u64 rdlk : 1;
1630 u64 exc : 1;
1631 u64 un_bx : 1;
1632 u64 un_b2 : 1;
1633 u64 un_b1 : 1;
1634 u64 up_bx : 1;
1635 u64 up_b2 : 1;
1636 u64 up_b1 : 1;
1637 u64 pmem : 1;
1638 u64 pmei : 1;
1639 u64 se : 1;
1640 u64 aeri : 1;
1641 } cn61xx;
1642 struct cvmx_pemx_int_sum_cn61xx cn63xx;
1643 struct cvmx_pemx_int_sum_cn61xx cn63xxp1;
1644 struct cvmx_pemx_int_sum_cn61xx cn66xx;
1645 struct cvmx_pemx_int_sum_cn61xx cn68xx;
1646 struct cvmx_pemx_int_sum_cn61xx cn68xxp1;
1647 struct cvmx_pemx_int_sum_cn61xx cn70xx;
1648 struct cvmx_pemx_int_sum_cn61xx cn70xxp1;
1649 struct cvmx_pemx_int_sum_cn73xx {
1650 u64 intd : 1;
1651 u64 intc : 1;
1652 u64 intb : 1;
1653 u64 inta : 1;
1654 u64 reserved_14_59 : 46;
1655 u64 crs_dr : 1;
1656 u64 crs_er : 1;
1657 u64 rdlk : 1;
1658 u64 reserved_10_10 : 1;
1659 u64 un_bx : 1;
1660 u64 un_b2 : 1;
1661 u64 un_b1 : 1;
1662 u64 up_bx : 1;
1663 u64 up_b2 : 1;
1664 u64 up_b1 : 1;
1665 u64 reserved_3_3 : 1;
1666 u64 pmei : 1;
1667 u64 se : 1;
1668 u64 aeri : 1;
1669 } cn73xx;
1670 struct cvmx_pemx_int_sum_cn73xx cn78xx;
1671 struct cvmx_pemx_int_sum_cn73xx cn78xxp1;
1672 struct cvmx_pemx_int_sum_cn61xx cnf71xx;
1673 struct cvmx_pemx_int_sum_cn73xx cnf75xx;
1674 };
1675
1676 typedef union cvmx_pemx_int_sum cvmx_pemx_int_sum_t;
1677
1678 /**
1679 * cvmx_pem#_on
1680 *
1681 * This register indicates that PEM is configured and ready.
1682 *
1683 */
1684 union cvmx_pemx_on {
1685 u64 u64;
1686 struct cvmx_pemx_on_s {
1687 u64 reserved_2_63 : 62;
1688 u64 pemoor : 1;
1689 u64 pemon : 1;
1690 } s;
1691 struct cvmx_pemx_on_s cn70xx;
1692 struct cvmx_pemx_on_s cn70xxp1;
1693 struct cvmx_pemx_on_s cn73xx;
1694 struct cvmx_pemx_on_s cn78xx;
1695 struct cvmx_pemx_on_s cn78xxp1;
1696 struct cvmx_pemx_on_s cnf75xx;
1697 };
1698
1699 typedef union cvmx_pemx_on cvmx_pemx_on_t;
1700
1701 /**
1702 * cvmx_pem#_p2n_bar0_start
1703 *
1704 * This register specifies the starting address for memory requests that are to be forwarded to
1705 * the SLI in RC mode.
1706 */
1707 union cvmx_pemx_p2n_bar0_start {
1708 u64 u64;
1709 struct cvmx_pemx_p2n_bar0_start_s {
1710 u64 reserved_0_63 : 64;
1711 } s;
1712 struct cvmx_pemx_p2n_bar0_start_cn61xx {
1713 u64 addr : 50;
1714 u64 reserved_0_13 : 14;
1715 } cn61xx;
1716 struct cvmx_pemx_p2n_bar0_start_cn61xx cn63xx;
1717 struct cvmx_pemx_p2n_bar0_start_cn61xx cn63xxp1;
1718 struct cvmx_pemx_p2n_bar0_start_cn61xx cn66xx;
1719 struct cvmx_pemx_p2n_bar0_start_cn61xx cn68xx;
1720 struct cvmx_pemx_p2n_bar0_start_cn61xx cn68xxp1;
1721 struct cvmx_pemx_p2n_bar0_start_cn61xx cn70xx;
1722 struct cvmx_pemx_p2n_bar0_start_cn61xx cn70xxp1;
1723 struct cvmx_pemx_p2n_bar0_start_cn73xx {
1724 u64 addr : 41;
1725 u64 reserved_0_22 : 23;
1726 } cn73xx;
1727 struct cvmx_pemx_p2n_bar0_start_cn73xx cn78xx;
1728 struct cvmx_pemx_p2n_bar0_start_cn78xxp1 {
1729 u64 addr : 49;
1730 u64 reserved_0_14 : 15;
1731 } cn78xxp1;
1732 struct cvmx_pemx_p2n_bar0_start_cn61xx cnf71xx;
1733 struct cvmx_pemx_p2n_bar0_start_cn73xx cnf75xx;
1734 };
1735
1736 typedef union cvmx_pemx_p2n_bar0_start cvmx_pemx_p2n_bar0_start_t;
1737
1738 /**
1739 * cvmx_pem#_p2n_bar1_start
1740 *
1741 * This register specifies the starting address for memory requests that are to be forwarded to
1742 * the SLI in RC mode.
1743 */
1744 union cvmx_pemx_p2n_bar1_start {
1745 u64 u64;
1746 struct cvmx_pemx_p2n_bar1_start_s {
1747 u64 addr : 38;
1748 u64 reserved_0_25 : 26;
1749 } s;
1750 struct cvmx_pemx_p2n_bar1_start_s cn61xx;
1751 struct cvmx_pemx_p2n_bar1_start_s cn63xx;
1752 struct cvmx_pemx_p2n_bar1_start_s cn63xxp1;
1753 struct cvmx_pemx_p2n_bar1_start_s cn66xx;
1754 struct cvmx_pemx_p2n_bar1_start_s cn68xx;
1755 struct cvmx_pemx_p2n_bar1_start_s cn68xxp1;
1756 struct cvmx_pemx_p2n_bar1_start_s cn70xx;
1757 struct cvmx_pemx_p2n_bar1_start_s cn70xxp1;
1758 struct cvmx_pemx_p2n_bar1_start_s cn73xx;
1759 struct cvmx_pemx_p2n_bar1_start_s cn78xx;
1760 struct cvmx_pemx_p2n_bar1_start_s cn78xxp1;
1761 struct cvmx_pemx_p2n_bar1_start_s cnf71xx;
1762 struct cvmx_pemx_p2n_bar1_start_s cnf75xx;
1763 };
1764
1765 typedef union cvmx_pemx_p2n_bar1_start cvmx_pemx_p2n_bar1_start_t;
1766
1767 /**
1768 * cvmx_pem#_p2n_bar2_start
1769 *
1770 * This register specifies the starting address for memory requests that are to be forwarded to
1771 * the SLI in RC mode.
1772 */
1773 union cvmx_pemx_p2n_bar2_start {
1774 u64 u64;
1775 struct cvmx_pemx_p2n_bar2_start_s {
1776 u64 reserved_0_63 : 64;
1777 } s;
1778 struct cvmx_pemx_p2n_bar2_start_cn61xx {
1779 u64 addr : 23;
1780 u64 reserved_0_40 : 41;
1781 } cn61xx;
1782 struct cvmx_pemx_p2n_bar2_start_cn61xx cn63xx;
1783 struct cvmx_pemx_p2n_bar2_start_cn61xx cn63xxp1;
1784 struct cvmx_pemx_p2n_bar2_start_cn61xx cn66xx;
1785 struct cvmx_pemx_p2n_bar2_start_cn61xx cn68xx;
1786 struct cvmx_pemx_p2n_bar2_start_cn61xx cn68xxp1;
1787 struct cvmx_pemx_p2n_bar2_start_cn61xx cn70xx;
1788 struct cvmx_pemx_p2n_bar2_start_cn61xx cn70xxp1;
1789 struct cvmx_pemx_p2n_bar2_start_cn73xx {
1790 u64 addr : 19;
1791 u64 reserved_0_44 : 45;
1792 } cn73xx;
1793 struct cvmx_pemx_p2n_bar2_start_cn73xx cn78xx;
1794 struct cvmx_pemx_p2n_bar2_start_cn73xx cn78xxp1;
1795 struct cvmx_pemx_p2n_bar2_start_cn61xx cnf71xx;
1796 struct cvmx_pemx_p2n_bar2_start_cn73xx cnf75xx;
1797 };
1798
1799 typedef union cvmx_pemx_p2n_bar2_start cvmx_pemx_p2n_bar2_start_t;
1800
1801 /**
1802 * cvmx_pem#_p2p_bar#_end
1803 *
1804 * This register specifies the ending address for memory requests that are to be forwarded to the
1805 * PCIe peer port.
1806 */
1807 union cvmx_pemx_p2p_barx_end {
1808 u64 u64;
1809 struct cvmx_pemx_p2p_barx_end_s {
1810 u64 addr : 52;
1811 u64 reserved_0_11 : 12;
1812 } s;
1813 struct cvmx_pemx_p2p_barx_end_s cn63xx;
1814 struct cvmx_pemx_p2p_barx_end_s cn63xxp1;
1815 struct cvmx_pemx_p2p_barx_end_s cn66xx;
1816 struct cvmx_pemx_p2p_barx_end_s cn68xx;
1817 struct cvmx_pemx_p2p_barx_end_s cn68xxp1;
1818 struct cvmx_pemx_p2p_barx_end_s cn73xx;
1819 struct cvmx_pemx_p2p_barx_end_s cn78xx;
1820 struct cvmx_pemx_p2p_barx_end_s cn78xxp1;
1821 struct cvmx_pemx_p2p_barx_end_s cnf75xx;
1822 };
1823
1824 typedef union cvmx_pemx_p2p_barx_end cvmx_pemx_p2p_barx_end_t;
1825
1826 /**
1827 * cvmx_pem#_p2p_bar#_start
1828 *
1829 * This register specifies the starting address for memory requests that are to be forwarded to
1830 * the PCIe peer port.
1831 */
1832 union cvmx_pemx_p2p_barx_start {
1833 u64 u64;
1834 struct cvmx_pemx_p2p_barx_start_s {
1835 u64 addr : 52;
1836 u64 reserved_2_11 : 10;
1837 u64 dst : 2;
1838 } s;
1839 struct cvmx_pemx_p2p_barx_start_cn63xx {
1840 u64 addr : 52;
1841 u64 reserved_0_11 : 12;
1842 } cn63xx;
1843 struct cvmx_pemx_p2p_barx_start_cn63xx cn63xxp1;
1844 struct cvmx_pemx_p2p_barx_start_cn63xx cn66xx;
1845 struct cvmx_pemx_p2p_barx_start_cn63xx cn68xx;
1846 struct cvmx_pemx_p2p_barx_start_cn63xx cn68xxp1;
1847 struct cvmx_pemx_p2p_barx_start_s cn73xx;
1848 struct cvmx_pemx_p2p_barx_start_s cn78xx;
1849 struct cvmx_pemx_p2p_barx_start_s cn78xxp1;
1850 struct cvmx_pemx_p2p_barx_start_s cnf75xx;
1851 };
1852
1853 typedef union cvmx_pemx_p2p_barx_start cvmx_pemx_p2p_barx_start_t;
1854
1855 /**
1856 * cvmx_pem#_qlm
1857 *
1858 * This register configures the PEM3 QLM.
1859 *
1860 */
1861 union cvmx_pemx_qlm {
1862 u64 u64;
1863 struct cvmx_pemx_qlm_s {
1864 u64 reserved_0_63 : 64;
1865 } s;
1866 struct cvmx_pemx_qlm_cn73xx {
1867 u64 reserved_1_63 : 63;
1868 u64 pemdlmsel : 1;
1869 } cn73xx;
1870 struct cvmx_pemx_qlm_cn78xx {
1871 u64 reserved_1_63 : 63;
1872 u64 pem3qlm : 1;
1873 } cn78xx;
1874 struct cvmx_pemx_qlm_cn78xx cn78xxp1;
1875 struct cvmx_pemx_qlm_cn73xx cnf75xx;
1876 };
1877
1878 typedef union cvmx_pemx_qlm cvmx_pemx_qlm_t;
1879
1880 /**
1881 * cvmx_pem#_spi_ctl
1882 *
1883 * PEM#_SPI_CTL register.
1884 *
1885 */
1886 union cvmx_pemx_spi_ctl {
1887 u64 u64;
1888 struct cvmx_pemx_spi_ctl_s {
1889 u64 reserved_14_63 : 50;
1890 u64 start_busy : 1;
1891 u64 tvalid : 1;
1892 u64 cmd : 3;
1893 u64 adr : 9;
1894 } s;
1895 struct cvmx_pemx_spi_ctl_s cn70xx;
1896 struct cvmx_pemx_spi_ctl_s cn70xxp1;
1897 struct cvmx_pemx_spi_ctl_s cn73xx;
1898 struct cvmx_pemx_spi_ctl_s cn78xx;
1899 struct cvmx_pemx_spi_ctl_s cn78xxp1;
1900 struct cvmx_pemx_spi_ctl_s cnf75xx;
1901 };
1902
1903 typedef union cvmx_pemx_spi_ctl cvmx_pemx_spi_ctl_t;
1904
1905 /**
1906 * cvmx_pem#_spi_data
1907 *
1908 * This register contains the most recently read or written SPI data and is unpredictable upon
1909 * power-up. Is valid after a PEM()_SPI_CTL[CMD]=READ/RDSR when hardware clears
1910 * PEM()_SPI_CTL[START_BUSY]. Is written after a PEM()_SPI_CTL[CMD]=WRITE/WRSR
1911 * when hardware clears PEM()_SPI_CTL[START_BUSY].
1912 */
1913 union cvmx_pemx_spi_data {
1914 u64 u64;
1915 struct cvmx_pemx_spi_data_s {
1916 u64 preamble : 16;
1917 u64 reserved_45_47 : 3;
1918 u64 cs2 : 1;
1919 u64 adr : 12;
1920 u64 data : 32;
1921 } s;
1922 struct cvmx_pemx_spi_data_s cn70xx;
1923 struct cvmx_pemx_spi_data_s cn70xxp1;
1924 struct cvmx_pemx_spi_data_s cn73xx;
1925 struct cvmx_pemx_spi_data_s cn78xx;
1926 struct cvmx_pemx_spi_data_s cn78xxp1;
1927 struct cvmx_pemx_spi_data_s cnf75xx;
1928 };
1929
1930 typedef union cvmx_pemx_spi_data cvmx_pemx_spi_data_t;
1931
1932 /**
1933 * cvmx_pem#_strap
1934 *
1935 * "Below are in pesc_csr
1936 * The input strapping pins"
1937 */
1938 union cvmx_pemx_strap {
1939 u64 u64;
1940 struct cvmx_pemx_strap_s {
1941 u64 reserved_5_63 : 59;
1942 u64 miopem2dlm5sel : 1;
1943 u64 pilaneswap : 1;
1944 u64 reserved_0_2 : 3;
1945 } s;
1946 struct cvmx_pemx_strap_cn70xx {
1947 u64 reserved_4_63 : 60;
1948 u64 pilaneswap : 1;
1949 u64 pimode : 3;
1950 } cn70xx;
1951 struct cvmx_pemx_strap_cn70xx cn70xxp1;
1952 struct cvmx_pemx_strap_cn73xx {
1953 u64 reserved_5_63 : 59;
1954 u64 miopem2dlm5sel : 1;
1955 u64 pilaneswap : 1;
1956 u64 pilanes8 : 1;
1957 u64 pimode : 2;
1958 } cn73xx;
1959 struct cvmx_pemx_strap_cn78xx {
1960 u64 reserved_4_63 : 60;
1961 u64 pilaneswap : 1;
1962 u64 pilanes8 : 1;
1963 u64 pimode : 2;
1964 } cn78xx;
1965 struct cvmx_pemx_strap_cn78xx cn78xxp1;
1966 struct cvmx_pemx_strap_cnf75xx {
1967 u64 reserved_5_63 : 59;
1968 u64 miopem2dlm5sel : 1;
1969 u64 pilaneswap : 1;
1970 u64 pilanes4 : 1;
1971 u64 pimode : 2;
1972 } cnf75xx;
1973 };
1974
1975 typedef union cvmx_pemx_strap cvmx_pemx_strap_t;
1976
1977 /**
1978 * cvmx_pem#_tlp_credits
1979 *
1980 * This register specifies the number of credits for use in moving TLPs. When this register is
1981 * written, the credit values are reset to the register value. A write to this register should
1982 * take place before traffic flow starts.
1983 */
1984 union cvmx_pemx_tlp_credits {
1985 u64 u64;
1986 struct cvmx_pemx_tlp_credits_s {
1987 u64 reserved_56_63 : 8;
1988 u64 peai_ppf : 8;
1989 u64 pem_cpl : 8;
1990 u64 pem_np : 8;
1991 u64 pem_p : 8;
1992 u64 sli_cpl : 8;
1993 u64 sli_np : 8;
1994 u64 sli_p : 8;
1995 } s;
1996 struct cvmx_pemx_tlp_credits_cn61xx {
1997 u64 reserved_56_63 : 8;
1998 u64 peai_ppf : 8;
1999 u64 reserved_24_47 : 24;
2000 u64 sli_cpl : 8;
2001 u64 sli_np : 8;
2002 u64 sli_p : 8;
2003 } cn61xx;
2004 struct cvmx_pemx_tlp_credits_s cn63xx;
2005 struct cvmx_pemx_tlp_credits_s cn63xxp1;
2006 struct cvmx_pemx_tlp_credits_s cn66xx;
2007 struct cvmx_pemx_tlp_credits_s cn68xx;
2008 struct cvmx_pemx_tlp_credits_s cn68xxp1;
2009 struct cvmx_pemx_tlp_credits_cn61xx cn70xx;
2010 struct cvmx_pemx_tlp_credits_cn61xx cn70xxp1;
2011 struct cvmx_pemx_tlp_credits_cn73xx {
2012 u64 reserved_48_63 : 16;
2013 u64 pem_cpl : 8;
2014 u64 pem_np : 8;
2015 u64 pem_p : 8;
2016 u64 sli_cpl : 8;
2017 u64 sli_np : 8;
2018 u64 sli_p : 8;
2019 } cn73xx;
2020 struct cvmx_pemx_tlp_credits_cn73xx cn78xx;
2021 struct cvmx_pemx_tlp_credits_cn73xx cn78xxp1;
2022 struct cvmx_pemx_tlp_credits_cn61xx cnf71xx;
2023 struct cvmx_pemx_tlp_credits_cn73xx cnf75xx;
2024 };
2025
2026 typedef union cvmx_pemx_tlp_credits cvmx_pemx_tlp_credits_t;
2027
2028 #endif
2029