1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (C) 2020 Marvell International Ltd.
4 *
5 * Configuration and status register (CSR) type definitions for
6 * Octeon sso.
7 */
8
9 #ifndef __CVMX_SSO_DEFS_H__
10 #define __CVMX_SSO_DEFS_H__
11
12 #define CVMX_SSO_ACTIVE_CYCLES (0x00016700000010E8ull)
13 #define CVMX_SSO_ACTIVE_CYCLESX(offset) (0x0001670000001100ull + ((offset) & 3) * 8)
14 #define CVMX_SSO_AW_ADD (0x0001670000002080ull)
15 #define CVMX_SSO_AW_CFG (0x00016700000010F0ull)
16 #define CVMX_SSO_AW_ECO (0x0001670000001030ull)
17 #define CVMX_SSO_AW_READ_ARB (0x0001670000002090ull)
18 #define CVMX_SSO_AW_STATUS (0x00016700000010E0ull)
19 #define CVMX_SSO_AW_TAG_LATENCY_PC (0x00016700000020A8ull)
20 #define CVMX_SSO_AW_TAG_REQ_PC (0x00016700000020A0ull)
21 #define CVMX_SSO_AW_WE (0x0001670000001080ull)
22 #define CVMX_SSO_BIST_STAT (0x0001670000001078ull)
23 #define CVMX_SSO_BIST_STATUS0 (0x0001670000001200ull)
24 #define CVMX_SSO_BIST_STATUS1 (0x0001670000001208ull)
25 #define CVMX_SSO_BIST_STATUS2 (0x0001670000001210ull)
26 #define CVMX_SSO_CFG (0x0001670000001088ull)
27 #define CVMX_SSO_DS_PC (0x0001670000001070ull)
28 #define CVMX_SSO_ECC_CTL0 (0x0001670000001280ull)
29 #define CVMX_SSO_ECC_CTL1 (0x0001670000001288ull)
30 #define CVMX_SSO_ECC_CTL2 (0x0001670000001290ull)
31 #define CVMX_SSO_ERR (0x0001670000001038ull)
32 #define CVMX_SSO_ERR0 (0x0001670000001240ull)
33 #define CVMX_SSO_ERR1 (0x0001670000001248ull)
34 #define CVMX_SSO_ERR2 (0x0001670000001250ull)
35 #define CVMX_SSO_ERR_ENB (0x0001670000001030ull)
36 #define CVMX_SSO_FIDX_ECC_CTL (0x00016700000010D0ull)
37 #define CVMX_SSO_FIDX_ECC_ST (0x00016700000010D8ull)
38 #define CVMX_SSO_FPAGE_CNT (0x0001670000001090ull)
39 #define CVMX_SSO_GRPX_AQ_CNT(offset) (0x0001670020000700ull + ((offset) & 255) * 0x10000ull)
40 #define CVMX_SSO_GRPX_AQ_THR(offset) (0x0001670020000800ull + ((offset) & 255) * 0x10000ull)
41 #define CVMX_SSO_GRPX_DS_PC(offset) (0x0001670020001400ull + ((offset) & 255) * 0x10000ull)
42 #define CVMX_SSO_GRPX_EXT_PC(offset) (0x0001670020001100ull + ((offset) & 255) * 0x10000ull)
43 #define CVMX_SSO_GRPX_IAQ_THR(offset) (0x0001670020000000ull + ((offset) & 255) * 0x10000ull)
44 #define CVMX_SSO_GRPX_INT(offset) (0x0001670020000400ull + ((offset) & 255) * 0x10000ull)
45 #define CVMX_SSO_GRPX_INT_CNT(offset) (0x0001670020000600ull + ((offset) & 255) * 0x10000ull)
46 #define CVMX_SSO_GRPX_INT_THR(offset) (0x0001670020000500ull + ((offset) & 255) * 0x10000ull)
47 #define CVMX_SSO_GRPX_PRI(offset) (0x0001670020000200ull + ((offset) & 255) * 0x10000ull)
48 #define CVMX_SSO_GRPX_TAQ_THR(offset) (0x0001670020000100ull + ((offset) & 255) * 0x10000ull)
49 #define CVMX_SSO_GRPX_TS_PC(offset) (0x0001670020001300ull + ((offset) & 255) * 0x10000ull)
50 #define CVMX_SSO_GRPX_WA_PC(offset) (0x0001670020001200ull + ((offset) & 255) * 0x10000ull)
51 #define CVMX_SSO_GRPX_WS_PC(offset) (0x0001670020001000ull + ((offset) & 255) * 0x10000ull)
52 #define CVMX_SSO_GWE_CFG (0x0001670000001098ull)
53 #define CVMX_SSO_GWE_RANDOM (0x00016700000010B0ull)
54 #define CVMX_SSO_GW_ECO (0x0001670000001038ull)
55 #define CVMX_SSO_IDX_ECC_CTL (0x00016700000010C0ull)
56 #define CVMX_SSO_IDX_ECC_ST (0x00016700000010C8ull)
57 #define CVMX_SSO_IENTX_LINKS(offset) (0x00016700A0060000ull + ((offset) & 4095) * 8)
58 #define CVMX_SSO_IENTX_PENDTAG(offset) (0x00016700A0040000ull + ((offset) & 4095) * 8)
59 #define CVMX_SSO_IENTX_QLINKS(offset) (0x00016700A0080000ull + ((offset) & 4095) * 8)
60 #define CVMX_SSO_IENTX_TAG(offset) (0x00016700A0000000ull + ((offset) & 4095) * 8)
61 #define CVMX_SSO_IENTX_WQPGRP(offset) (0x00016700A0020000ull + ((offset) & 4095) * 8)
62 #define CVMX_SSO_IPL_CONFX(offset) (0x0001670080080000ull + ((offset) & 255) * 8)
63 #define CVMX_SSO_IPL_DESCHEDX(offset) (0x0001670080060000ull + ((offset) & 255) * 8)
64 #define CVMX_SSO_IPL_FREEX(offset) (0x0001670080000000ull + ((offset) & 7) * 8)
65 #define CVMX_SSO_IPL_IAQX(offset) (0x0001670080040000ull + ((offset) & 255) * 8)
66 #define CVMX_SSO_IQ_CNTX(offset) (0x0001670000009000ull + ((offset) & 7) * 8)
67 #define CVMX_SSO_IQ_COM_CNT (0x0001670000001058ull)
68 #define CVMX_SSO_IQ_INT (0x0001670000001048ull)
69 #define CVMX_SSO_IQ_INT_EN (0x0001670000001050ull)
70 #define CVMX_SSO_IQ_THRX(offset) (0x000167000000A000ull + ((offset) & 7) * 8)
71 #define CVMX_SSO_NOS_CNT (0x0001670000001040ull)
72 #define CVMX_SSO_NW_TIM (0x0001670000001028ull)
73 #define CVMX_SSO_OTH_ECC_CTL (0x00016700000010B0ull)
74 #define CVMX_SSO_OTH_ECC_ST (0x00016700000010B8ull)
75 #define CVMX_SSO_PAGE_CNT (0x0001670000001090ull)
76 #define CVMX_SSO_PND_ECC_CTL (0x00016700000010A0ull)
77 #define CVMX_SSO_PND_ECC_ST (0x00016700000010A8ull)
78 #define CVMX_SSO_PPX_ARB(offset) (0x0001670040000000ull + ((offset) & 63) * 0x10000ull)
79 #define CVMX_SSO_PPX_GRP_MSK(offset) (0x0001670000006000ull + ((offset) & 31) * 8)
80 #define CVMX_SSO_PPX_QOS_PRI(offset) (0x0001670000003000ull + ((offset) & 31) * 8)
81 #define CVMX_SSO_PPX_SX_GRPMSKX(a, b, c) \
82 (0x0001670040001000ull + ((a) << 16) + ((b) << 5) + ((c) << 3))
83 #define CVMX_SSO_PP_STRICT (0x00016700000010E0ull)
84 #define CVMX_SSO_QOSX_RND(offset) (0x0001670000002000ull + ((offset) & 7) * 8)
85 #define CVMX_SSO_QOS_THRX(offset) (0x000167000000B000ull + ((offset) & 7) * 8)
86 #define CVMX_SSO_QOS_WE (0x0001670000001080ull)
87 #define CVMX_SSO_RESET CVMX_SSO_RESET_FUNC()
CVMX_SSO_RESET_FUNC(void)88 static inline u64 CVMX_SSO_RESET_FUNC(void)
89 {
90 switch (cvmx_get_octeon_family()) {
91 case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
92 case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
93 if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
94 return 0x00016700000010F8ull;
95 if (OCTEON_IS_MODEL(OCTEON_CN78XX))
96 return 0x00016700000010F8ull;
97 case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
98 return 0x00016700000010F8ull;
99 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
100 return 0x00016700000010F0ull;
101 }
102 return 0x00016700000010F8ull;
103 }
104
105 #define CVMX_SSO_RWQ_HEAD_PTRX(offset) (0x000167000000C000ull + ((offset) & 7) * 8)
106 #define CVMX_SSO_RWQ_POP_FPTR (0x000167000000C408ull)
107 #define CVMX_SSO_RWQ_PSH_FPTR (0x000167000000C400ull)
108 #define CVMX_SSO_RWQ_TAIL_PTRX(offset) (0x000167000000C200ull + ((offset) & 7) * 8)
109 #define CVMX_SSO_SL_PPX_LINKS(offset) (0x0001670060000040ull + ((offset) & 63) * 0x10000ull)
110 #define CVMX_SSO_SL_PPX_PENDTAG(offset) (0x0001670060000000ull + ((offset) & 63) * 0x10000ull)
111 #define CVMX_SSO_SL_PPX_PENDWQP(offset) (0x0001670060000010ull + ((offset) & 63) * 0x10000ull)
112 #define CVMX_SSO_SL_PPX_TAG(offset) (0x0001670060000020ull + ((offset) & 63) * 0x10000ull)
113 #define CVMX_SSO_SL_PPX_WQP(offset) (0x0001670060000030ull + ((offset) & 63) * 0x10000ull)
114 #define CVMX_SSO_TAQX_LINK(offset) (0x00016700C0000000ull + ((offset) & 2047) * 4096)
115 #define CVMX_SSO_TAQX_WAEX_TAG(offset, block_id) \
116 (0x00016700D0000000ull + (((offset) & 15) + ((block_id) & 2047) * 0x100ull) * 16)
117 #define CVMX_SSO_TAQX_WAEX_WQP(offset, block_id) \
118 (0x00016700D0000008ull + (((offset) & 15) + ((block_id) & 2047) * 0x100ull) * 16)
119 #define CVMX_SSO_TAQ_ADD (0x00016700000020E0ull)
120 #define CVMX_SSO_TAQ_CNT (0x00016700000020C0ull)
121 #define CVMX_SSO_TIAQX_STATUS(offset) (0x00016700000C0000ull + ((offset) & 255) * 8)
122 #define CVMX_SSO_TOAQX_STATUS(offset) (0x00016700000D0000ull + ((offset) & 255) * 8)
123 #define CVMX_SSO_TS_PC (0x0001670000001068ull)
124 #define CVMX_SSO_WA_COM_PC (0x0001670000001060ull)
125 #define CVMX_SSO_WA_PCX(offset) (0x0001670000005000ull + ((offset) & 7) * 8)
126 #define CVMX_SSO_WQ_INT (0x0001670000001000ull)
127 #define CVMX_SSO_WQ_INT_CNTX(offset) (0x0001670000008000ull + ((offset) & 63) * 8)
128 #define CVMX_SSO_WQ_INT_PC (0x0001670000001020ull)
129 #define CVMX_SSO_WQ_INT_THRX(offset) (0x0001670000007000ull + ((offset) & 63) * 8)
130 #define CVMX_SSO_WQ_IQ_DIS (0x0001670000001010ull)
131 #define CVMX_SSO_WS_CFG (0x0001670000001088ull)
132 #define CVMX_SSO_WS_ECO (0x0001670000001048ull)
133 #define CVMX_SSO_WS_PCX(offset) (0x0001670000004000ull + ((offset) & 63) * 8)
134 #define CVMX_SSO_XAQX_HEAD_NEXT(offset) (0x00016700000A0000ull + ((offset) & 255) * 8)
135 #define CVMX_SSO_XAQX_HEAD_PTR(offset) (0x0001670000080000ull + ((offset) & 255) * 8)
136 #define CVMX_SSO_XAQX_TAIL_NEXT(offset) (0x00016700000B0000ull + ((offset) & 255) * 8)
137 #define CVMX_SSO_XAQX_TAIL_PTR(offset) (0x0001670000090000ull + ((offset) & 255) * 8)
138 #define CVMX_SSO_XAQ_AURA (0x0001670000002100ull)
139 #define CVMX_SSO_XAQ_LATENCY_PC (0x00016700000020B8ull)
140 #define CVMX_SSO_XAQ_REQ_PC (0x00016700000020B0ull)
141
142 /**
143 * cvmx_sso_active_cycles
144 *
145 * SSO_ACTIVE_CYCLES = SSO cycles SSO active
146 *
147 * This register counts every sclk cycle that the SSO clocks are active.
148 * **NOTE: Added in pass 2.0
149 */
150 union cvmx_sso_active_cycles {
151 u64 u64;
152 struct cvmx_sso_active_cycles_s {
153 u64 act_cyc : 64;
154 } s;
155 struct cvmx_sso_active_cycles_s cn68xx;
156 };
157
158 typedef union cvmx_sso_active_cycles cvmx_sso_active_cycles_t;
159
160 /**
161 * cvmx_sso_active_cycles#
162 *
163 * This register counts every coprocessor clock (SCLK) cycle that the SSO clocks are active.
164 *
165 */
166 union cvmx_sso_active_cyclesx {
167 u64 u64;
168 struct cvmx_sso_active_cyclesx_s {
169 u64 act_cyc : 64;
170 } s;
171 struct cvmx_sso_active_cyclesx_s cn73xx;
172 struct cvmx_sso_active_cyclesx_s cn78xx;
173 struct cvmx_sso_active_cyclesx_s cn78xxp1;
174 struct cvmx_sso_active_cyclesx_s cnf75xx;
175 };
176
177 typedef union cvmx_sso_active_cyclesx cvmx_sso_active_cyclesx_t;
178
179 /**
180 * cvmx_sso_aw_add
181 */
182 union cvmx_sso_aw_add {
183 u64 u64;
184 struct cvmx_sso_aw_add_s {
185 u64 reserved_30_63 : 34;
186 u64 rsvd_free : 14;
187 u64 reserved_0_15 : 16;
188 } s;
189 struct cvmx_sso_aw_add_s cn73xx;
190 struct cvmx_sso_aw_add_s cn78xx;
191 struct cvmx_sso_aw_add_s cn78xxp1;
192 struct cvmx_sso_aw_add_s cnf75xx;
193 };
194
195 typedef union cvmx_sso_aw_add cvmx_sso_aw_add_t;
196
197 /**
198 * cvmx_sso_aw_cfg
199 *
200 * This register controls the operation of the add-work block (AW).
201 *
202 */
203 union cvmx_sso_aw_cfg {
204 u64 u64;
205 struct cvmx_sso_aw_cfg_s {
206 u64 reserved_9_63 : 55;
207 u64 ldt_short : 1;
208 u64 lol : 1;
209 u64 xaq_alloc_dis : 1;
210 u64 ocla_bp : 1;
211 u64 xaq_byp_dis : 1;
212 u64 stt : 1;
213 u64 ldt : 1;
214 u64 ldwb : 1;
215 u64 rwen : 1;
216 } s;
217 struct cvmx_sso_aw_cfg_s cn73xx;
218 struct cvmx_sso_aw_cfg_s cn78xx;
219 struct cvmx_sso_aw_cfg_s cn78xxp1;
220 struct cvmx_sso_aw_cfg_s cnf75xx;
221 };
222
223 typedef union cvmx_sso_aw_cfg cvmx_sso_aw_cfg_t;
224
225 /**
226 * cvmx_sso_aw_eco
227 */
228 union cvmx_sso_aw_eco {
229 u64 u64;
230 struct cvmx_sso_aw_eco_s {
231 u64 reserved_8_63 : 56;
232 u64 eco_rw : 8;
233 } s;
234 struct cvmx_sso_aw_eco_s cn73xx;
235 struct cvmx_sso_aw_eco_s cnf75xx;
236 };
237
238 typedef union cvmx_sso_aw_eco cvmx_sso_aw_eco_t;
239
240 /**
241 * cvmx_sso_aw_read_arb
242 *
243 * This register fine tunes the AW read arbiter and is for diagnostic use.
244 *
245 */
246 union cvmx_sso_aw_read_arb {
247 u64 u64;
248 struct cvmx_sso_aw_read_arb_s {
249 u64 reserved_30_63 : 34;
250 u64 xaq_lev : 6;
251 u64 reserved_21_23 : 3;
252 u64 xaq_min : 5;
253 u64 reserved_14_15 : 2;
254 u64 aw_tag_lev : 6;
255 u64 reserved_5_7 : 3;
256 u64 aw_tag_min : 5;
257 } s;
258 struct cvmx_sso_aw_read_arb_s cn73xx;
259 struct cvmx_sso_aw_read_arb_s cn78xx;
260 struct cvmx_sso_aw_read_arb_s cn78xxp1;
261 struct cvmx_sso_aw_read_arb_s cnf75xx;
262 };
263
264 typedef union cvmx_sso_aw_read_arb cvmx_sso_aw_read_arb_t;
265
266 /**
267 * cvmx_sso_aw_status
268 *
269 * This register indicates the status of the add-work block (AW).
270 *
271 */
272 union cvmx_sso_aw_status {
273 u64 u64;
274 struct cvmx_sso_aw_status_s {
275 u64 reserved_6_63 : 58;
276 u64 xaq_buf_cached : 6;
277 } s;
278 struct cvmx_sso_aw_status_s cn73xx;
279 struct cvmx_sso_aw_status_s cn78xx;
280 struct cvmx_sso_aw_status_s cn78xxp1;
281 struct cvmx_sso_aw_status_s cnf75xx;
282 };
283
284 typedef union cvmx_sso_aw_status cvmx_sso_aw_status_t;
285
286 /**
287 * cvmx_sso_aw_tag_latency_pc
288 */
289 union cvmx_sso_aw_tag_latency_pc {
290 u64 u64;
291 struct cvmx_sso_aw_tag_latency_pc_s {
292 u64 count : 64;
293 } s;
294 struct cvmx_sso_aw_tag_latency_pc_s cn73xx;
295 struct cvmx_sso_aw_tag_latency_pc_s cn78xx;
296 struct cvmx_sso_aw_tag_latency_pc_s cn78xxp1;
297 struct cvmx_sso_aw_tag_latency_pc_s cnf75xx;
298 };
299
300 typedef union cvmx_sso_aw_tag_latency_pc cvmx_sso_aw_tag_latency_pc_t;
301
302 /**
303 * cvmx_sso_aw_tag_req_pc
304 */
305 union cvmx_sso_aw_tag_req_pc {
306 u64 u64;
307 struct cvmx_sso_aw_tag_req_pc_s {
308 u64 count : 64;
309 } s;
310 struct cvmx_sso_aw_tag_req_pc_s cn73xx;
311 struct cvmx_sso_aw_tag_req_pc_s cn78xx;
312 struct cvmx_sso_aw_tag_req_pc_s cn78xxp1;
313 struct cvmx_sso_aw_tag_req_pc_s cnf75xx;
314 };
315
316 typedef union cvmx_sso_aw_tag_req_pc cvmx_sso_aw_tag_req_pc_t;
317
318 /**
319 * cvmx_sso_aw_we
320 */
321 union cvmx_sso_aw_we {
322 u64 u64;
323 struct cvmx_sso_aw_we_s {
324 u64 reserved_29_63 : 35;
325 u64 rsvd_free : 13;
326 u64 reserved_13_15 : 3;
327 u64 free_cnt : 13;
328 } s;
329 struct cvmx_sso_aw_we_s cn73xx;
330 struct cvmx_sso_aw_we_s cn78xx;
331 struct cvmx_sso_aw_we_s cn78xxp1;
332 struct cvmx_sso_aw_we_s cnf75xx;
333 };
334
335 typedef union cvmx_sso_aw_we cvmx_sso_aw_we_t;
336
337 /**
338 * cvmx_sso_bist_stat
339 *
340 * SSO_BIST_STAT = SSO BIST Status Register
341 *
342 * Contains the BIST status for the SSO memories ('0' = pass, '1' = fail).
343 * Note that PP BIST status is not reported here as it was in previous designs.
344 *
345 * There may be more for DDR interface buffers.
346 * It's possible that a RAM will be used for SSO_PP_QOS_RND.
347 */
348 union cvmx_sso_bist_stat {
349 u64 u64;
350 struct cvmx_sso_bist_stat_s {
351 u64 reserved_62_63 : 2;
352 u64 odu_pref : 2;
353 u64 reserved_54_59 : 6;
354 u64 fptr : 2;
355 u64 reserved_45_51 : 7;
356 u64 rwo_dat : 1;
357 u64 rwo : 2;
358 u64 reserved_35_41 : 7;
359 u64 rwi_dat : 1;
360 u64 reserved_32_33 : 2;
361 u64 soc : 1;
362 u64 reserved_28_30 : 3;
363 u64 ncbo : 4;
364 u64 reserved_21_23 : 3;
365 u64 index : 1;
366 u64 reserved_17_19 : 3;
367 u64 fidx : 1;
368 u64 reserved_10_15 : 6;
369 u64 pend : 2;
370 u64 reserved_2_7 : 6;
371 u64 oth : 2;
372 } s;
373 struct cvmx_sso_bist_stat_s cn68xx;
374 struct cvmx_sso_bist_stat_cn68xxp1 {
375 u64 reserved_54_63 : 10;
376 u64 fptr : 2;
377 u64 reserved_45_51 : 7;
378 u64 rwo_dat : 1;
379 u64 rwo : 2;
380 u64 reserved_35_41 : 7;
381 u64 rwi_dat : 1;
382 u64 reserved_32_33 : 2;
383 u64 soc : 1;
384 u64 reserved_28_30 : 3;
385 u64 ncbo : 4;
386 u64 reserved_21_23 : 3;
387 u64 index : 1;
388 u64 reserved_17_19 : 3;
389 u64 fidx : 1;
390 u64 reserved_10_15 : 6;
391 u64 pend : 2;
392 u64 reserved_2_7 : 6;
393 u64 oth : 2;
394 } cn68xxp1;
395 };
396
397 typedef union cvmx_sso_bist_stat cvmx_sso_bist_stat_t;
398
399 /**
400 * cvmx_sso_bist_status0
401 *
402 * Contains the BIST status for the SSO memories.
403 *
404 */
405 union cvmx_sso_bist_status0 {
406 u64 u64;
407 struct cvmx_sso_bist_status0_s {
408 u64 reserved_10_63 : 54;
409 u64 bist : 10;
410 } s;
411 struct cvmx_sso_bist_status0_s cn73xx;
412 struct cvmx_sso_bist_status0_s cn78xx;
413 struct cvmx_sso_bist_status0_s cn78xxp1;
414 struct cvmx_sso_bist_status0_s cnf75xx;
415 };
416
417 typedef union cvmx_sso_bist_status0 cvmx_sso_bist_status0_t;
418
419 /**
420 * cvmx_sso_bist_status1
421 *
422 * Contains the BIST status for the SSO memories.
423 *
424 */
425 union cvmx_sso_bist_status1 {
426 u64 u64;
427 struct cvmx_sso_bist_status1_s {
428 u64 reserved_7_63 : 57;
429 u64 bist : 7;
430 } s;
431 struct cvmx_sso_bist_status1_s cn73xx;
432 struct cvmx_sso_bist_status1_s cn78xx;
433 struct cvmx_sso_bist_status1_s cn78xxp1;
434 struct cvmx_sso_bist_status1_s cnf75xx;
435 };
436
437 typedef union cvmx_sso_bist_status1 cvmx_sso_bist_status1_t;
438
439 /**
440 * cvmx_sso_bist_status2
441 *
442 * Contains the BIST status for the SSO memories.
443 *
444 */
445 union cvmx_sso_bist_status2 {
446 u64 u64;
447 struct cvmx_sso_bist_status2_s {
448 u64 reserved_9_63 : 55;
449 u64 bist : 9;
450 } s;
451 struct cvmx_sso_bist_status2_s cn73xx;
452 struct cvmx_sso_bist_status2_s cn78xx;
453 struct cvmx_sso_bist_status2_s cn78xxp1;
454 struct cvmx_sso_bist_status2_s cnf75xx;
455 };
456
457 typedef union cvmx_sso_bist_status2 cvmx_sso_bist_status2_t;
458
459 /**
460 * cvmx_sso_cfg
461 *
462 * SSO_CFG = SSO Config
463 *
464 * This register is an assortment of various SSO configuration bits.
465 */
466 union cvmx_sso_cfg {
467 u64 u64;
468 struct cvmx_sso_cfg_s {
469 u64 reserved_16_63 : 48;
470 u64 qck_gw_rsp_adj : 3;
471 u64 qck_gw_rsp_dis : 1;
472 u64 qck_sw_dis : 1;
473 u64 rwq_alloc_dis : 1;
474 u64 soc_ccam_dis : 1;
475 u64 sso_cclk_dis : 1;
476 u64 rwo_flush : 1;
477 u64 wfe_thr : 1;
478 u64 rwio_byp_dis : 1;
479 u64 rwq_byp_dis : 1;
480 u64 stt : 1;
481 u64 ldt : 1;
482 u64 dwb : 1;
483 u64 rwen : 1;
484 } s;
485 struct cvmx_sso_cfg_s cn68xx;
486 struct cvmx_sso_cfg_cn68xxp1 {
487 u64 reserved_8_63 : 56;
488 u64 rwo_flush : 1;
489 u64 wfe_thr : 1;
490 u64 rwio_byp_dis : 1;
491 u64 rwq_byp_dis : 1;
492 u64 stt : 1;
493 u64 ldt : 1;
494 u64 dwb : 1;
495 u64 rwen : 1;
496 } cn68xxp1;
497 };
498
499 typedef union cvmx_sso_cfg cvmx_sso_cfg_t;
500
501 /**
502 * cvmx_sso_ds_pc
503 *
504 * SSO_DS_PC = SSO De-Schedule Performance Counter
505 *
506 * Counts the number of de-schedule requests.
507 * Counter rolls over through zero when max value exceeded.
508 */
509 union cvmx_sso_ds_pc {
510 u64 u64;
511 struct cvmx_sso_ds_pc_s {
512 u64 ds_pc : 64;
513 } s;
514 struct cvmx_sso_ds_pc_s cn68xx;
515 struct cvmx_sso_ds_pc_s cn68xxp1;
516 };
517
518 typedef union cvmx_sso_ds_pc cvmx_sso_ds_pc_t;
519
520 /**
521 * cvmx_sso_ecc_ctl0
522 */
523 union cvmx_sso_ecc_ctl0 {
524 u64 u64;
525 struct cvmx_sso_ecc_ctl0_s {
526 u64 reserved_30_63 : 34;
527 u64 toaqt_flip : 2;
528 u64 toaqt_cdis : 1;
529 u64 toaqh_flip : 2;
530 u64 toaqh_cdis : 1;
531 u64 tiaqt_flip : 2;
532 u64 tiaqt_cdis : 1;
533 u64 tiaqh_flip : 2;
534 u64 tiaqh_cdis : 1;
535 u64 llm_flip : 2;
536 u64 llm_cdis : 1;
537 u64 inp_flip : 2;
538 u64 inp_cdis : 1;
539 u64 qtc_flip : 2;
540 u64 qtc_cdis : 1;
541 u64 xaq_flip : 2;
542 u64 xaq_cdis : 1;
543 u64 fff_flip : 2;
544 u64 fff_cdis : 1;
545 u64 wes_flip : 2;
546 u64 wes_cdis : 1;
547 } s;
548 struct cvmx_sso_ecc_ctl0_s cn73xx;
549 struct cvmx_sso_ecc_ctl0_s cn78xx;
550 struct cvmx_sso_ecc_ctl0_s cn78xxp1;
551 struct cvmx_sso_ecc_ctl0_s cnf75xx;
552 };
553
554 typedef union cvmx_sso_ecc_ctl0 cvmx_sso_ecc_ctl0_t;
555
556 /**
557 * cvmx_sso_ecc_ctl1
558 */
559 union cvmx_sso_ecc_ctl1 {
560 u64 u64;
561 struct cvmx_sso_ecc_ctl1_s {
562 u64 reserved_21_63 : 43;
563 u64 thrint_flip : 2;
564 u64 thrint_cdis : 1;
565 u64 mask_flip : 2;
566 u64 mask_cdis : 1;
567 u64 gdw_flip : 2;
568 u64 gdw_cdis : 1;
569 u64 qidx_flip : 2;
570 u64 qidx_cdis : 1;
571 u64 tptr_flip : 2;
572 u64 tptr_cdis : 1;
573 u64 hptr_flip : 2;
574 u64 hptr_cdis : 1;
575 u64 cntr_flip : 2;
576 u64 cntr_cdis : 1;
577 } s;
578 struct cvmx_sso_ecc_ctl1_s cn73xx;
579 struct cvmx_sso_ecc_ctl1_s cn78xx;
580 struct cvmx_sso_ecc_ctl1_s cn78xxp1;
581 struct cvmx_sso_ecc_ctl1_s cnf75xx;
582 };
583
584 typedef union cvmx_sso_ecc_ctl1 cvmx_sso_ecc_ctl1_t;
585
586 /**
587 * cvmx_sso_ecc_ctl2
588 */
589 union cvmx_sso_ecc_ctl2 {
590 u64 u64;
591 struct cvmx_sso_ecc_ctl2_s {
592 u64 reserved_15_63 : 49;
593 u64 ncbo_flip : 2;
594 u64 ncbo_cdis : 1;
595 u64 pnd_flip : 2;
596 u64 pnd_cdis : 1;
597 u64 oth_flip : 2;
598 u64 oth_cdis : 1;
599 u64 nidx_flip : 2;
600 u64 nidx_cdis : 1;
601 u64 pidx_flip : 2;
602 u64 pidx_cdis : 1;
603 } s;
604 struct cvmx_sso_ecc_ctl2_s cn73xx;
605 struct cvmx_sso_ecc_ctl2_s cn78xx;
606 struct cvmx_sso_ecc_ctl2_s cn78xxp1;
607 struct cvmx_sso_ecc_ctl2_s cnf75xx;
608 };
609
610 typedef union cvmx_sso_ecc_ctl2 cvmx_sso_ecc_ctl2_t;
611
612 /**
613 * cvmx_sso_err
614 *
615 * SSO_ERR = SSO Error Register
616 *
617 * Contains ECC and other misc error bits.
618 *
619 * <45> The free page error bit will assert when SSO_FPAGE_CNT <= 16 and
620 * SSO_CFG[RWEN] is 1. Software will want to disable the interrupt
621 * associated with this error when recovering SSO pointers from the
622 * FPA and SSO.
623 *
624 * This register also contains the illegal operation error bits:
625 *
626 * <42> Received ADDWQ with tag specified as EMPTY
627 * <41> Received illegal opcode
628 * <40> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/ALLOC_WE
629 * from WS with CLR_NSCHED pending
630 * <39> Received CLR_NSCHED
631 * from WS with SWTAG_DESCH/DESCH/CLR_NSCHED pending
632 * <38> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/ALLOC_WE
633 * from WS with ALLOC_WE pending
634 * <37> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/ALLOC_WE/CLR_NSCHED
635 * from WS with GET_WORK pending
636 * <36> Received SWTAG_FULL/SWTAG_DESCH
637 * with tag specified as UNSCHEDULED
638 * <35> Received SWTAG/SWTAG_FULL/SWTAG_DESCH
639 * with tag specified as EMPTY
640 * <34> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/GET_WORK
641 * from WS with pending tag switch to ORDERED or ATOMIC
642 * <33> Received SWTAG/SWTAG_DESCH/DESCH/UPD_WQP
643 * from WS in UNSCHEDULED state
644 * <32> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP
645 * from WS in EMPTY state
646 */
647 union cvmx_sso_err {
648 u64 u64;
649 struct cvmx_sso_err_s {
650 u64 reserved_48_63 : 16;
651 u64 bfp : 1;
652 u64 awe : 1;
653 u64 fpe : 1;
654 u64 reserved_43_44 : 2;
655 u64 iop : 11;
656 u64 reserved_12_31 : 20;
657 u64 pnd_dbe0 : 1;
658 u64 pnd_sbe0 : 1;
659 u64 pnd_dbe1 : 1;
660 u64 pnd_sbe1 : 1;
661 u64 oth_dbe0 : 1;
662 u64 oth_sbe0 : 1;
663 u64 oth_dbe1 : 1;
664 u64 oth_sbe1 : 1;
665 u64 idx_dbe : 1;
666 u64 idx_sbe : 1;
667 u64 fidx_dbe : 1;
668 u64 fidx_sbe : 1;
669 } s;
670 struct cvmx_sso_err_s cn68xx;
671 struct cvmx_sso_err_s cn68xxp1;
672 };
673
674 typedef union cvmx_sso_err cvmx_sso_err_t;
675
676 /**
677 * cvmx_sso_err0
678 *
679 * This register contains ECC and other miscellaneous error bits.
680 *
681 */
682 union cvmx_sso_err0 {
683 u64 u64;
684 struct cvmx_sso_err0_s {
685 u64 reserved_52_63 : 12;
686 u64 toaqt_dbe : 1;
687 u64 toaqt_sbe : 1;
688 u64 toaqh_dbe : 1;
689 u64 toaqh_sbe : 1;
690 u64 tiaqt_dbe : 1;
691 u64 tiaqt_sbe : 1;
692 u64 tiaqh_dbe : 1;
693 u64 tiaqh_sbe : 1;
694 u64 llm_dbe : 1;
695 u64 llm_sbe : 1;
696 u64 inp_dbe : 1;
697 u64 inp_sbe : 1;
698 u64 qtc_dbe : 1;
699 u64 qtc_sbe : 1;
700 u64 xaq_dbe : 1;
701 u64 xaq_sbe : 1;
702 u64 fff_dbe : 1;
703 u64 fff_sbe : 1;
704 u64 wes_dbe : 1;
705 u64 wes_sbe : 1;
706 u64 reserved_6_31 : 26;
707 u64 addwq_dropped : 1;
708 u64 awempty : 1;
709 u64 grpdis : 1;
710 u64 bfp : 1;
711 u64 awe : 1;
712 u64 fpe : 1;
713 } s;
714 struct cvmx_sso_err0_s cn73xx;
715 struct cvmx_sso_err0_s cn78xx;
716 struct cvmx_sso_err0_s cn78xxp1;
717 struct cvmx_sso_err0_s cnf75xx;
718 };
719
720 typedef union cvmx_sso_err0 cvmx_sso_err0_t;
721
722 /**
723 * cvmx_sso_err1
724 *
725 * This register contains ECC and other miscellaneous error bits.
726 *
727 */
728 union cvmx_sso_err1 {
729 u64 u64;
730 struct cvmx_sso_err1_s {
731 u64 reserved_14_63 : 50;
732 u64 thrint_dbe : 1;
733 u64 thrint_sbe : 1;
734 u64 mask_dbe : 1;
735 u64 mask_sbe : 1;
736 u64 gdw_dbe : 1;
737 u64 gdw_sbe : 1;
738 u64 qidx_dbe : 1;
739 u64 qidx_sbe : 1;
740 u64 tptr_dbe : 1;
741 u64 tptr_sbe : 1;
742 u64 hptr_dbe : 1;
743 u64 hptr_sbe : 1;
744 u64 cntr_dbe : 1;
745 u64 cntr_sbe : 1;
746 } s;
747 struct cvmx_sso_err1_s cn73xx;
748 struct cvmx_sso_err1_s cn78xx;
749 struct cvmx_sso_err1_s cn78xxp1;
750 struct cvmx_sso_err1_s cnf75xx;
751 };
752
753 typedef union cvmx_sso_err1 cvmx_sso_err1_t;
754
755 /**
756 * cvmx_sso_err2
757 *
758 * This register contains ECC and other miscellaneous error bits.
759 *
760 */
761 union cvmx_sso_err2 {
762 u64 u64;
763 struct cvmx_sso_err2_s {
764 u64 reserved_42_63 : 22;
765 u64 ncbo_dbe : 1;
766 u64 ncbo_sbe : 1;
767 u64 pnd_dbe : 1;
768 u64 pnd_sbe : 1;
769 u64 oth_dbe : 1;
770 u64 oth_sbe : 1;
771 u64 nidx_dbe : 1;
772 u64 nidx_sbe : 1;
773 u64 pidx_dbe : 1;
774 u64 pidx_sbe : 1;
775 u64 reserved_13_31 : 19;
776 u64 iop : 13;
777 } s;
778 struct cvmx_sso_err2_s cn73xx;
779 struct cvmx_sso_err2_s cn78xx;
780 struct cvmx_sso_err2_s cn78xxp1;
781 struct cvmx_sso_err2_s cnf75xx;
782 };
783
784 typedef union cvmx_sso_err2 cvmx_sso_err2_t;
785
786 /**
787 * cvmx_sso_err_enb
788 *
789 * SSO_ERR_ENB = SSO Error Enable Register
790 *
791 * Contains the interrupt enables corresponding to SSO_ERR.
792 */
793 union cvmx_sso_err_enb {
794 u64 u64;
795 struct cvmx_sso_err_enb_s {
796 u64 reserved_48_63 : 16;
797 u64 bfp_ie : 1;
798 u64 awe_ie : 1;
799 u64 fpe_ie : 1;
800 u64 reserved_43_44 : 2;
801 u64 iop_ie : 11;
802 u64 reserved_12_31 : 20;
803 u64 pnd_dbe0_ie : 1;
804 u64 pnd_sbe0_ie : 1;
805 u64 pnd_dbe1_ie : 1;
806 u64 pnd_sbe1_ie : 1;
807 u64 oth_dbe0_ie : 1;
808 u64 oth_sbe0_ie : 1;
809 u64 oth_dbe1_ie : 1;
810 u64 oth_sbe1_ie : 1;
811 u64 idx_dbe_ie : 1;
812 u64 idx_sbe_ie : 1;
813 u64 fidx_dbe_ie : 1;
814 u64 fidx_sbe_ie : 1;
815 } s;
816 struct cvmx_sso_err_enb_s cn68xx;
817 struct cvmx_sso_err_enb_s cn68xxp1;
818 };
819
820 typedef union cvmx_sso_err_enb cvmx_sso_err_enb_t;
821
822 /**
823 * cvmx_sso_fidx_ecc_ctl
824 *
825 * SSO_FIDX_ECC_CTL = SSO FIDX ECC Control
826 *
827 */
828 union cvmx_sso_fidx_ecc_ctl {
829 u64 u64;
830 struct cvmx_sso_fidx_ecc_ctl_s {
831 u64 reserved_3_63 : 61;
832 u64 flip_synd : 2;
833 u64 ecc_ena : 1;
834 } s;
835 struct cvmx_sso_fidx_ecc_ctl_s cn68xx;
836 struct cvmx_sso_fidx_ecc_ctl_s cn68xxp1;
837 };
838
839 typedef union cvmx_sso_fidx_ecc_ctl cvmx_sso_fidx_ecc_ctl_t;
840
841 /**
842 * cvmx_sso_fidx_ecc_st
843 *
844 * SSO_FIDX_ECC_ST = SSO FIDX ECC Status
845 *
846 */
847 union cvmx_sso_fidx_ecc_st {
848 u64 u64;
849 struct cvmx_sso_fidx_ecc_st_s {
850 u64 reserved_27_63 : 37;
851 u64 addr : 11;
852 u64 reserved_9_15 : 7;
853 u64 syndrom : 5;
854 u64 reserved_0_3 : 4;
855 } s;
856 struct cvmx_sso_fidx_ecc_st_s cn68xx;
857 struct cvmx_sso_fidx_ecc_st_s cn68xxp1;
858 };
859
860 typedef union cvmx_sso_fidx_ecc_st cvmx_sso_fidx_ecc_st_t;
861
862 /**
863 * cvmx_sso_fpage_cnt
864 *
865 * SSO_FPAGE_CNT = SSO Free Page Cnt
866 *
867 * This register keeps track of the number of free pages pointers available for use in external memory.
868 */
869 union cvmx_sso_fpage_cnt {
870 u64 u64;
871 struct cvmx_sso_fpage_cnt_s {
872 u64 reserved_32_63 : 32;
873 u64 fpage_cnt : 32;
874 } s;
875 struct cvmx_sso_fpage_cnt_s cn68xx;
876 struct cvmx_sso_fpage_cnt_s cn68xxp1;
877 };
878
879 typedef union cvmx_sso_fpage_cnt cvmx_sso_fpage_cnt_t;
880
881 /**
882 * cvmx_sso_grp#_aq_cnt
883 */
884 union cvmx_sso_grpx_aq_cnt {
885 u64 u64;
886 struct cvmx_sso_grpx_aq_cnt_s {
887 u64 reserved_33_63 : 31;
888 u64 aq_cnt : 33;
889 } s;
890 struct cvmx_sso_grpx_aq_cnt_s cn73xx;
891 struct cvmx_sso_grpx_aq_cnt_s cn78xx;
892 struct cvmx_sso_grpx_aq_cnt_s cn78xxp1;
893 struct cvmx_sso_grpx_aq_cnt_s cnf75xx;
894 };
895
896 typedef union cvmx_sso_grpx_aq_cnt cvmx_sso_grpx_aq_cnt_t;
897
898 /**
899 * cvmx_sso_grp#_aq_thr
900 */
901 union cvmx_sso_grpx_aq_thr {
902 u64 u64;
903 struct cvmx_sso_grpx_aq_thr_s {
904 u64 reserved_33_63 : 31;
905 u64 aq_thr : 33;
906 } s;
907 struct cvmx_sso_grpx_aq_thr_s cn73xx;
908 struct cvmx_sso_grpx_aq_thr_s cn78xx;
909 struct cvmx_sso_grpx_aq_thr_s cn78xxp1;
910 struct cvmx_sso_grpx_aq_thr_s cnf75xx;
911 };
912
913 typedef union cvmx_sso_grpx_aq_thr cvmx_sso_grpx_aq_thr_t;
914
915 /**
916 * cvmx_sso_grp#_ds_pc
917 *
918 * Counts the number of deschedule requests for each group. Counter rolls over through zero when
919 * max value exceeded.
920 */
921 union cvmx_sso_grpx_ds_pc {
922 u64 u64;
923 struct cvmx_sso_grpx_ds_pc_s {
924 u64 cnt : 64;
925 } s;
926 struct cvmx_sso_grpx_ds_pc_s cn73xx;
927 struct cvmx_sso_grpx_ds_pc_s cn78xx;
928 struct cvmx_sso_grpx_ds_pc_s cn78xxp1;
929 struct cvmx_sso_grpx_ds_pc_s cnf75xx;
930 };
931
932 typedef union cvmx_sso_grpx_ds_pc cvmx_sso_grpx_ds_pc_t;
933
934 /**
935 * cvmx_sso_grp#_ext_pc
936 *
937 * Counts the number of cache lines of WAEs sent to L2/DDR. Counter rolls over through zero when
938 * max value exceeded.
939 */
940 union cvmx_sso_grpx_ext_pc {
941 u64 u64;
942 struct cvmx_sso_grpx_ext_pc_s {
943 u64 cnt : 64;
944 } s;
945 struct cvmx_sso_grpx_ext_pc_s cn73xx;
946 struct cvmx_sso_grpx_ext_pc_s cn78xx;
947 struct cvmx_sso_grpx_ext_pc_s cn78xxp1;
948 struct cvmx_sso_grpx_ext_pc_s cnf75xx;
949 };
950
951 typedef union cvmx_sso_grpx_ext_pc cvmx_sso_grpx_ext_pc_t;
952
953 /**
954 * cvmx_sso_grp#_iaq_thr
955 *
956 * These registers contain the thresholds for allocating SSO in-unit admission queue entries, see
957 * In-Unit Thresholds.
958 */
959 union cvmx_sso_grpx_iaq_thr {
960 u64 u64;
961 struct cvmx_sso_grpx_iaq_thr_s {
962 u64 reserved_61_63 : 3;
963 u64 grp_cnt : 13;
964 u64 reserved_45_47 : 3;
965 u64 max_thr : 13;
966 u64 reserved_13_31 : 19;
967 u64 rsvd_thr : 13;
968 } s;
969 struct cvmx_sso_grpx_iaq_thr_s cn73xx;
970 struct cvmx_sso_grpx_iaq_thr_s cn78xx;
971 struct cvmx_sso_grpx_iaq_thr_s cn78xxp1;
972 struct cvmx_sso_grpx_iaq_thr_s cnf75xx;
973 };
974
975 typedef union cvmx_sso_grpx_iaq_thr cvmx_sso_grpx_iaq_thr_t;
976
977 /**
978 * cvmx_sso_grp#_int
979 *
980 * Contains the per-group interrupts and are used to clear these interrupts. For more information
981 * on this register, refer to Interrupts.
982 */
983 union cvmx_sso_grpx_int {
984 u64 u64;
985 struct cvmx_sso_grpx_int_s {
986 u64 exe_dis : 1;
987 u64 reserved_2_62 : 61;
988 u64 exe_int : 1;
989 u64 aq_int : 1;
990 } s;
991 struct cvmx_sso_grpx_int_s cn73xx;
992 struct cvmx_sso_grpx_int_s cn78xx;
993 struct cvmx_sso_grpx_int_s cn78xxp1;
994 struct cvmx_sso_grpx_int_s cnf75xx;
995 };
996
997 typedef union cvmx_sso_grpx_int cvmx_sso_grpx_int_t;
998
999 /**
1000 * cvmx_sso_grp#_int_cnt
1001 *
1002 * These registers contain a read-only copy of the counts used to trigger work-queue interrupts
1003 * (one per group). For more information on this register, refer to Interrupts.
1004 */
1005 union cvmx_sso_grpx_int_cnt {
1006 u64 u64;
1007 struct cvmx_sso_grpx_int_cnt_s {
1008 u64 reserved_61_63 : 3;
1009 u64 tc_cnt : 13;
1010 u64 reserved_45_47 : 3;
1011 u64 cq_cnt : 13;
1012 u64 reserved_29_31 : 3;
1013 u64 ds_cnt : 13;
1014 u64 reserved_13_15 : 3;
1015 u64 iaq_cnt : 13;
1016 } s;
1017 struct cvmx_sso_grpx_int_cnt_s cn73xx;
1018 struct cvmx_sso_grpx_int_cnt_s cn78xx;
1019 struct cvmx_sso_grpx_int_cnt_s cn78xxp1;
1020 struct cvmx_sso_grpx_int_cnt_s cnf75xx;
1021 };
1022
1023 typedef union cvmx_sso_grpx_int_cnt cvmx_sso_grpx_int_cnt_t;
1024
1025 /**
1026 * cvmx_sso_grp#_int_thr
1027 *
1028 * These registers contain the thresholds for enabling and setting work-queue interrupts (one per
1029 * group). For more information on this register, refer to Interrupts.
1030 */
1031 union cvmx_sso_grpx_int_thr {
1032 u64 u64;
1033 struct cvmx_sso_grpx_int_thr_s {
1034 u64 tc_en : 1;
1035 u64 reserved_61_62 : 2;
1036 u64 tc_thr : 13;
1037 u64 reserved_45_47 : 3;
1038 u64 cq_thr : 13;
1039 u64 reserved_29_31 : 3;
1040 u64 ds_thr : 13;
1041 u64 reserved_13_15 : 3;
1042 u64 iaq_thr : 13;
1043 } s;
1044 struct cvmx_sso_grpx_int_thr_s cn73xx;
1045 struct cvmx_sso_grpx_int_thr_s cn78xx;
1046 struct cvmx_sso_grpx_int_thr_s cn78xxp1;
1047 struct cvmx_sso_grpx_int_thr_s cnf75xx;
1048 };
1049
1050 typedef union cvmx_sso_grpx_int_thr cvmx_sso_grpx_int_thr_t;
1051
1052 /**
1053 * cvmx_sso_grp#_pri
1054 *
1055 * Controls the priority and group affinity arbitration for each group.
1056 *
1057 */
1058 union cvmx_sso_grpx_pri {
1059 u64 u64;
1060 struct cvmx_sso_grpx_pri_s {
1061 u64 reserved_30_63 : 34;
1062 u64 wgt_left : 6;
1063 u64 reserved_22_23 : 2;
1064 u64 weight : 6;
1065 u64 reserved_12_15 : 4;
1066 u64 affinity : 4;
1067 u64 reserved_3_7 : 5;
1068 u64 pri : 3;
1069 } s;
1070 struct cvmx_sso_grpx_pri_s cn73xx;
1071 struct cvmx_sso_grpx_pri_s cn78xx;
1072 struct cvmx_sso_grpx_pri_s cn78xxp1;
1073 struct cvmx_sso_grpx_pri_s cnf75xx;
1074 };
1075
1076 typedef union cvmx_sso_grpx_pri cvmx_sso_grpx_pri_t;
1077
1078 /**
1079 * cvmx_sso_grp#_taq_thr
1080 *
1081 * These registers contain the thresholds for allocating SSO transitory admission queue storage
1082 * buffers, see Transitory-Admission Thresholds.
1083 */
1084 union cvmx_sso_grpx_taq_thr {
1085 u64 u64;
1086 struct cvmx_sso_grpx_taq_thr_s {
1087 u64 reserved_59_63 : 5;
1088 u64 grp_cnt : 11;
1089 u64 reserved_43_47 : 5;
1090 u64 max_thr : 11;
1091 u64 reserved_11_31 : 21;
1092 u64 rsvd_thr : 11;
1093 } s;
1094 struct cvmx_sso_grpx_taq_thr_s cn73xx;
1095 struct cvmx_sso_grpx_taq_thr_s cn78xx;
1096 struct cvmx_sso_grpx_taq_thr_s cn78xxp1;
1097 struct cvmx_sso_grpx_taq_thr_s cnf75xx;
1098 };
1099
1100 typedef union cvmx_sso_grpx_taq_thr cvmx_sso_grpx_taq_thr_t;
1101
1102 /**
1103 * cvmx_sso_grp#_ts_pc
1104 *
1105 * Counts the number of tag switch requests for each group being switched to. Counter rolls over
1106 * through zero when max value exceeded.
1107 */
1108 union cvmx_sso_grpx_ts_pc {
1109 u64 u64;
1110 struct cvmx_sso_grpx_ts_pc_s {
1111 u64 cnt : 64;
1112 } s;
1113 struct cvmx_sso_grpx_ts_pc_s cn73xx;
1114 struct cvmx_sso_grpx_ts_pc_s cn78xx;
1115 struct cvmx_sso_grpx_ts_pc_s cn78xxp1;
1116 struct cvmx_sso_grpx_ts_pc_s cnf75xx;
1117 };
1118
1119 typedef union cvmx_sso_grpx_ts_pc cvmx_sso_grpx_ts_pc_t;
1120
1121 /**
1122 * cvmx_sso_grp#_wa_pc
1123 *
1124 * Counts the number of add new work requests for each group. The counter rolls over through zero
1125 * when the max value exceeded.
1126 */
1127 union cvmx_sso_grpx_wa_pc {
1128 u64 u64;
1129 struct cvmx_sso_grpx_wa_pc_s {
1130 u64 cnt : 64;
1131 } s;
1132 struct cvmx_sso_grpx_wa_pc_s cn73xx;
1133 struct cvmx_sso_grpx_wa_pc_s cn78xx;
1134 struct cvmx_sso_grpx_wa_pc_s cn78xxp1;
1135 struct cvmx_sso_grpx_wa_pc_s cnf75xx;
1136 };
1137
1138 typedef union cvmx_sso_grpx_wa_pc cvmx_sso_grpx_wa_pc_t;
1139
1140 /**
1141 * cvmx_sso_grp#_ws_pc
1142 *
1143 * Counts the number of work schedules for each group. The counter rolls over through zero when
1144 * the maximum value is exceeded.
1145 */
1146 union cvmx_sso_grpx_ws_pc {
1147 u64 u64;
1148 struct cvmx_sso_grpx_ws_pc_s {
1149 u64 cnt : 64;
1150 } s;
1151 struct cvmx_sso_grpx_ws_pc_s cn73xx;
1152 struct cvmx_sso_grpx_ws_pc_s cn78xx;
1153 struct cvmx_sso_grpx_ws_pc_s cn78xxp1;
1154 struct cvmx_sso_grpx_ws_pc_s cnf75xx;
1155 };
1156
1157 typedef union cvmx_sso_grpx_ws_pc cvmx_sso_grpx_ws_pc_t;
1158
1159 /**
1160 * cvmx_sso_gw_eco
1161 */
1162 union cvmx_sso_gw_eco {
1163 u64 u64;
1164 struct cvmx_sso_gw_eco_s {
1165 u64 reserved_8_63 : 56;
1166 u64 eco_rw : 8;
1167 } s;
1168 struct cvmx_sso_gw_eco_s cn73xx;
1169 struct cvmx_sso_gw_eco_s cnf75xx;
1170 };
1171
1172 typedef union cvmx_sso_gw_eco cvmx_sso_gw_eco_t;
1173
1174 /**
1175 * cvmx_sso_gwe_cfg
1176 *
1177 * This register controls the operation of the get-work examiner (GWE).
1178 *
1179 */
1180 union cvmx_sso_gwe_cfg {
1181 u64 u64;
1182 struct cvmx_sso_gwe_cfg_s {
1183 u64 reserved_12_63 : 52;
1184 u64 odu_ffpgw_dis : 1;
1185 u64 gwe_rfpgw_dis : 1;
1186 u64 odu_prf_dis : 1;
1187 u64 reserved_0_8 : 9;
1188 } s;
1189 struct cvmx_sso_gwe_cfg_cn68xx {
1190 u64 reserved_12_63 : 52;
1191 u64 odu_ffpgw_dis : 1;
1192 u64 gwe_rfpgw_dis : 1;
1193 u64 odu_prf_dis : 1;
1194 u64 odu_bmp_dis : 1;
1195 u64 reserved_5_7 : 3;
1196 u64 gwe_hvy_dis : 1;
1197 u64 gwe_poe : 1;
1198 u64 gwe_fpor : 1;
1199 u64 gwe_rah : 1;
1200 u64 gwe_dis : 1;
1201 } cn68xx;
1202 struct cvmx_sso_gwe_cfg_cn68xxp1 {
1203 u64 reserved_4_63 : 60;
1204 u64 gwe_poe : 1;
1205 u64 gwe_fpor : 1;
1206 u64 gwe_rah : 1;
1207 u64 gwe_dis : 1;
1208 } cn68xxp1;
1209 struct cvmx_sso_gwe_cfg_cn73xx {
1210 u64 reserved_9_63 : 55;
1211 u64 dis_wgt_credit : 1;
1212 u64 ws_retries : 8;
1213 } cn73xx;
1214 struct cvmx_sso_gwe_cfg_cn73xx cn78xx;
1215 struct cvmx_sso_gwe_cfg_cn73xx cn78xxp1;
1216 struct cvmx_sso_gwe_cfg_cn73xx cnf75xx;
1217 };
1218
1219 typedef union cvmx_sso_gwe_cfg cvmx_sso_gwe_cfg_t;
1220
1221 /**
1222 * cvmx_sso_gwe_random
1223 *
1224 * This register contains the random search start position for the get-work examiner (GWE).
1225 *
1226 */
1227 union cvmx_sso_gwe_random {
1228 u64 u64;
1229 struct cvmx_sso_gwe_random_s {
1230 u64 reserved_16_63 : 48;
1231 u64 rnd : 16;
1232 } s;
1233 struct cvmx_sso_gwe_random_s cn73xx;
1234 struct cvmx_sso_gwe_random_s cn78xx;
1235 struct cvmx_sso_gwe_random_s cn78xxp1;
1236 struct cvmx_sso_gwe_random_s cnf75xx;
1237 };
1238
1239 typedef union cvmx_sso_gwe_random cvmx_sso_gwe_random_t;
1240
1241 /**
1242 * cvmx_sso_idx_ecc_ctl
1243 *
1244 * SSO_IDX_ECC_CTL = SSO IDX ECC Control
1245 *
1246 */
1247 union cvmx_sso_idx_ecc_ctl {
1248 u64 u64;
1249 struct cvmx_sso_idx_ecc_ctl_s {
1250 u64 reserved_3_63 : 61;
1251 u64 flip_synd : 2;
1252 u64 ecc_ena : 1;
1253 } s;
1254 struct cvmx_sso_idx_ecc_ctl_s cn68xx;
1255 struct cvmx_sso_idx_ecc_ctl_s cn68xxp1;
1256 };
1257
1258 typedef union cvmx_sso_idx_ecc_ctl cvmx_sso_idx_ecc_ctl_t;
1259
1260 /**
1261 * cvmx_sso_idx_ecc_st
1262 *
1263 * SSO_IDX_ECC_ST = SSO IDX ECC Status
1264 *
1265 */
1266 union cvmx_sso_idx_ecc_st {
1267 u64 u64;
1268 struct cvmx_sso_idx_ecc_st_s {
1269 u64 reserved_27_63 : 37;
1270 u64 addr : 11;
1271 u64 reserved_9_15 : 7;
1272 u64 syndrom : 5;
1273 u64 reserved_0_3 : 4;
1274 } s;
1275 struct cvmx_sso_idx_ecc_st_s cn68xx;
1276 struct cvmx_sso_idx_ecc_st_s cn68xxp1;
1277 };
1278
1279 typedef union cvmx_sso_idx_ecc_st cvmx_sso_idx_ecc_st_t;
1280
1281 /**
1282 * cvmx_sso_ient#_links
1283 *
1284 * Returns unit memory status for an index.
1285 *
1286 */
1287 union cvmx_sso_ientx_links {
1288 u64 u64;
1289 struct cvmx_sso_ientx_links_s {
1290 u64 reserved_28_63 : 36;
1291 u64 prev_index : 12;
1292 u64 reserved_0_15 : 16;
1293 } s;
1294 struct cvmx_sso_ientx_links_cn73xx {
1295 u64 reserved_26_63 : 38;
1296 u64 prev_index : 10;
1297 u64 reserved_11_15 : 5;
1298 u64 next_index_vld : 1;
1299 u64 next_index : 10;
1300 } cn73xx;
1301 struct cvmx_sso_ientx_links_cn78xx {
1302 u64 reserved_28_63 : 36;
1303 u64 prev_index : 12;
1304 u64 reserved_13_15 : 3;
1305 u64 next_index_vld : 1;
1306 u64 next_index : 12;
1307 } cn78xx;
1308 struct cvmx_sso_ientx_links_cn78xx cn78xxp1;
1309 struct cvmx_sso_ientx_links_cn73xx cnf75xx;
1310 };
1311
1312 typedef union cvmx_sso_ientx_links cvmx_sso_ientx_links_t;
1313
1314 /**
1315 * cvmx_sso_ient#_pendtag
1316 *
1317 * Returns unit memory status for an index.
1318 *
1319 */
1320 union cvmx_sso_ientx_pendtag {
1321 u64 u64;
1322 struct cvmx_sso_ientx_pendtag_s {
1323 u64 reserved_38_63 : 26;
1324 u64 pend_switch : 1;
1325 u64 reserved_34_36 : 3;
1326 u64 pend_tt : 2;
1327 u64 pend_tag : 32;
1328 } s;
1329 struct cvmx_sso_ientx_pendtag_s cn73xx;
1330 struct cvmx_sso_ientx_pendtag_s cn78xx;
1331 struct cvmx_sso_ientx_pendtag_s cn78xxp1;
1332 struct cvmx_sso_ientx_pendtag_s cnf75xx;
1333 };
1334
1335 typedef union cvmx_sso_ientx_pendtag cvmx_sso_ientx_pendtag_t;
1336
1337 /**
1338 * cvmx_sso_ient#_qlinks
1339 *
1340 * Returns unit memory status for an index.
1341 *
1342 */
1343 union cvmx_sso_ientx_qlinks {
1344 u64 u64;
1345 struct cvmx_sso_ientx_qlinks_s {
1346 u64 reserved_12_63 : 52;
1347 u64 next_index : 12;
1348 } s;
1349 struct cvmx_sso_ientx_qlinks_s cn73xx;
1350 struct cvmx_sso_ientx_qlinks_s cn78xx;
1351 struct cvmx_sso_ientx_qlinks_s cn78xxp1;
1352 struct cvmx_sso_ientx_qlinks_s cnf75xx;
1353 };
1354
1355 typedef union cvmx_sso_ientx_qlinks cvmx_sso_ientx_qlinks_t;
1356
1357 /**
1358 * cvmx_sso_ient#_tag
1359 *
1360 * Returns unit memory status for an index.
1361 *
1362 */
1363 union cvmx_sso_ientx_tag {
1364 u64 u64;
1365 struct cvmx_sso_ientx_tag_s {
1366 u64 reserved_39_63 : 25;
1367 u64 tailc : 1;
1368 u64 tail : 1;
1369 u64 reserved_34_36 : 3;
1370 u64 tt : 2;
1371 u64 tag : 32;
1372 } s;
1373 struct cvmx_sso_ientx_tag_s cn73xx;
1374 struct cvmx_sso_ientx_tag_s cn78xx;
1375 struct cvmx_sso_ientx_tag_s cn78xxp1;
1376 struct cvmx_sso_ientx_tag_s cnf75xx;
1377 };
1378
1379 typedef union cvmx_sso_ientx_tag cvmx_sso_ientx_tag_t;
1380
1381 /**
1382 * cvmx_sso_ient#_wqpgrp
1383 *
1384 * Returns unit memory status for an index.
1385 *
1386 */
1387 union cvmx_sso_ientx_wqpgrp {
1388 u64 u64;
1389 struct cvmx_sso_ientx_wqpgrp_s {
1390 u64 reserved_62_63 : 2;
1391 u64 head : 1;
1392 u64 nosched : 1;
1393 u64 reserved_58_59 : 2;
1394 u64 grp : 10;
1395 u64 reserved_42_47 : 6;
1396 u64 wqp : 42;
1397 } s;
1398 struct cvmx_sso_ientx_wqpgrp_cn73xx {
1399 u64 reserved_62_63 : 2;
1400 u64 head : 1;
1401 u64 nosched : 1;
1402 u64 reserved_56_59 : 4;
1403 u64 grp : 8;
1404 u64 reserved_42_47 : 6;
1405 u64 wqp : 42;
1406 } cn73xx;
1407 struct cvmx_sso_ientx_wqpgrp_s cn78xx;
1408 struct cvmx_sso_ientx_wqpgrp_s cn78xxp1;
1409 struct cvmx_sso_ientx_wqpgrp_cn73xx cnf75xx;
1410 };
1411
1412 typedef union cvmx_sso_ientx_wqpgrp cvmx_sso_ientx_wqpgrp_t;
1413
1414 /**
1415 * cvmx_sso_ipl_conf#
1416 *
1417 * Returns list status for the conflicted list indexed by group. Register
1418 * fields are identical to those in SSO_IPL_IAQ() above.
1419 */
1420 union cvmx_sso_ipl_confx {
1421 u64 u64;
1422 struct cvmx_sso_ipl_confx_s {
1423 u64 reserved_28_63 : 36;
1424 u64 queue_val : 1;
1425 u64 queue_one : 1;
1426 u64 reserved_25_25 : 1;
1427 u64 queue_head : 12;
1428 u64 reserved_12_12 : 1;
1429 u64 queue_tail : 12;
1430 } s;
1431 struct cvmx_sso_ipl_confx_s cn73xx;
1432 struct cvmx_sso_ipl_confx_s cn78xx;
1433 struct cvmx_sso_ipl_confx_s cn78xxp1;
1434 struct cvmx_sso_ipl_confx_s cnf75xx;
1435 };
1436
1437 typedef union cvmx_sso_ipl_confx cvmx_sso_ipl_confx_t;
1438
1439 /**
1440 * cvmx_sso_ipl_desched#
1441 *
1442 * Returns list status for the deschedule list indexed by group. Register
1443 * fields are identical to those in SSO_IPL_IAQ() above.
1444 */
1445 union cvmx_sso_ipl_deschedx {
1446 u64 u64;
1447 struct cvmx_sso_ipl_deschedx_s {
1448 u64 reserved_28_63 : 36;
1449 u64 queue_val : 1;
1450 u64 queue_one : 1;
1451 u64 reserved_25_25 : 1;
1452 u64 queue_head : 12;
1453 u64 reserved_12_12 : 1;
1454 u64 queue_tail : 12;
1455 } s;
1456 struct cvmx_sso_ipl_deschedx_s cn73xx;
1457 struct cvmx_sso_ipl_deschedx_s cn78xx;
1458 struct cvmx_sso_ipl_deschedx_s cn78xxp1;
1459 struct cvmx_sso_ipl_deschedx_s cnf75xx;
1460 };
1461
1462 typedef union cvmx_sso_ipl_deschedx cvmx_sso_ipl_deschedx_t;
1463
1464 /**
1465 * cvmx_sso_ipl_free#
1466 *
1467 * Returns list status.
1468 *
1469 */
1470 union cvmx_sso_ipl_freex {
1471 u64 u64;
1472 struct cvmx_sso_ipl_freex_s {
1473 u64 reserved_62_63 : 2;
1474 u64 qnum_head : 3;
1475 u64 qnum_tail : 3;
1476 u64 reserved_28_55 : 28;
1477 u64 queue_val : 1;
1478 u64 reserved_25_26 : 2;
1479 u64 queue_head : 12;
1480 u64 reserved_12_12 : 1;
1481 u64 queue_tail : 12;
1482 } s;
1483 struct cvmx_sso_ipl_freex_cn73xx {
1484 u64 reserved_62_63 : 2;
1485 u64 qnum_head : 3;
1486 u64 qnum_tail : 3;
1487 u64 reserved_28_55 : 28;
1488 u64 queue_val : 1;
1489 u64 reserved_23_26 : 4;
1490 u64 queue_head : 10;
1491 u64 reserved_10_12 : 3;
1492 u64 queue_tail : 10;
1493 } cn73xx;
1494 struct cvmx_sso_ipl_freex_s cn78xx;
1495 struct cvmx_sso_ipl_freex_s cn78xxp1;
1496 struct cvmx_sso_ipl_freex_cn73xx cnf75xx;
1497 };
1498
1499 typedef union cvmx_sso_ipl_freex cvmx_sso_ipl_freex_t;
1500
1501 /**
1502 * cvmx_sso_ipl_iaq#
1503 *
1504 * Returns list status for the internal admission queue indexed by group.
1505 *
1506 */
1507 union cvmx_sso_ipl_iaqx {
1508 u64 u64;
1509 struct cvmx_sso_ipl_iaqx_s {
1510 u64 reserved_28_63 : 36;
1511 u64 queue_val : 1;
1512 u64 queue_one : 1;
1513 u64 reserved_25_25 : 1;
1514 u64 queue_head : 12;
1515 u64 reserved_12_12 : 1;
1516 u64 queue_tail : 12;
1517 } s;
1518 struct cvmx_sso_ipl_iaqx_s cn73xx;
1519 struct cvmx_sso_ipl_iaqx_s cn78xx;
1520 struct cvmx_sso_ipl_iaqx_s cn78xxp1;
1521 struct cvmx_sso_ipl_iaqx_s cnf75xx;
1522 };
1523
1524 typedef union cvmx_sso_ipl_iaqx cvmx_sso_ipl_iaqx_t;
1525
1526 /**
1527 * cvmx_sso_iq_cnt#
1528 *
1529 * CSR reserved addresses: (64): 0x8200..0x83f8
1530 * CSR align addresses: ===========================================================================================================
1531 * SSO_IQ_CNTX = SSO Input Queue Count Register
1532 * (one per QOS level)
1533 *
1534 * Contains a read-only count of the number of work queue entries for each QOS
1535 * level. Counts both in-unit and in-memory entries.
1536 */
1537 union cvmx_sso_iq_cntx {
1538 u64 u64;
1539 struct cvmx_sso_iq_cntx_s {
1540 u64 reserved_32_63 : 32;
1541 u64 iq_cnt : 32;
1542 } s;
1543 struct cvmx_sso_iq_cntx_s cn68xx;
1544 struct cvmx_sso_iq_cntx_s cn68xxp1;
1545 };
1546
1547 typedef union cvmx_sso_iq_cntx cvmx_sso_iq_cntx_t;
1548
1549 /**
1550 * cvmx_sso_iq_com_cnt
1551 *
1552 * SSO_IQ_COM_CNT = SSO Input Queue Combined Count Register
1553 *
1554 * Contains a read-only count of the total number of work queue entries in all
1555 * QOS levels. Counts both in-unit and in-memory entries.
1556 */
1557 union cvmx_sso_iq_com_cnt {
1558 u64 u64;
1559 struct cvmx_sso_iq_com_cnt_s {
1560 u64 reserved_32_63 : 32;
1561 u64 iq_cnt : 32;
1562 } s;
1563 struct cvmx_sso_iq_com_cnt_s cn68xx;
1564 struct cvmx_sso_iq_com_cnt_s cn68xxp1;
1565 };
1566
1567 typedef union cvmx_sso_iq_com_cnt cvmx_sso_iq_com_cnt_t;
1568
1569 /**
1570 * cvmx_sso_iq_int
1571 *
1572 * SSO_IQ_INT = SSO Input Queue Interrupt Register
1573 *
1574 * Contains the bits (one per QOS level) that can trigger the input queue
1575 * interrupt. An IQ_INT bit will be set if SSO_IQ_CNT#QOS# changes and the
1576 * resulting value is equal to SSO_IQ_THR#QOS#.
1577 */
1578 union cvmx_sso_iq_int {
1579 u64 u64;
1580 struct cvmx_sso_iq_int_s {
1581 u64 reserved_8_63 : 56;
1582 u64 iq_int : 8;
1583 } s;
1584 struct cvmx_sso_iq_int_s cn68xx;
1585 struct cvmx_sso_iq_int_s cn68xxp1;
1586 };
1587
1588 typedef union cvmx_sso_iq_int cvmx_sso_iq_int_t;
1589
1590 /**
1591 * cvmx_sso_iq_int_en
1592 *
1593 * SSO_IQ_INT_EN = SSO Input Queue Interrupt Enable Register
1594 *
1595 * Contains the bits (one per QOS level) that enable the input queue interrupt.
1596 */
1597 union cvmx_sso_iq_int_en {
1598 u64 u64;
1599 struct cvmx_sso_iq_int_en_s {
1600 u64 reserved_8_63 : 56;
1601 u64 int_en : 8;
1602 } s;
1603 struct cvmx_sso_iq_int_en_s cn68xx;
1604 struct cvmx_sso_iq_int_en_s cn68xxp1;
1605 };
1606
1607 typedef union cvmx_sso_iq_int_en cvmx_sso_iq_int_en_t;
1608
1609 /**
1610 * cvmx_sso_iq_thr#
1611 *
1612 * CSR reserved addresses: (24): 0x9040..0x90f8
1613 * CSR align addresses: ===========================================================================================================
1614 * SSO_IQ_THRX = SSO Input Queue Threshold Register
1615 * (one per QOS level)
1616 *
1617 * Threshold value for triggering input queue interrupts.
1618 */
1619 union cvmx_sso_iq_thrx {
1620 u64 u64;
1621 struct cvmx_sso_iq_thrx_s {
1622 u64 reserved_32_63 : 32;
1623 u64 iq_thr : 32;
1624 } s;
1625 struct cvmx_sso_iq_thrx_s cn68xx;
1626 struct cvmx_sso_iq_thrx_s cn68xxp1;
1627 };
1628
1629 typedef union cvmx_sso_iq_thrx cvmx_sso_iq_thrx_t;
1630
1631 /**
1632 * cvmx_sso_nos_cnt
1633 *
1634 * Contains the number of work-queue entries on the no-schedule list.
1635 *
1636 */
1637 union cvmx_sso_nos_cnt {
1638 u64 u64;
1639 struct cvmx_sso_nos_cnt_s {
1640 u64 reserved_13_63 : 51;
1641 u64 nos_cnt : 13;
1642 } s;
1643 struct cvmx_sso_nos_cnt_cn68xx {
1644 u64 reserved_12_63 : 52;
1645 u64 nos_cnt : 12;
1646 } cn68xx;
1647 struct cvmx_sso_nos_cnt_cn68xx cn68xxp1;
1648 struct cvmx_sso_nos_cnt_s cn73xx;
1649 struct cvmx_sso_nos_cnt_s cn78xx;
1650 struct cvmx_sso_nos_cnt_s cn78xxp1;
1651 struct cvmx_sso_nos_cnt_s cnf75xx;
1652 };
1653
1654 typedef union cvmx_sso_nos_cnt cvmx_sso_nos_cnt_t;
1655
1656 /**
1657 * cvmx_sso_nw_tim
1658 *
1659 * Sets the minimum period for a new-work-request timeout. The period is specified in n-1
1660 * notation, with the increment value of 1024 clock cycles. Thus, a value of 0x0 in this register
1661 * translates to 1024 cycles, 0x1 translates to 2048 cycles, 0x2 translates to 3072 cycles, etc.
1662 */
1663 union cvmx_sso_nw_tim {
1664 u64 u64;
1665 struct cvmx_sso_nw_tim_s {
1666 u64 reserved_10_63 : 54;
1667 u64 nw_tim : 10;
1668 } s;
1669 struct cvmx_sso_nw_tim_s cn68xx;
1670 struct cvmx_sso_nw_tim_s cn68xxp1;
1671 struct cvmx_sso_nw_tim_s cn73xx;
1672 struct cvmx_sso_nw_tim_s cn78xx;
1673 struct cvmx_sso_nw_tim_s cn78xxp1;
1674 struct cvmx_sso_nw_tim_s cnf75xx;
1675 };
1676
1677 typedef union cvmx_sso_nw_tim cvmx_sso_nw_tim_t;
1678
1679 /**
1680 * cvmx_sso_oth_ecc_ctl
1681 *
1682 * SSO_OTH_ECC_CTL = SSO OTH ECC Control
1683 *
1684 */
1685 union cvmx_sso_oth_ecc_ctl {
1686 u64 u64;
1687 struct cvmx_sso_oth_ecc_ctl_s {
1688 u64 reserved_6_63 : 58;
1689 u64 flip_synd1 : 2;
1690 u64 ecc_ena1 : 1;
1691 u64 flip_synd0 : 2;
1692 u64 ecc_ena0 : 1;
1693 } s;
1694 struct cvmx_sso_oth_ecc_ctl_s cn68xx;
1695 struct cvmx_sso_oth_ecc_ctl_s cn68xxp1;
1696 };
1697
1698 typedef union cvmx_sso_oth_ecc_ctl cvmx_sso_oth_ecc_ctl_t;
1699
1700 /**
1701 * cvmx_sso_oth_ecc_st
1702 *
1703 * SSO_OTH_ECC_ST = SSO OTH ECC Status
1704 *
1705 */
1706 union cvmx_sso_oth_ecc_st {
1707 u64 u64;
1708 struct cvmx_sso_oth_ecc_st_s {
1709 u64 reserved_59_63 : 5;
1710 u64 addr1 : 11;
1711 u64 reserved_43_47 : 5;
1712 u64 syndrom1 : 7;
1713 u64 reserved_27_35 : 9;
1714 u64 addr0 : 11;
1715 u64 reserved_11_15 : 5;
1716 u64 syndrom0 : 7;
1717 u64 reserved_0_3 : 4;
1718 } s;
1719 struct cvmx_sso_oth_ecc_st_s cn68xx;
1720 struct cvmx_sso_oth_ecc_st_s cn68xxp1;
1721 };
1722
1723 typedef union cvmx_sso_oth_ecc_st cvmx_sso_oth_ecc_st_t;
1724
1725 /**
1726 * cvmx_sso_page_cnt
1727 */
1728 union cvmx_sso_page_cnt {
1729 u64 u64;
1730 struct cvmx_sso_page_cnt_s {
1731 u64 reserved_32_63 : 32;
1732 u64 cnt : 32;
1733 } s;
1734 struct cvmx_sso_page_cnt_s cn73xx;
1735 struct cvmx_sso_page_cnt_s cn78xx;
1736 struct cvmx_sso_page_cnt_s cn78xxp1;
1737 struct cvmx_sso_page_cnt_s cnf75xx;
1738 };
1739
1740 typedef union cvmx_sso_page_cnt cvmx_sso_page_cnt_t;
1741
1742 /**
1743 * cvmx_sso_pnd_ecc_ctl
1744 *
1745 * SSO_PND_ECC_CTL = SSO PND ECC Control
1746 *
1747 */
1748 union cvmx_sso_pnd_ecc_ctl {
1749 u64 u64;
1750 struct cvmx_sso_pnd_ecc_ctl_s {
1751 u64 reserved_6_63 : 58;
1752 u64 flip_synd1 : 2;
1753 u64 ecc_ena1 : 1;
1754 u64 flip_synd0 : 2;
1755 u64 ecc_ena0 : 1;
1756 } s;
1757 struct cvmx_sso_pnd_ecc_ctl_s cn68xx;
1758 struct cvmx_sso_pnd_ecc_ctl_s cn68xxp1;
1759 };
1760
1761 typedef union cvmx_sso_pnd_ecc_ctl cvmx_sso_pnd_ecc_ctl_t;
1762
1763 /**
1764 * cvmx_sso_pnd_ecc_st
1765 *
1766 * SSO_PND_ECC_ST = SSO PND ECC Status
1767 *
1768 */
1769 union cvmx_sso_pnd_ecc_st {
1770 u64 u64;
1771 struct cvmx_sso_pnd_ecc_st_s {
1772 u64 reserved_59_63 : 5;
1773 u64 addr1 : 11;
1774 u64 reserved_43_47 : 5;
1775 u64 syndrom1 : 7;
1776 u64 reserved_27_35 : 9;
1777 u64 addr0 : 11;
1778 u64 reserved_11_15 : 5;
1779 u64 syndrom0 : 7;
1780 u64 reserved_0_3 : 4;
1781 } s;
1782 struct cvmx_sso_pnd_ecc_st_s cn68xx;
1783 struct cvmx_sso_pnd_ecc_st_s cn68xxp1;
1784 };
1785
1786 typedef union cvmx_sso_pnd_ecc_st cvmx_sso_pnd_ecc_st_t;
1787
1788 /**
1789 * cvmx_sso_pp#_arb
1790 *
1791 * For diagnostic use, returns the group affinity arbitration state for each core.
1792 *
1793 */
1794 union cvmx_sso_ppx_arb {
1795 u64 u64;
1796 struct cvmx_sso_ppx_arb_s {
1797 u64 reserved_20_63 : 44;
1798 u64 aff_left : 4;
1799 u64 reserved_8_15 : 8;
1800 u64 last_grp : 8;
1801 } s;
1802 struct cvmx_sso_ppx_arb_s cn73xx;
1803 struct cvmx_sso_ppx_arb_s cn78xx;
1804 struct cvmx_sso_ppx_arb_s cn78xxp1;
1805 struct cvmx_sso_ppx_arb_s cnf75xx;
1806 };
1807
1808 typedef union cvmx_sso_ppx_arb cvmx_sso_ppx_arb_t;
1809
1810 /**
1811 * cvmx_sso_pp#_grp_msk
1812 *
1813 * CSR reserved addresses: (24): 0x5040..0x50f8
1814 * CSR align addresses: ===========================================================================================================
1815 * SSO_PPX_GRP_MSK = SSO PP Group Mask Register
1816 * (one bit per group per PP)
1817 *
1818 * Selects which group(s) a PP belongs to. A '1' in any bit position sets the
1819 * PP's membership in the corresponding group. A value of 0x0 will prevent the
1820 * PP from receiving new work.
1821 *
1822 * Note that these do not contain QOS level priorities for each PP. This is a
1823 * change from previous POW designs.
1824 */
1825 union cvmx_sso_ppx_grp_msk {
1826 u64 u64;
1827 struct cvmx_sso_ppx_grp_msk_s {
1828 u64 grp_msk : 64;
1829 } s;
1830 struct cvmx_sso_ppx_grp_msk_s cn68xx;
1831 struct cvmx_sso_ppx_grp_msk_s cn68xxp1;
1832 };
1833
1834 typedef union cvmx_sso_ppx_grp_msk cvmx_sso_ppx_grp_msk_t;
1835
1836 /**
1837 * cvmx_sso_pp#_qos_pri
1838 *
1839 * CSR reserved addresses: (56): 0x2040..0x21f8
1840 * CSR align addresses: ===========================================================================================================
1841 * SSO_PP(0..31)_QOS_PRI = SSO PP QOS Priority Register
1842 * (one field per IQ per PP)
1843 *
1844 * Contains the QOS level priorities for each PP.
1845 * 0x0 is the highest priority
1846 * 0x7 is the lowest priority
1847 * 0xf prevents the PP from receiving work from that QOS level
1848 * 0x8-0xe Reserved
1849 *
1850 * For a given PP, priorities should begin at 0x0, and remain contiguous
1851 * throughout the range. Failure to do so may result in severe
1852 * performance degradation.
1853 *
1854 *
1855 * Priorities for IQs 0..7
1856 */
1857 union cvmx_sso_ppx_qos_pri {
1858 u64 u64;
1859 struct cvmx_sso_ppx_qos_pri_s {
1860 u64 reserved_60_63 : 4;
1861 u64 qos7_pri : 4;
1862 u64 reserved_52_55 : 4;
1863 u64 qos6_pri : 4;
1864 u64 reserved_44_47 : 4;
1865 u64 qos5_pri : 4;
1866 u64 reserved_36_39 : 4;
1867 u64 qos4_pri : 4;
1868 u64 reserved_28_31 : 4;
1869 u64 qos3_pri : 4;
1870 u64 reserved_20_23 : 4;
1871 u64 qos2_pri : 4;
1872 u64 reserved_12_15 : 4;
1873 u64 qos1_pri : 4;
1874 u64 reserved_4_7 : 4;
1875 u64 qos0_pri : 4;
1876 } s;
1877 struct cvmx_sso_ppx_qos_pri_s cn68xx;
1878 struct cvmx_sso_ppx_qos_pri_s cn68xxp1;
1879 };
1880
1881 typedef union cvmx_sso_ppx_qos_pri cvmx_sso_ppx_qos_pri_t;
1882
1883 /**
1884 * cvmx_sso_pp#_s#_grpmsk#
1885 *
1886 * These registers select which group or groups a core belongs to. There are 2 sets of masks per
1887 * core, each with 1 register corresponding to 64 groups.
1888 */
1889 union cvmx_sso_ppx_sx_grpmskx {
1890 u64 u64;
1891 struct cvmx_sso_ppx_sx_grpmskx_s {
1892 u64 grp_msk : 64;
1893 } s;
1894 struct cvmx_sso_ppx_sx_grpmskx_s cn73xx;
1895 struct cvmx_sso_ppx_sx_grpmskx_s cn78xx;
1896 struct cvmx_sso_ppx_sx_grpmskx_s cn78xxp1;
1897 struct cvmx_sso_ppx_sx_grpmskx_s cnf75xx;
1898 };
1899
1900 typedef union cvmx_sso_ppx_sx_grpmskx cvmx_sso_ppx_sx_grpmskx_t;
1901
1902 /**
1903 * cvmx_sso_pp_strict
1904 *
1905 * SSO_PP_STRICT = SSO Strict Priority
1906 *
1907 * This register controls getting work from the input queues. If the bit
1908 * corresponding to a PP is set, that PP will not take work off the input
1909 * queues until it is known that there is no higher-priority work available.
1910 *
1911 * Setting SSO_PP_STRICT may incur a performance penalty if highest-priority
1912 * work is not found early.
1913 *
1914 * It is possible to starve a PP of work with SSO_PP_STRICT. If the
1915 * SSO_PPX_GRP_MSK for a PP masks-out much of the work added to the input
1916 * queues that are higher-priority for that PP, and if there is a constant
1917 * stream of work through one or more of those higher-priority input queues,
1918 * then that PP may not accept work from lower-priority input queues. This can
1919 * be alleviated by ensuring that most or all the work added to the
1920 * higher-priority input queues for a PP with SSO_PP_STRICT set are in a group
1921 * acceptable to that PP.
1922 *
1923 * It is also possible to neglect work in an input queue if SSO_PP_STRICT is
1924 * used. If an input queue is a lower-priority queue for all PPs, and if all
1925 * the PPs have their corresponding bit in SSO_PP_STRICT set, then work may
1926 * never be taken (or be seldom taken) from that queue. This can be alleviated
1927 * by ensuring that work in all input queues can be serviced by one or more PPs
1928 * that do not have SSO_PP_STRICT set, or that the input queue is the
1929 * highest-priority input queue for one or more PPs that do have SSO_PP_STRICT
1930 * set.
1931 */
1932 union cvmx_sso_pp_strict {
1933 u64 u64;
1934 struct cvmx_sso_pp_strict_s {
1935 u64 reserved_32_63 : 32;
1936 u64 pp_strict : 32;
1937 } s;
1938 struct cvmx_sso_pp_strict_s cn68xx;
1939 struct cvmx_sso_pp_strict_s cn68xxp1;
1940 };
1941
1942 typedef union cvmx_sso_pp_strict cvmx_sso_pp_strict_t;
1943
1944 /**
1945 * cvmx_sso_qos#_rnd
1946 *
1947 * CSR align addresses: ===========================================================================================================
1948 * SSO_QOS(0..7)_RND = SSO QOS Issue Round Register
1949 * (one per IQ)
1950 *
1951 * The number of arbitration rounds each QOS level participates in.
1952 */
1953 union cvmx_sso_qosx_rnd {
1954 u64 u64;
1955 struct cvmx_sso_qosx_rnd_s {
1956 u64 reserved_8_63 : 56;
1957 u64 rnds_qos : 8;
1958 } s;
1959 struct cvmx_sso_qosx_rnd_s cn68xx;
1960 struct cvmx_sso_qosx_rnd_s cn68xxp1;
1961 };
1962
1963 typedef union cvmx_sso_qosx_rnd cvmx_sso_qosx_rnd_t;
1964
1965 /**
1966 * cvmx_sso_qos_thr#
1967 *
1968 * CSR reserved addresses: (24): 0xa040..0xa0f8
1969 * CSR align addresses: ===========================================================================================================
1970 * SSO_QOS_THRX = SSO QOS Threshold Register
1971 * (one per QOS level)
1972 *
1973 * Contains the thresholds for allocating SSO internal storage buffers. If the
1974 * number of remaining free buffers drops below the minimum threshold (MIN_THR)
1975 * or the number of allocated buffers for this QOS level rises above the
1976 * maximum threshold (MAX_THR), future incoming work queue entries will be
1977 * buffered externally rather than internally. This register also contains the
1978 * number of internal buffers currently allocated to this QOS level (BUF_CNT).
1979 */
1980 union cvmx_sso_qos_thrx {
1981 u64 u64;
1982 struct cvmx_sso_qos_thrx_s {
1983 u64 reserved_40_63 : 24;
1984 u64 buf_cnt : 12;
1985 u64 reserved_26_27 : 2;
1986 u64 max_thr : 12;
1987 u64 reserved_12_13 : 2;
1988 u64 min_thr : 12;
1989 } s;
1990 struct cvmx_sso_qos_thrx_s cn68xx;
1991 struct cvmx_sso_qos_thrx_s cn68xxp1;
1992 };
1993
1994 typedef union cvmx_sso_qos_thrx cvmx_sso_qos_thrx_t;
1995
1996 /**
1997 * cvmx_sso_qos_we
1998 *
1999 * SSO_QOS_WE = SSO WE Buffers
2000 *
2001 * This register contains a read-only count of the current number of free
2002 * buffers (FREE_CNT) and the total number of tag chain heads on the de-schedule list
2003 * (DES_CNT) (which is not the same as the total number of entries on all of the descheduled
2004 * tag chains.)
2005 */
2006 union cvmx_sso_qos_we {
2007 u64 u64;
2008 struct cvmx_sso_qos_we_s {
2009 u64 reserved_26_63 : 38;
2010 u64 des_cnt : 12;
2011 u64 reserved_12_13 : 2;
2012 u64 free_cnt : 12;
2013 } s;
2014 struct cvmx_sso_qos_we_s cn68xx;
2015 struct cvmx_sso_qos_we_s cn68xxp1;
2016 };
2017
2018 typedef union cvmx_sso_qos_we cvmx_sso_qos_we_t;
2019
2020 /**
2021 * cvmx_sso_reset
2022 *
2023 * Writing a 1 to SSO_RESET[RESET] resets the SSO. After receiving a store to this CSR, the SSO
2024 * must not be sent any other operations for 2500 coprocessor (SCLK) cycles. Note that the
2025 * contents of this register are reset along with the rest of the SSO.
2026 */
2027 union cvmx_sso_reset {
2028 u64 u64;
2029 struct cvmx_sso_reset_s {
2030 u64 busy : 1;
2031 u64 reserved_1_62 : 62;
2032 u64 reset : 1;
2033 } s;
2034 struct cvmx_sso_reset_cn68xx {
2035 u64 reserved_1_63 : 63;
2036 u64 reset : 1;
2037 } cn68xx;
2038 struct cvmx_sso_reset_s cn73xx;
2039 struct cvmx_sso_reset_s cn78xx;
2040 struct cvmx_sso_reset_s cn78xxp1;
2041 struct cvmx_sso_reset_s cnf75xx;
2042 };
2043
2044 typedef union cvmx_sso_reset cvmx_sso_reset_t;
2045
2046 /**
2047 * cvmx_sso_rwq_head_ptr#
2048 *
2049 * CSR reserved addresses: (24): 0xb040..0xb0f8
2050 * CSR align addresses: ===========================================================================================================
2051 * SSO_RWQ_HEAD_PTRX = SSO Remote Queue Head Register
2052 * (one per QOS level)
2053 * Contains the ptr to the first entry of the remote linked list(s) for a particular
2054 * QoS level. SW should initialize the remote linked list(s) by programming
2055 * SSO_RWQ_HEAD_PTRX and SSO_RWQ_TAIL_PTRX to identical values.
2056 */
2057 union cvmx_sso_rwq_head_ptrx {
2058 u64 u64;
2059 struct cvmx_sso_rwq_head_ptrx_s {
2060 u64 reserved_38_63 : 26;
2061 u64 ptr : 31;
2062 u64 reserved_5_6 : 2;
2063 u64 rctr : 5;
2064 } s;
2065 struct cvmx_sso_rwq_head_ptrx_s cn68xx;
2066 struct cvmx_sso_rwq_head_ptrx_s cn68xxp1;
2067 };
2068
2069 typedef union cvmx_sso_rwq_head_ptrx cvmx_sso_rwq_head_ptrx_t;
2070
2071 /**
2072 * cvmx_sso_rwq_pop_fptr
2073 *
2074 * SSO_RWQ_POP_FPTR = SSO Pop Free Pointer
2075 *
2076 * This register is used by SW to remove pointers for buffer-reallocation and diagnostics, and
2077 * should only be used when SSO is idle.
2078 *
2079 * To remove ALL pointers, software must insure that there are modulus 16
2080 * pointers in the FPA. To do this, SSO_CFG.RWQ_BYP_DIS must be set, the FPA
2081 * pointer count read, and enough fake buffers pushed via SSO_RWQ_PSH_FPTR to
2082 * bring the FPA pointer count up to mod 16.
2083 */
2084 union cvmx_sso_rwq_pop_fptr {
2085 u64 u64;
2086 struct cvmx_sso_rwq_pop_fptr_s {
2087 u64 val : 1;
2088 u64 reserved_38_62 : 25;
2089 u64 fptr : 31;
2090 u64 reserved_0_6 : 7;
2091 } s;
2092 struct cvmx_sso_rwq_pop_fptr_s cn68xx;
2093 struct cvmx_sso_rwq_pop_fptr_s cn68xxp1;
2094 };
2095
2096 typedef union cvmx_sso_rwq_pop_fptr cvmx_sso_rwq_pop_fptr_t;
2097
2098 /**
2099 * cvmx_sso_rwq_psh_fptr
2100 *
2101 * CSR reserved addresses: (56): 0xc240..0xc3f8
2102 * SSO_RWQ_PSH_FPTR = SSO Free Pointer FIFO
2103 *
2104 * This register is used by SW to initialize the SSO with a pool of free
2105 * pointers by writing the FPTR field whenever FULL = 0. Free pointers are
2106 * fetched/released from/to the pool when accessing WQE entries stored remotely
2107 * (in remote linked lists). Free pointers should be 128 byte aligned, each of
2108 * 256 bytes. This register should only be used when SSO is idle.
2109 *
2110 * Software needs to set aside buffering for
2111 * 8 + 48 + ROUNDUP(N/26)
2112 *
2113 * where as many as N DRAM work queue entries may be used. The first 8 buffers
2114 * are used to setup the SSO_RWQ_HEAD_PTR and SSO_RWQ_TAIL_PTRs, and the
2115 * remainder are pushed via this register.
2116 *
2117 * IMPLEMENTATION NOTES--NOT FOR SPEC:
2118 * 48 avoids false out of buffer error due to (16) FPA and in-sso FPA buffering (32)
2119 * 26 is number of WAE's per 256B buffer
2120 */
2121 union cvmx_sso_rwq_psh_fptr {
2122 u64 u64;
2123 struct cvmx_sso_rwq_psh_fptr_s {
2124 u64 full : 1;
2125 u64 reserved_38_62 : 25;
2126 u64 fptr : 31;
2127 u64 reserved_0_6 : 7;
2128 } s;
2129 struct cvmx_sso_rwq_psh_fptr_s cn68xx;
2130 struct cvmx_sso_rwq_psh_fptr_s cn68xxp1;
2131 };
2132
2133 typedef union cvmx_sso_rwq_psh_fptr cvmx_sso_rwq_psh_fptr_t;
2134
2135 /**
2136 * cvmx_sso_rwq_tail_ptr#
2137 *
2138 * CSR reserved addresses: (56): 0xc040..0xc1f8
2139 * SSO_RWQ_TAIL_PTRX = SSO Remote Queue Tail Register
2140 * (one per QOS level)
2141 * Contains the ptr to the last entry of the remote linked list(s) for a particular
2142 * QoS level. SW must initialize the remote linked list(s) by programming
2143 * SSO_RWQ_HEAD_PTRX and SSO_RWQ_TAIL_PTRX to identical values.
2144 */
2145 union cvmx_sso_rwq_tail_ptrx {
2146 u64 u64;
2147 struct cvmx_sso_rwq_tail_ptrx_s {
2148 u64 reserved_38_63 : 26;
2149 u64 ptr : 31;
2150 u64 reserved_5_6 : 2;
2151 u64 rctr : 5;
2152 } s;
2153 struct cvmx_sso_rwq_tail_ptrx_s cn68xx;
2154 struct cvmx_sso_rwq_tail_ptrx_s cn68xxp1;
2155 };
2156
2157 typedef union cvmx_sso_rwq_tail_ptrx cvmx_sso_rwq_tail_ptrx_t;
2158
2159 /**
2160 * cvmx_sso_sl_pp#_links
2161 *
2162 * Returns status of each core.
2163 *
2164 */
2165 union cvmx_sso_sl_ppx_links {
2166 u64 u64;
2167 struct cvmx_sso_sl_ppx_links_s {
2168 u64 tailc : 1;
2169 u64 reserved_60_62 : 3;
2170 u64 index : 12;
2171 u64 reserved_38_47 : 10;
2172 u64 grp : 10;
2173 u64 head : 1;
2174 u64 tail : 1;
2175 u64 reserved_0_25 : 26;
2176 } s;
2177 struct cvmx_sso_sl_ppx_links_cn73xx {
2178 u64 tailc : 1;
2179 u64 reserved_58_62 : 5;
2180 u64 index : 10;
2181 u64 reserved_36_47 : 12;
2182 u64 grp : 8;
2183 u64 head : 1;
2184 u64 tail : 1;
2185 u64 reserved_21_25 : 5;
2186 u64 revlink_index : 10;
2187 u64 link_index_vld : 1;
2188 u64 link_index : 10;
2189 } cn73xx;
2190 struct cvmx_sso_sl_ppx_links_cn78xx {
2191 u64 tailc : 1;
2192 u64 reserved_60_62 : 3;
2193 u64 index : 12;
2194 u64 reserved_38_47 : 10;
2195 u64 grp : 10;
2196 u64 head : 1;
2197 u64 tail : 1;
2198 u64 reserved_25_25 : 1;
2199 u64 revlink_index : 12;
2200 u64 link_index_vld : 1;
2201 u64 link_index : 12;
2202 } cn78xx;
2203 struct cvmx_sso_sl_ppx_links_cn78xx cn78xxp1;
2204 struct cvmx_sso_sl_ppx_links_cn73xx cnf75xx;
2205 };
2206
2207 typedef union cvmx_sso_sl_ppx_links cvmx_sso_sl_ppx_links_t;
2208
2209 /**
2210 * cvmx_sso_sl_pp#_pendtag
2211 *
2212 * Returns status of each core.
2213 *
2214 */
2215 union cvmx_sso_sl_ppx_pendtag {
2216 u64 u64;
2217 struct cvmx_sso_sl_ppx_pendtag_s {
2218 u64 pend_switch : 1;
2219 u64 pend_get_work : 1;
2220 u64 pend_get_work_wait : 1;
2221 u64 pend_nosched : 1;
2222 u64 pend_nosched_clr : 1;
2223 u64 pend_desched : 1;
2224 u64 pend_alloc_we : 1;
2225 u64 pend_gw_insert : 1;
2226 u64 reserved_34_55 : 22;
2227 u64 pend_tt : 2;
2228 u64 pend_tag : 32;
2229 } s;
2230 struct cvmx_sso_sl_ppx_pendtag_s cn73xx;
2231 struct cvmx_sso_sl_ppx_pendtag_s cn78xx;
2232 struct cvmx_sso_sl_ppx_pendtag_s cn78xxp1;
2233 struct cvmx_sso_sl_ppx_pendtag_s cnf75xx;
2234 };
2235
2236 typedef union cvmx_sso_sl_ppx_pendtag cvmx_sso_sl_ppx_pendtag_t;
2237
2238 /**
2239 * cvmx_sso_sl_pp#_pendwqp
2240 *
2241 * Returns status of each core.
2242 *
2243 */
2244 union cvmx_sso_sl_ppx_pendwqp {
2245 u64 u64;
2246 struct cvmx_sso_sl_ppx_pendwqp_s {
2247 u64 pend_switch : 1;
2248 u64 pend_get_work : 1;
2249 u64 pend_get_work_wait : 1;
2250 u64 pend_nosched : 1;
2251 u64 pend_nosched_clr : 1;
2252 u64 pend_desched : 1;
2253 u64 pend_alloc_we : 1;
2254 u64 reserved_56_56 : 1;
2255 u64 pend_index : 12;
2256 u64 reserved_42_43 : 2;
2257 u64 pend_wqp : 42;
2258 } s;
2259 struct cvmx_sso_sl_ppx_pendwqp_cn73xx {
2260 u64 pend_switch : 1;
2261 u64 pend_get_work : 1;
2262 u64 pend_get_work_wait : 1;
2263 u64 pend_nosched : 1;
2264 u64 pend_nosched_clr : 1;
2265 u64 pend_desched : 1;
2266 u64 pend_alloc_we : 1;
2267 u64 reserved_54_56 : 3;
2268 u64 pend_index : 10;
2269 u64 reserved_42_43 : 2;
2270 u64 pend_wqp : 42;
2271 } cn73xx;
2272 struct cvmx_sso_sl_ppx_pendwqp_s cn78xx;
2273 struct cvmx_sso_sl_ppx_pendwqp_s cn78xxp1;
2274 struct cvmx_sso_sl_ppx_pendwqp_cn73xx cnf75xx;
2275 };
2276
2277 typedef union cvmx_sso_sl_ppx_pendwqp cvmx_sso_sl_ppx_pendwqp_t;
2278
2279 /**
2280 * cvmx_sso_sl_pp#_tag
2281 *
2282 * Returns status of each core.
2283 *
2284 */
2285 union cvmx_sso_sl_ppx_tag {
2286 u64 u64;
2287 struct cvmx_sso_sl_ppx_tag_s {
2288 u64 tailc : 1;
2289 u64 reserved_60_62 : 3;
2290 u64 index : 12;
2291 u64 reserved_46_47 : 2;
2292 u64 grp : 10;
2293 u64 head : 1;
2294 u64 tail : 1;
2295 u64 tt : 2;
2296 u64 tag : 32;
2297 } s;
2298 struct cvmx_sso_sl_ppx_tag_cn73xx {
2299 u64 tailc : 1;
2300 u64 reserved_58_62 : 5;
2301 u64 index : 10;
2302 u64 reserved_44_47 : 4;
2303 u64 grp : 8;
2304 u64 head : 1;
2305 u64 tail : 1;
2306 u64 tt : 2;
2307 u64 tag : 32;
2308 } cn73xx;
2309 struct cvmx_sso_sl_ppx_tag_s cn78xx;
2310 struct cvmx_sso_sl_ppx_tag_s cn78xxp1;
2311 struct cvmx_sso_sl_ppx_tag_cn73xx cnf75xx;
2312 };
2313
2314 typedef union cvmx_sso_sl_ppx_tag cvmx_sso_sl_ppx_tag_t;
2315
2316 /**
2317 * cvmx_sso_sl_pp#_wqp
2318 *
2319 * Returns status of each core.
2320 *
2321 */
2322 union cvmx_sso_sl_ppx_wqp {
2323 u64 u64;
2324 struct cvmx_sso_sl_ppx_wqp_s {
2325 u64 reserved_58_63 : 6;
2326 u64 grp : 10;
2327 u64 reserved_42_47 : 6;
2328 u64 wqp : 42;
2329 } s;
2330 struct cvmx_sso_sl_ppx_wqp_cn73xx {
2331 u64 reserved_56_63 : 8;
2332 u64 grp : 8;
2333 u64 reserved_42_47 : 6;
2334 u64 wqp : 42;
2335 } cn73xx;
2336 struct cvmx_sso_sl_ppx_wqp_s cn78xx;
2337 struct cvmx_sso_sl_ppx_wqp_s cn78xxp1;
2338 struct cvmx_sso_sl_ppx_wqp_cn73xx cnf75xx;
2339 };
2340
2341 typedef union cvmx_sso_sl_ppx_wqp cvmx_sso_sl_ppx_wqp_t;
2342
2343 /**
2344 * cvmx_sso_taq#_link
2345 *
2346 * Returns TAQ status for a given line.
2347 *
2348 */
2349 union cvmx_sso_taqx_link {
2350 u64 u64;
2351 struct cvmx_sso_taqx_link_s {
2352 u64 reserved_11_63 : 53;
2353 u64 next : 11;
2354 } s;
2355 struct cvmx_sso_taqx_link_s cn73xx;
2356 struct cvmx_sso_taqx_link_s cn78xx;
2357 struct cvmx_sso_taqx_link_s cn78xxp1;
2358 struct cvmx_sso_taqx_link_s cnf75xx;
2359 };
2360
2361 typedef union cvmx_sso_taqx_link cvmx_sso_taqx_link_t;
2362
2363 /**
2364 * cvmx_sso_taq#_wae#_tag
2365 *
2366 * Returns TAQ status for a given line and WAE within that line.
2367 *
2368 */
2369 union cvmx_sso_taqx_waex_tag {
2370 u64 u64;
2371 struct cvmx_sso_taqx_waex_tag_s {
2372 u64 reserved_34_63 : 30;
2373 u64 tt : 2;
2374 u64 tag : 32;
2375 } s;
2376 struct cvmx_sso_taqx_waex_tag_s cn73xx;
2377 struct cvmx_sso_taqx_waex_tag_s cn78xx;
2378 struct cvmx_sso_taqx_waex_tag_s cn78xxp1;
2379 struct cvmx_sso_taqx_waex_tag_s cnf75xx;
2380 };
2381
2382 typedef union cvmx_sso_taqx_waex_tag cvmx_sso_taqx_waex_tag_t;
2383
2384 /**
2385 * cvmx_sso_taq#_wae#_wqp
2386 *
2387 * Returns TAQ status for a given line and WAE within that line.
2388 *
2389 */
2390 union cvmx_sso_taqx_waex_wqp {
2391 u64 u64;
2392 struct cvmx_sso_taqx_waex_wqp_s {
2393 u64 reserved_42_63 : 22;
2394 u64 wqp : 42;
2395 } s;
2396 struct cvmx_sso_taqx_waex_wqp_s cn73xx;
2397 struct cvmx_sso_taqx_waex_wqp_s cn78xx;
2398 struct cvmx_sso_taqx_waex_wqp_s cn78xxp1;
2399 struct cvmx_sso_taqx_waex_wqp_s cnf75xx;
2400 };
2401
2402 typedef union cvmx_sso_taqx_waex_wqp cvmx_sso_taqx_waex_wqp_t;
2403
2404 /**
2405 * cvmx_sso_taq_add
2406 */
2407 union cvmx_sso_taq_add {
2408 u64 u64;
2409 struct cvmx_sso_taq_add_s {
2410 u64 reserved_29_63 : 35;
2411 u64 rsvd_free : 13;
2412 u64 reserved_0_15 : 16;
2413 } s;
2414 struct cvmx_sso_taq_add_s cn73xx;
2415 struct cvmx_sso_taq_add_s cn78xx;
2416 struct cvmx_sso_taq_add_s cn78xxp1;
2417 struct cvmx_sso_taq_add_s cnf75xx;
2418 };
2419
2420 typedef union cvmx_sso_taq_add cvmx_sso_taq_add_t;
2421
2422 /**
2423 * cvmx_sso_taq_cnt
2424 */
2425 union cvmx_sso_taq_cnt {
2426 u64 u64;
2427 struct cvmx_sso_taq_cnt_s {
2428 u64 reserved_27_63 : 37;
2429 u64 rsvd_free : 11;
2430 u64 reserved_11_15 : 5;
2431 u64 free_cnt : 11;
2432 } s;
2433 struct cvmx_sso_taq_cnt_s cn73xx;
2434 struct cvmx_sso_taq_cnt_s cn78xx;
2435 struct cvmx_sso_taq_cnt_s cn78xxp1;
2436 struct cvmx_sso_taq_cnt_s cnf75xx;
2437 };
2438
2439 typedef union cvmx_sso_taq_cnt cvmx_sso_taq_cnt_t;
2440
2441 /**
2442 * cvmx_sso_tiaq#_status
2443 *
2444 * Returns TAQ inbound status indexed by group.
2445 *
2446 */
2447 union cvmx_sso_tiaqx_status {
2448 u64 u64;
2449 struct cvmx_sso_tiaqx_status_s {
2450 u64 wae_head : 4;
2451 u64 wae_tail : 4;
2452 u64 reserved_47_55 : 9;
2453 u64 wae_used : 15;
2454 u64 reserved_23_31 : 9;
2455 u64 ent_head : 11;
2456 u64 reserved_11_11 : 1;
2457 u64 ent_tail : 11;
2458 } s;
2459 struct cvmx_sso_tiaqx_status_s cn73xx;
2460 struct cvmx_sso_tiaqx_status_s cn78xx;
2461 struct cvmx_sso_tiaqx_status_s cn78xxp1;
2462 struct cvmx_sso_tiaqx_status_s cnf75xx;
2463 };
2464
2465 typedef union cvmx_sso_tiaqx_status cvmx_sso_tiaqx_status_t;
2466
2467 /**
2468 * cvmx_sso_toaq#_status
2469 *
2470 * Returns TAQ outbound status indexed by group.
2471 *
2472 */
2473 union cvmx_sso_toaqx_status {
2474 u64 u64;
2475 struct cvmx_sso_toaqx_status_s {
2476 u64 reserved_62_63 : 2;
2477 u64 ext_vld : 1;
2478 u64 partial : 1;
2479 u64 wae_tail : 4;
2480 u64 reserved_43_55 : 13;
2481 u64 cl_used : 11;
2482 u64 reserved_23_31 : 9;
2483 u64 ent_head : 11;
2484 u64 reserved_11_11 : 1;
2485 u64 ent_tail : 11;
2486 } s;
2487 struct cvmx_sso_toaqx_status_s cn73xx;
2488 struct cvmx_sso_toaqx_status_s cn78xx;
2489 struct cvmx_sso_toaqx_status_s cn78xxp1;
2490 struct cvmx_sso_toaqx_status_s cnf75xx;
2491 };
2492
2493 typedef union cvmx_sso_toaqx_status cvmx_sso_toaqx_status_t;
2494
2495 /**
2496 * cvmx_sso_ts_pc
2497 *
2498 * SSO_TS_PC = SSO Tag Switch Performance Counter
2499 *
2500 * Counts the number of tag switch requests.
2501 * Counter rolls over through zero when max value exceeded.
2502 */
2503 union cvmx_sso_ts_pc {
2504 u64 u64;
2505 struct cvmx_sso_ts_pc_s {
2506 u64 ts_pc : 64;
2507 } s;
2508 struct cvmx_sso_ts_pc_s cn68xx;
2509 struct cvmx_sso_ts_pc_s cn68xxp1;
2510 };
2511
2512 typedef union cvmx_sso_ts_pc cvmx_sso_ts_pc_t;
2513
2514 /**
2515 * cvmx_sso_wa_com_pc
2516 *
2517 * SSO_WA_COM_PC = SSO Work Add Combined Performance Counter
2518 *
2519 * Counts the number of add new work requests for all QOS levels.
2520 * Counter rolls over through zero when max value exceeded.
2521 */
2522 union cvmx_sso_wa_com_pc {
2523 u64 u64;
2524 struct cvmx_sso_wa_com_pc_s {
2525 u64 wa_pc : 64;
2526 } s;
2527 struct cvmx_sso_wa_com_pc_s cn68xx;
2528 struct cvmx_sso_wa_com_pc_s cn68xxp1;
2529 };
2530
2531 typedef union cvmx_sso_wa_com_pc cvmx_sso_wa_com_pc_t;
2532
2533 /**
2534 * cvmx_sso_wa_pc#
2535 *
2536 * CSR reserved addresses: (64): 0x4200..0x43f8
2537 * CSR align addresses: ===========================================================================================================
2538 * SSO_WA_PCX = SSO Work Add Performance Counter
2539 * (one per QOS level)
2540 *
2541 * Counts the number of add new work requests for each QOS level.
2542 * Counter rolls over through zero when max value exceeded.
2543 */
2544 union cvmx_sso_wa_pcx {
2545 u64 u64;
2546 struct cvmx_sso_wa_pcx_s {
2547 u64 wa_pc : 64;
2548 } s;
2549 struct cvmx_sso_wa_pcx_s cn68xx;
2550 struct cvmx_sso_wa_pcx_s cn68xxp1;
2551 };
2552
2553 typedef union cvmx_sso_wa_pcx cvmx_sso_wa_pcx_t;
2554
2555 /**
2556 * cvmx_sso_wq_int
2557 *
2558 * Note, the old POW offsets ran from 0x0 to 0x3f8, leaving the next available slot at 0x400.
2559 * To ensure no overlap, start on 4k boundary: 0x1000.
2560 * SSO_WQ_INT = SSO Work Queue Interrupt Register
2561 *
2562 * Contains the bits (one per group) that set work queue interrupts and are
2563 * used to clear these interrupts. For more information regarding this
2564 * register, see the interrupt section of the SSO spec.
2565 */
2566 union cvmx_sso_wq_int {
2567 u64 u64;
2568 struct cvmx_sso_wq_int_s {
2569 u64 wq_int : 64;
2570 } s;
2571 struct cvmx_sso_wq_int_s cn68xx;
2572 struct cvmx_sso_wq_int_s cn68xxp1;
2573 };
2574
2575 typedef union cvmx_sso_wq_int cvmx_sso_wq_int_t;
2576
2577 /**
2578 * cvmx_sso_wq_int_cnt#
2579 *
2580 * CSR reserved addresses: (64): 0x7200..0x73f8
2581 * CSR align addresses: ===========================================================================================================
2582 * SSO_WQ_INT_CNTX = SSO Work Queue Interrupt Count Register
2583 * (one per group)
2584 *
2585 * Contains a read-only copy of the counts used to trigger work queue
2586 * interrupts. For more information regarding this register, see the interrupt
2587 * section.
2588 */
2589 union cvmx_sso_wq_int_cntx {
2590 u64 u64;
2591 struct cvmx_sso_wq_int_cntx_s {
2592 u64 reserved_32_63 : 32;
2593 u64 tc_cnt : 4;
2594 u64 reserved_26_27 : 2;
2595 u64 ds_cnt : 12;
2596 u64 reserved_12_13 : 2;
2597 u64 iq_cnt : 12;
2598 } s;
2599 struct cvmx_sso_wq_int_cntx_s cn68xx;
2600 struct cvmx_sso_wq_int_cntx_s cn68xxp1;
2601 };
2602
2603 typedef union cvmx_sso_wq_int_cntx cvmx_sso_wq_int_cntx_t;
2604
2605 /**
2606 * cvmx_sso_wq_int_pc
2607 *
2608 * Contains the threshold value for the work-executable interrupt periodic counter and also a
2609 * read-only copy of the periodic counter. For more information on this register, refer to
2610 * Interrupts.
2611 */
2612 union cvmx_sso_wq_int_pc {
2613 u64 u64;
2614 struct cvmx_sso_wq_int_pc_s {
2615 u64 reserved_60_63 : 4;
2616 u64 pc : 28;
2617 u64 reserved_28_31 : 4;
2618 u64 pc_thr : 20;
2619 u64 reserved_0_7 : 8;
2620 } s;
2621 struct cvmx_sso_wq_int_pc_s cn68xx;
2622 struct cvmx_sso_wq_int_pc_s cn68xxp1;
2623 struct cvmx_sso_wq_int_pc_s cn73xx;
2624 struct cvmx_sso_wq_int_pc_s cn78xx;
2625 struct cvmx_sso_wq_int_pc_s cn78xxp1;
2626 struct cvmx_sso_wq_int_pc_s cnf75xx;
2627 };
2628
2629 typedef union cvmx_sso_wq_int_pc cvmx_sso_wq_int_pc_t;
2630
2631 /**
2632 * cvmx_sso_wq_int_thr#
2633 *
2634 * CSR reserved addresses: (96): 0x6100..0x63f8
2635 * CSR align addresses: ===========================================================================================================
2636 * SSO_WQ_INT_THR(0..63) = SSO Work Queue Interrupt Threshold Registers
2637 * (one per group)
2638 *
2639 * Contains the thresholds for enabling and setting work queue interrupts. For
2640 * more information, see the interrupt section.
2641 *
2642 * Note: Up to 16 of the SSO's internal storage buffers can be allocated
2643 * for hardware use and are therefore not available for incoming work queue
2644 * entries. Additionally, any WS that is not in the EMPTY state consumes a
2645 * buffer. Thus in a 32 PP system, it is not advisable to set either IQ_THR or
2646 * DS_THR to greater than 2048 - 16 - 32*2 = 1968. Doing so may prevent the
2647 * interrupt from ever triggering.
2648 *
2649 * Priorities for QOS levels 0..7
2650 */
2651 union cvmx_sso_wq_int_thrx {
2652 u64 u64;
2653 struct cvmx_sso_wq_int_thrx_s {
2654 u64 reserved_33_63 : 31;
2655 u64 tc_en : 1;
2656 u64 tc_thr : 4;
2657 u64 reserved_26_27 : 2;
2658 u64 ds_thr : 12;
2659 u64 reserved_12_13 : 2;
2660 u64 iq_thr : 12;
2661 } s;
2662 struct cvmx_sso_wq_int_thrx_s cn68xx;
2663 struct cvmx_sso_wq_int_thrx_s cn68xxp1;
2664 };
2665
2666 typedef union cvmx_sso_wq_int_thrx cvmx_sso_wq_int_thrx_t;
2667
2668 /**
2669 * cvmx_sso_wq_iq_dis
2670 *
2671 * CSR reserved addresses: (1): 0x1008..0x1008
2672 * SSO_WQ_IQ_DIS = SSO Input Queue Interrupt Temporary Disable Mask
2673 *
2674 * Contains the input queue interrupt temporary disable bits (one per group).
2675 * For more information regarding this register, see the interrupt section.
2676 */
2677 union cvmx_sso_wq_iq_dis {
2678 u64 u64;
2679 struct cvmx_sso_wq_iq_dis_s {
2680 u64 iq_dis : 64;
2681 } s;
2682 struct cvmx_sso_wq_iq_dis_s cn68xx;
2683 struct cvmx_sso_wq_iq_dis_s cn68xxp1;
2684 };
2685
2686 typedef union cvmx_sso_wq_iq_dis cvmx_sso_wq_iq_dis_t;
2687
2688 /**
2689 * cvmx_sso_ws_cfg
2690 *
2691 * This register contains various SSO work-slot configuration bits.
2692 *
2693 */
2694 union cvmx_sso_ws_cfg {
2695 u64 u64;
2696 struct cvmx_sso_ws_cfg_s {
2697 u64 reserved_56_63 : 8;
2698 u64 ocla_bp : 8;
2699 u64 reserved_7_47 : 41;
2700 u64 aw_clk_dis : 1;
2701 u64 gw_clk_dis : 1;
2702 u64 disable_pw : 1;
2703 u64 arbc_step_en : 1;
2704 u64 ncbo_step_en : 1;
2705 u64 soc_ccam_dis : 1;
2706 u64 sso_cclk_dis : 1;
2707 } s;
2708 struct cvmx_sso_ws_cfg_s cn73xx;
2709 struct cvmx_sso_ws_cfg_cn78xx {
2710 u64 reserved_56_63 : 8;
2711 u64 ocla_bp : 8;
2712 u64 reserved_5_47 : 43;
2713 u64 disable_pw : 1;
2714 u64 arbc_step_en : 1;
2715 u64 ncbo_step_en : 1;
2716 u64 soc_ccam_dis : 1;
2717 u64 sso_cclk_dis : 1;
2718 } cn78xx;
2719 struct cvmx_sso_ws_cfg_cn78xx cn78xxp1;
2720 struct cvmx_sso_ws_cfg_s cnf75xx;
2721 };
2722
2723 typedef union cvmx_sso_ws_cfg cvmx_sso_ws_cfg_t;
2724
2725 /**
2726 * cvmx_sso_ws_eco
2727 */
2728 union cvmx_sso_ws_eco {
2729 u64 u64;
2730 struct cvmx_sso_ws_eco_s {
2731 u64 reserved_8_63 : 56;
2732 u64 eco_rw : 8;
2733 } s;
2734 struct cvmx_sso_ws_eco_s cn73xx;
2735 struct cvmx_sso_ws_eco_s cnf75xx;
2736 };
2737
2738 typedef union cvmx_sso_ws_eco cvmx_sso_ws_eco_t;
2739
2740 /**
2741 * cvmx_sso_ws_pc#
2742 *
2743 * CSR reserved addresses: (225): 0x3100..0x3800
2744 * CSR align addresses: ===========================================================================================================
2745 * SSO_WS_PCX = SSO Work Schedule Performance Counter
2746 * (one per group)
2747 *
2748 * Counts the number of work schedules for each group.
2749 * Counter rolls over through zero when max value exceeded.
2750 */
2751 union cvmx_sso_ws_pcx {
2752 u64 u64;
2753 struct cvmx_sso_ws_pcx_s {
2754 u64 ws_pc : 64;
2755 } s;
2756 struct cvmx_sso_ws_pcx_s cn68xx;
2757 struct cvmx_sso_ws_pcx_s cn68xxp1;
2758 };
2759
2760 typedef union cvmx_sso_ws_pcx cvmx_sso_ws_pcx_t;
2761
2762 /**
2763 * cvmx_sso_xaq#_head_next
2764 *
2765 * These registers contain the pointer to the next buffer to become the head when the final cache
2766 * line in this buffer is read.
2767 */
2768 union cvmx_sso_xaqx_head_next {
2769 u64 u64;
2770 struct cvmx_sso_xaqx_head_next_s {
2771 u64 reserved_42_63 : 22;
2772 u64 ptr : 35;
2773 u64 reserved_0_6 : 7;
2774 } s;
2775 struct cvmx_sso_xaqx_head_next_s cn73xx;
2776 struct cvmx_sso_xaqx_head_next_s cn78xx;
2777 struct cvmx_sso_xaqx_head_next_s cn78xxp1;
2778 struct cvmx_sso_xaqx_head_next_s cnf75xx;
2779 };
2780
2781 typedef union cvmx_sso_xaqx_head_next cvmx_sso_xaqx_head_next_t;
2782
2783 /**
2784 * cvmx_sso_xaq#_head_ptr
2785 *
2786 * These registers contain the pointer to the first entry of the external linked list(s) for a
2787 * particular group. Software must initialize the external linked list(s) by programming
2788 * SSO_XAQ()_HEAD_PTR, SSO_XAQ()_HEAD_NEXT, SSO_XAQ()_TAIL_PTR and
2789 * SSO_XAQ()_TAIL_NEXT to identical values.
2790 */
2791 union cvmx_sso_xaqx_head_ptr {
2792 u64 u64;
2793 struct cvmx_sso_xaqx_head_ptr_s {
2794 u64 reserved_42_63 : 22;
2795 u64 ptr : 35;
2796 u64 reserved_5_6 : 2;
2797 u64 cl : 5;
2798 } s;
2799 struct cvmx_sso_xaqx_head_ptr_s cn73xx;
2800 struct cvmx_sso_xaqx_head_ptr_s cn78xx;
2801 struct cvmx_sso_xaqx_head_ptr_s cn78xxp1;
2802 struct cvmx_sso_xaqx_head_ptr_s cnf75xx;
2803 };
2804
2805 typedef union cvmx_sso_xaqx_head_ptr cvmx_sso_xaqx_head_ptr_t;
2806
2807 /**
2808 * cvmx_sso_xaq#_tail_next
2809 *
2810 * These registers contain the pointer to the next buffer to become the tail when the final cache
2811 * line in this buffer is written. Register fields are identical to those in
2812 * SSO_XAQ()_HEAD_NEXT above.
2813 */
2814 union cvmx_sso_xaqx_tail_next {
2815 u64 u64;
2816 struct cvmx_sso_xaqx_tail_next_s {
2817 u64 reserved_42_63 : 22;
2818 u64 ptr : 35;
2819 u64 reserved_0_6 : 7;
2820 } s;
2821 struct cvmx_sso_xaqx_tail_next_s cn73xx;
2822 struct cvmx_sso_xaqx_tail_next_s cn78xx;
2823 struct cvmx_sso_xaqx_tail_next_s cn78xxp1;
2824 struct cvmx_sso_xaqx_tail_next_s cnf75xx;
2825 };
2826
2827 typedef union cvmx_sso_xaqx_tail_next cvmx_sso_xaqx_tail_next_t;
2828
2829 /**
2830 * cvmx_sso_xaq#_tail_ptr
2831 *
2832 * These registers contain the pointer to the last entry of the external linked list(s) for a
2833 * particular group. Register fields are identical to those in SSO_XAQ()_HEAD_PTR above.
2834 * Software must initialize the external linked list(s) by programming
2835 * SSO_XAQ()_HEAD_PTR, SSO_XAQ()_HEAD_NEXT, SSO_XAQ()_TAIL_PTR and
2836 * SSO_XAQ()_TAIL_NEXT to identical values.
2837 */
2838 union cvmx_sso_xaqx_tail_ptr {
2839 u64 u64;
2840 struct cvmx_sso_xaqx_tail_ptr_s {
2841 u64 reserved_42_63 : 22;
2842 u64 ptr : 35;
2843 u64 reserved_5_6 : 2;
2844 u64 cl : 5;
2845 } s;
2846 struct cvmx_sso_xaqx_tail_ptr_s cn73xx;
2847 struct cvmx_sso_xaqx_tail_ptr_s cn78xx;
2848 struct cvmx_sso_xaqx_tail_ptr_s cn78xxp1;
2849 struct cvmx_sso_xaqx_tail_ptr_s cnf75xx;
2850 };
2851
2852 typedef union cvmx_sso_xaqx_tail_ptr cvmx_sso_xaqx_tail_ptr_t;
2853
2854 /**
2855 * cvmx_sso_xaq_aura
2856 */
2857 union cvmx_sso_xaq_aura {
2858 u64 u64;
2859 struct cvmx_sso_xaq_aura_s {
2860 u64 reserved_12_63 : 52;
2861 u64 node : 2;
2862 u64 laura : 10;
2863 } s;
2864 struct cvmx_sso_xaq_aura_s cn73xx;
2865 struct cvmx_sso_xaq_aura_s cn78xx;
2866 struct cvmx_sso_xaq_aura_s cn78xxp1;
2867 struct cvmx_sso_xaq_aura_s cnf75xx;
2868 };
2869
2870 typedef union cvmx_sso_xaq_aura cvmx_sso_xaq_aura_t;
2871
2872 /**
2873 * cvmx_sso_xaq_latency_pc
2874 */
2875 union cvmx_sso_xaq_latency_pc {
2876 u64 u64;
2877 struct cvmx_sso_xaq_latency_pc_s {
2878 u64 count : 64;
2879 } s;
2880 struct cvmx_sso_xaq_latency_pc_s cn73xx;
2881 struct cvmx_sso_xaq_latency_pc_s cn78xx;
2882 struct cvmx_sso_xaq_latency_pc_s cn78xxp1;
2883 struct cvmx_sso_xaq_latency_pc_s cnf75xx;
2884 };
2885
2886 typedef union cvmx_sso_xaq_latency_pc cvmx_sso_xaq_latency_pc_t;
2887
2888 /**
2889 * cvmx_sso_xaq_req_pc
2890 */
2891 union cvmx_sso_xaq_req_pc {
2892 u64 u64;
2893 struct cvmx_sso_xaq_req_pc_s {
2894 u64 count : 64;
2895 } s;
2896 struct cvmx_sso_xaq_req_pc_s cn73xx;
2897 struct cvmx_sso_xaq_req_pc_s cn78xx;
2898 struct cvmx_sso_xaq_req_pc_s cn78xxp1;
2899 struct cvmx_sso_xaq_req_pc_s cnf75xx;
2900 };
2901
2902 typedef union cvmx_sso_xaq_req_pc cvmx_sso_xaq_req_pc_t;
2903
2904 #endif
2905