1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 Atmel Corporation
4 * Copyright (C) 2019 Stefan Roese <sr@denx.de>
5 */
6
7 #include <common.h>
8 #include <nand.h>
9 #include <spl.h>
10 #include <asm/arch/at91sam9x5_matrix.h>
11 #include <asm/arch/at91sam9_smc.h>
12 #include <asm/arch/atmel_mpddrc.h>
13 #include <asm/arch/clk.h>
14 #include <asm/arch/gpio.h>
15
at91sam9x5ek_nand_hw_init(void)16 static void at91sam9x5ek_nand_hw_init(void)
17 {
18 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
19 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
20 unsigned long csa;
21
22 /* Enable CS3 */
23 csa = readl(&matrix->ebicsa);
24 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
25
26 /* NAND flash on D16 */
27 csa |= AT91_MATRIX_NFD0_ON_D16;
28
29 /* Configure IO drive */
30 csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
31
32 writel(csa, &matrix->ebicsa);
33
34 /* Configure SMC CS3 for NAND/SmartMedia */
35 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
36 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
37 &smc->cs[3].setup);
38 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
39 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
40 &smc->cs[3].pulse);
41 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
42 &smc->cs[3].cycle);
43 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
44 AT91_SMC_MODE_EXNW_DISABLE |
45 #ifdef CONFIG_SYS_NAND_DBW_16
46 AT91_SMC_MODE_DBW_16 |
47 #else /* CONFIG_SYS_NAND_DBW_8 */
48 AT91_SMC_MODE_DBW_8 |
49 #endif
50 AT91_SMC_MODE_TDF_CYCLE(1),
51 &smc->cs[3].mode);
52
53 at91_periph_clk_enable(ATMEL_ID_PIOCD);
54
55 /* Configure RDY/BSY */
56 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
57
58 /* Enable NandFlash */
59 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
60
61 at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
62 at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
63 at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
64 at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
65 at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
66 at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
67 at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
68 at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
69 at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
70 at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
71 at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
72 at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
73 }
74
at91_spl_board_init(void)75 void at91_spl_board_init(void)
76 {
77 at91sam9x5ek_nand_hw_init();
78 }
79
ddr2_conf(struct atmel_mpddrc_config * ddr2)80 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
81 {
82 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
83
84 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
85 ATMEL_MPDDRC_CR_NR_ROW_13 |
86 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
87 ATMEL_MPDDRC_CR_NB_8BANKS |
88 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
89
90 ddr2->rtr = 0x411;
91
92 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
93 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
94 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
95 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
96 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
97 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
98 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
99 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
100
101 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
102 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
103 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
104 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
105
106 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
107 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
108 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
109 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
110 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
111 }
112
mem_init(void)113 void mem_init(void)
114 {
115 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
116 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
117 struct atmel_mpddrc_config ddr2;
118 unsigned long csa;
119
120 ddr2_conf(&ddr2);
121
122 /* Enable DDR2 clock */
123 writel(AT91_PMC_DDR, &pmc->scer);
124
125 /* Chip select 1 is for DDR2/SDRAM */
126 csa = readl(&matrix->ebicsa);
127 csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
128 csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
129 csa |= AT91_MATRIX_EBI_DBPD_OFF;
130 csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
131 writel(csa, &matrix->ebicsa);
132
133 /* DDRAM2 Controller initialize */
134 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
135 }
136