1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Technexion Ltd.
4 *
5 * Author: Richard Hu <richard.hu@technexion.com>
6 * Fabio Estevam <festevam@gmail.com>
7 */
8
9 #include <common.h>
10 #include <image.h>
11 #include <init.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/iomux.h>
15 #include <asm/arch/mx6-pins.h>
16 #include <linux/delay.h>
17 #include <linux/errno.h>
18 #include <asm/gpio.h>
19 #include <asm/mach-imx/iomux-v3.h>
20 #include <asm/mach-imx/video.h>
21 #include <mmc.h>
22 #include <fsl_esdhc_imx.h>
23 #include <asm/arch/crm_regs.h>
24 #include <asm/io.h>
25 #include <asm/arch/sys_proto.h>
26 #include <spl.h>
27
28 #if defined(CONFIG_SPL_BUILD)
29 #include <asm/arch/mx6-ddr.h>
30
31 #define IMX6DQ_DRIVE_STRENGTH 0x30
32 #define IMX6SDL_DRIVE_STRENGTH 0x28
33
34 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)35 int spl_start_uboot(void)
36 {
37 /* Break into full U-Boot on 'c' */
38 if (serial_tstc() && serial_getc() == 'c')
39 return 1;
40
41 return 0;
42 }
43 #endif
44
45 /* configure MX6Q/DUAL mmdc DDR io registers */
46 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
47 .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
48 .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
49 .dram_cas = IMX6DQ_DRIVE_STRENGTH,
50 .dram_ras = IMX6DQ_DRIVE_STRENGTH,
51 .dram_reset = IMX6DQ_DRIVE_STRENGTH,
52 .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
53 .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
54 .dram_sdba2 = 0x00000000,
55 .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
56 .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
57 .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
58 .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
59 .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
60 .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
61 .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
62 .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
63 .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
64 .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
65 .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
66 .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
67 .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
68 .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
69 .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
70 .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
71 .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
72 .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
73 };
74
75 /* configure MX6Q/DUAL mmdc GRP io registers */
76 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
77 .grp_ddr_type = 0x000c0000,
78 .grp_ddrmode_ctl = 0x00020000,
79 .grp_ddrpke = 0x00000000,
80 .grp_addds = IMX6DQ_DRIVE_STRENGTH,
81 .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
82 .grp_ddrmode = 0x00020000,
83 .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
84 .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
85 .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
86 .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
87 .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
88 .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
89 .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
90 .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
91 };
92
93 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
94 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
95 .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
96 .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
97 .dram_cas = IMX6SDL_DRIVE_STRENGTH,
98 .dram_ras = IMX6SDL_DRIVE_STRENGTH,
99 .dram_reset = IMX6SDL_DRIVE_STRENGTH,
100 .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
101 .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
102 .dram_sdba2 = 0x00000000,
103 .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
104 .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
105 .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
106 .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
107 .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
108 .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
109 .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
110 .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
111 .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
112 .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
113 .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
114 .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
115 .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
116 .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
117 .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
118 .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
119 .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
120 .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
121 };
122
123 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
124 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
125 .grp_ddr_type = 0x000c0000,
126 .grp_ddrmode_ctl = 0x00020000,
127 .grp_ddrpke = 0x00000000,
128 .grp_addds = IMX6SDL_DRIVE_STRENGTH,
129 .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
130 .grp_ddrmode = 0x00020000,
131 .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
132 .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
133 .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
134 .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
135 .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
136 .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
137 .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
138 .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
139 };
140
141 /* H5T04G63AFR-PB for i.mx6Solo/DL operating DDR at 400MHz */
142 static struct mx6_ddr3_cfg h5t04g63afr = {
143 .mem_speed = 800,
144 .density = 4,
145 .width = 16,
146 .banks = 8,
147 .rowaddr = 15,
148 .coladdr = 10,
149 .pagesz = 2,
150 .trcd = 1500,
151 .trcmin = 5250,
152 .trasmin = 3750,
153 };
154
155 /* H5TQ2G63FFR-H9 for i.mx6Solo/DL operating DDR at 400MHz */
156 static struct mx6_ddr3_cfg h5tq2g63ffr = {
157 .mem_speed = 800,
158 .density = 2,
159 .width = 16,
160 .banks = 8,
161 .rowaddr = 14,
162 .coladdr = 10,
163 .pagesz = 2,
164 .trcd = 1500,
165 .trcmin = 5250,
166 .trasmin = 3750,
167 };
168
169 static struct mx6_mmdc_calibration mx6q_1g_mmdc_calib = {
170 .p0_mpwldectrl0 = 0x00000000,
171 .p0_mpwldectrl1 = 0x00000000,
172 .p1_mpwldectrl0 = 0x00000000,
173 .p1_mpwldectrl1 = 0x00000000,
174 .p0_mpdgctrl0 = 0x032C0340,
175 .p0_mpdgctrl1 = 0x03300324,
176 .p1_mpdgctrl0 = 0x032C0338,
177 .p1_mpdgctrl1 = 0x03300274,
178 .p0_mprddlctl = 0x423A383E,
179 .p1_mprddlctl = 0x3638323E,
180 .p0_mpwrdlctl = 0x363C4640,
181 .p1_mpwrdlctl = 0x4034423C,
182 };
183
184 /* DDR 32bit */
185 static struct mx6_ddr_sysinfo mem_s = {
186 .dsize = 1,
187 .cs1_mirror = 0,
188 /* config for full 4GB range so that get_mem_size() works */
189 .cs_density = 32,
190 .ncs = 1,
191 .bi_on = 1,
192 .rtt_nom = 1,
193 .rtt_wr = 0,
194 .ralat = 5,
195 .walat = 0,
196 .mif3_mode = 3,
197 .rst_to_cke = 0x23,
198 .sde_to_rst = 0x10,
199 };
200
201 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
202 .p0_mpwldectrl0 = 0x001f001f,
203 .p0_mpwldectrl1 = 0x001f001f,
204 .p1_mpwldectrl0 = 0x001f001f,
205 .p1_mpwldectrl1 = 0x001f001f,
206 .p0_mpdgctrl0 = 0x420e020e,
207 .p0_mpdgctrl1 = 0x02000200,
208 .p1_mpdgctrl0 = 0x42020202,
209 .p1_mpdgctrl1 = 0x01720172,
210 .p0_mprddlctl = 0x494c4f4c,
211 .p1_mprddlctl = 0x4a4c4c49,
212 .p0_mpwrdlctl = 0x3f3f3133,
213 .p1_mpwrdlctl = 0x39373f2e,
214 };
215
216 static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
217 .p0_mpwldectrl0 = 0x0040003c,
218 .p0_mpwldectrl1 = 0x0032003e,
219 .p0_mpdgctrl0 = 0x42350231,
220 .p0_mpdgctrl1 = 0x021a0218,
221 .p0_mprddlctl = 0x4b4b4e49,
222 .p0_mpwrdlctl = 0x3f3f3035,
223 };
224
ccgr_init(void)225 static void ccgr_init(void)
226 {
227 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
228
229 writel(0x00C03F3F, &ccm->CCGR0);
230 writel(0x0030FC03, &ccm->CCGR1);
231 writel(0x0FFFC000, &ccm->CCGR2);
232 writel(0x3FF03000, &ccm->CCGR3);
233 writel(0x00FFF300, &ccm->CCGR4);
234 writel(0x0F0000C3, &ccm->CCGR5);
235 writel(0x000003FF, &ccm->CCGR6);
236 }
237
spl_dram_init(void)238 static void spl_dram_init(void)
239 {
240 if (is_mx6solo()) {
241 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
242 mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63ffr);
243 } else if (is_mx6dl()) {
244 mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
245 mx6_dram_cfg(&mem_s, &mx6dl_1g_mmdc_calib, &h5t04g63afr);
246 } else if (is_mx6dq()) {
247 mx6dq_dram_iocfg(32, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
248 mx6_dram_cfg(&mem_s, &mx6q_1g_mmdc_calib, &h5t04g63afr);
249 }
250
251 udelay(100);
252 }
253
board_init_f(ulong dummy)254 void board_init_f(ulong dummy)
255 {
256 ccgr_init();
257
258 /* setup AIPS and disable watchdog */
259 arch_cpu_init();
260
261 gpr_init();
262
263 /* iomux */
264 board_early_init_f();
265
266 /* setup GP timer */
267 timer_init();
268
269 /* UART clocks enabled and gd valid - init serial console */
270 preloader_console_init();
271
272 /* DDR initialization */
273 spl_dram_init();
274 }
275
276 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
277 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
278 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
279
280 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
281 {USDHC3_BASE_ADDR},
282 };
283
284 static iomux_v3_cfg_t const usdhc3_pads[] = {
285 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
286 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
287 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
288 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
289 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
290 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
291 /* SOM MicroSD Card Detect */
292 IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
293 };
294
board_mmc_getcd(struct mmc * mmc)295 int board_mmc_getcd(struct mmc *mmc)
296 {
297 return 1;
298 }
299
board_mmc_init(struct bd_info * bis)300 int board_mmc_init(struct bd_info *bis)
301 {
302 SETUP_IOMUX_PADS(usdhc3_pads);
303 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
304 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
305 }
306 #endif
307
308 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)309 int board_fit_config_name_match(const char *name)
310 {
311 if (is_mx6dq() && !strcmp(name, "imx6q-pico"))
312 return 0;
313 else if ((is_mx6dl() || is_mx6solo()) && !strcmp(name, "imx6dl-pico"))
314 return 0;
315
316 return -EINVAL;
317 }
318 #endif
319