1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * (C) Copyright 2019
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 *
6 */
7 #include <common.h>
8 #include <asm/bitops.h>
9 #include <asm/cpm_85xx.h>
10 #include <pci.h>
11 #include <dm.h>
12 #include <asm/fsl_law.h>
13
14 struct mpc85xx_pci_priv {
15 void __iomem *cfg_addr;
16 void __iomem *cfg_data;
17 };
18
mpc85xx_pci_dm_read_config(const struct udevice * dev,pci_dev_t bdf,uint offset,ulong * value,enum pci_size_t size)19 static int mpc85xx_pci_dm_read_config(const struct udevice *dev, pci_dev_t bdf,
20 uint offset, ulong *value,
21 enum pci_size_t size)
22 {
23 struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
24 u32 addr;
25
26 addr = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
27 out_be32(priv->cfg_addr, addr);
28 sync();
29 *value = pci_conv_32_to_size(in_le32(priv->cfg_data), offset, size);
30
31 return 0;
32 }
33
mpc85xx_pci_dm_write_config(struct udevice * dev,pci_dev_t bdf,uint offset,ulong value,enum pci_size_t size)34 static int mpc85xx_pci_dm_write_config(struct udevice *dev, pci_dev_t bdf,
35 uint offset, ulong value,
36 enum pci_size_t size)
37 {
38 struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
39 u32 addr;
40
41 addr = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
42 out_be32(priv->cfg_addr, addr);
43 sync();
44 out_le32(priv->cfg_data, pci_conv_size_to_32(0, value, offset, size));
45
46 return 0;
47 }
48
49 #ifdef CONFIG_FSL_LAW
50 static int
mpc85xx_pci_dm_setup_laws(struct pci_region * io,struct pci_region * mem,struct pci_region * pre)51 mpc85xx_pci_dm_setup_laws(struct pci_region *io, struct pci_region *mem,
52 struct pci_region *pre)
53 {
54 /*
55 * Unfortunately we have defines for this addresse,
56 * as we have to setup the TLB, and at this stage
57 * we have no access to DT ... may we check here
58 * if the value in the define is the same ?
59 */
60 if (mem)
61 set_next_law(mem->phys_start, law_size_bits(mem->size),
62 LAW_TRGT_IF_PCI);
63 if (io)
64 set_next_law(io->phys_start, law_size_bits(io->size),
65 LAW_TRGT_IF_PCI);
66 if (pre)
67 set_next_law(pre->phys_start, law_size_bits(pre->size),
68 LAW_TRGT_IF_PCI);
69
70 return 0;
71 }
72 #endif
73
mpc85xx_pci_dm_probe(struct udevice * dev)74 static int mpc85xx_pci_dm_probe(struct udevice *dev)
75 {
76 struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
77 struct pci_region *io;
78 struct pci_region *mem;
79 struct pci_region *pre;
80 int count;
81 ccsr_pcix_t *pcix;
82
83 count = pci_get_regions(dev, &io, &mem, &pre);
84 if (count != 2) {
85 printf("%s: wrong count of regions %d only 2 allowed\n",
86 __func__, count);
87 return -EINVAL;
88 }
89
90 #ifdef CONFIG_FSL_LAW
91 mpc85xx_pci_dm_setup_laws(io, mem, pre);
92 #endif
93
94 pcix = priv->cfg_addr;
95 /* BAR 1: memory */
96 out_be32(&pcix->potar1, mem->bus_start >> 12);
97 out_be32(&pcix->potear1, (u64)mem->bus_start >> 44);
98 out_be32(&pcix->powbar1, mem->phys_start >> 12);
99 out_be32(&pcix->powbear1, (u64)mem->phys_start >> 44);
100 out_be32(&pcix->powar1, (POWAR_EN | POWAR_MEM_READ |
101 POWAR_MEM_WRITE | (__ilog2(mem->size) - 1)));
102
103 /* BAR 1: IO */
104 out_be32(&pcix->potar2, io->bus_start >> 12);
105 out_be32(&pcix->potear2, (u64)io->bus_start >> 44);
106 out_be32(&pcix->powbar2, io->phys_start >> 12);
107 out_be32(&pcix->powbear2, (u64)io->phys_start >> 44);
108 out_be32(&pcix->powar2, (POWAR_EN | POWAR_IO_READ |
109 POWAR_IO_WRITE | (__ilog2(io->size) - 1)));
110
111 out_be32(&pcix->pitar1, 0);
112 out_be32(&pcix->piwbar1, 0);
113 out_be32(&pcix->piwar1, (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
114 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G));
115
116 out_be32(&pcix->powar3, 0);
117 out_be32(&pcix->powar4, 0);
118 out_be32(&pcix->piwar2, 0);
119 out_be32(&pcix->piwar3, 0);
120
121 return 0;
122 }
123
mpc85xx_pci_dm_remove(struct udevice * dev)124 static int mpc85xx_pci_dm_remove(struct udevice *dev)
125 {
126 return 0;
127 }
128
mpc85xx_pci_of_to_plat(struct udevice * dev)129 static int mpc85xx_pci_of_to_plat(struct udevice *dev)
130 {
131 struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
132 fdt_addr_t addr;
133
134 addr = devfdt_get_addr_index(dev, 0);
135 if (addr == FDT_ADDR_T_NONE)
136 return -EINVAL;
137 priv->cfg_addr = (void __iomem *)map_physmem(addr, 0, MAP_NOCACHE);
138 priv->cfg_data = (void __iomem *)((ulong)priv->cfg_addr + 4);
139
140 return 0;
141 }
142
143 static const struct dm_pci_ops mpc85xx_pci_ops = {
144 .read_config = mpc85xx_pci_dm_read_config,
145 .write_config = mpc85xx_pci_dm_write_config,
146 };
147
148 static const struct udevice_id mpc85xx_pci_ids[] = {
149 { .compatible = "fsl,mpc8540-pci" },
150 { }
151 };
152
153 U_BOOT_DRIVER(mpc85xx_pci) = {
154 .name = "mpc85xx_pci",
155 .id = UCLASS_PCI,
156 .of_match = mpc85xx_pci_ids,
157 .ops = &mpc85xx_pci_ops,
158 .probe = mpc85xx_pci_dm_probe,
159 .remove = mpc85xx_pci_dm_remove,
160 .of_to_plat = mpc85xx_pci_of_to_plat,
161 .priv_auto = sizeof(struct mpc85xx_pci_priv),
162 };
163