1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2010-2011 Freescale Semiconductor, Inc. 4 * Copyright 2020 NXP 5 */ 6 7 /* 8 * P010 RDB board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include <linux/stringify.h> 15 16 #include <asm/config_mpc85xx.h> 17 #define CONFIG_NAND_FSL_IFC 18 19 #ifdef CONFIG_SDCARD 20 #define CONFIG_SPL_FLUSH_IMAGE 21 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 22 #define CONFIG_SPL_PAD_TO 0x18000 23 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 24 #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) 25 #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) 26 #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) 27 #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) 28 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 29 #ifdef CONFIG_SPL_BUILD 30 #define CONFIG_SPL_COMMON_INIT_DDR 31 #endif 32 #endif 33 34 #ifdef CONFIG_SPIFLASH 35 #ifdef CONFIG_NXP_ESBC 36 #define CONFIG_RAMBOOT_SPIFLASH 37 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 38 #else 39 #define CONFIG_SPL_SPI_FLASH_MINIMAL 40 #define CONFIG_SPL_FLUSH_IMAGE 41 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 42 #define CONFIG_SPL_PAD_TO 0x18000 43 #define CONFIG_SPL_MAX_SIZE (96 * 1024) 44 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) 45 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) 46 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) 47 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) 48 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 49 #ifdef CONFIG_SPL_BUILD 50 #define CONFIG_SPL_COMMON_INIT_DDR 51 #endif 52 #endif 53 #endif 54 55 #ifdef CONFIG_MTD_RAW_NAND 56 #ifdef CONFIG_NXP_ESBC 57 #define CONFIG_SPL_INIT_MINIMAL 58 #define CONFIG_SPL_FLUSH_IMAGE 59 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 60 61 #define CONFIG_SPL_MAX_SIZE 8192 62 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 63 #define CONFIG_SPL_RELOC_STACK 0x00100000 64 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 65 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 66 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 67 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 68 #else 69 #ifdef CONFIG_TPL_BUILD 70 #define CONFIG_SPL_FLUSH_IMAGE 71 #define CONFIG_SPL_NAND_INIT 72 #define CONFIG_SPL_COMMON_INIT_DDR 73 #define CONFIG_SPL_MAX_SIZE (128 << 10) 74 #define CONFIG_TPL_TEXT_BASE 0xD0001000 75 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 76 #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) 77 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 78 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 79 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 80 #elif defined(CONFIG_SPL_BUILD) 81 #define CONFIG_SPL_INIT_MINIMAL 82 #define CONFIG_SPL_NAND_MINIMAL 83 #define CONFIG_SPL_FLUSH_IMAGE 84 #define CONFIG_SPL_MAX_SIZE 8192 85 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 86 #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 87 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 88 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 89 #endif 90 #define CONFIG_SPL_PAD_TO 0x20000 91 #define CONFIG_TPL_PAD_TO 0x20000 92 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 93 #endif 94 #endif 95 96 #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ 97 #define CONFIG_RAMBOOT_NAND 98 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 99 #endif 100 101 #ifndef CONFIG_RESET_VECTOR_ADDRESS 102 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 103 #endif 104 105 #ifdef CONFIG_TPL_BUILD 106 #define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE 107 #elif defined(CONFIG_SPL_BUILD) 108 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 109 #else 110 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 111 #endif 112 113 /* High Level Configuration Options */ 114 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 115 116 #if defined(CONFIG_PCI) 117 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 118 #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ 119 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 120 121 /* 122 * PCI Windows 123 * Memory space is mapped 1-1, but I/O space must start from 0. 124 */ 125 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 126 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 127 #ifdef CONFIG_PHYS_64BIT 128 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 129 #else 130 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 131 #endif 132 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 133 #ifdef CONFIG_PHYS_64BIT 134 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 135 #else 136 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 137 #endif 138 139 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 140 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 141 #ifdef CONFIG_PHYS_64BIT 142 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 143 #else 144 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 145 #endif 146 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 147 #ifdef CONFIG_PHYS_64BIT 148 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 149 #else 150 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 151 #endif 152 153 #if !defined(CONFIG_DM_PCI) 154 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 155 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 156 #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" 157 #ifdef CONFIG_PHYS_64BIT 158 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 159 #else 160 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 161 #endif 162 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 163 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 164 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 165 166 #if defined(CONFIG_TARGET_P1010RDB_PA) 167 #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" 168 #elif defined(CONFIG_TARGET_P1010RDB_PB) 169 #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" 170 #endif 171 #ifdef CONFIG_PHYS_64BIT 172 #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 173 #else 174 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 175 #endif 176 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 177 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 178 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 179 #endif 180 181 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 182 #endif 183 184 #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ 185 #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ 186 187 #define CONFIG_HWCONFIG 188 /* 189 * These can be toggled for performance analysis, otherwise use default. 190 */ 191 #define CONFIG_L2_CACHE /* toggle L2 cache */ 192 #define CONFIG_BTB /* toggle branch predition */ 193 194 195 #define CONFIG_ENABLE_36BIT_PHYS 196 197 /* DDR Setup */ 198 #define CONFIG_SYS_DDR_RAW_TIMING 199 #define CONFIG_DDR_SPD 200 #define CONFIG_SYS_SPD_BUS_NUM 1 201 #define SPD_EEPROM_ADDRESS 0x52 202 203 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 204 205 #ifndef __ASSEMBLY__ 206 extern unsigned long get_sdram_size(void); 207 #endif 208 #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ 209 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 210 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 211 212 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 213 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 214 215 /* DDR3 Controller Settings */ 216 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f 217 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 218 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 219 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 220 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 221 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 222 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 223 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 224 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 225 #define CONFIG_SYS_DDR_RCW_1 0x00000000 226 #define CONFIG_SYS_DDR_RCW_2 0x00000000 227 #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ 228 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 229 #define CONFIG_SYS_DDR_TIMING_4 0x00000001 230 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 231 232 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 233 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 234 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 235 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF 236 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 237 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 238 #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 239 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 240 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 241 242 /* settings for DDR3 at 667MT/s */ 243 #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 244 #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 245 #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 246 #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD 247 #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 248 #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 249 #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 250 #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 251 #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 252 253 #define CONFIG_SYS_CCSRBAR 0xffe00000 254 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 255 256 /* Don't relocate CCSRBAR while in NAND_SPL */ 257 #ifdef CONFIG_SPL_BUILD 258 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 259 #endif 260 261 /* 262 * Memory map 263 * 264 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable 265 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable 266 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable 267 * 268 * Localbus non-cacheable 269 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable 270 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable 271 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 272 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 273 */ 274 275 /* 276 * IFC Definitions 277 */ 278 /* NOR Flash on IFC */ 279 280 #define CONFIG_SYS_FLASH_BASE 0xee000000 281 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ 282 283 #ifdef CONFIG_PHYS_64BIT 284 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 285 #else 286 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 287 #endif 288 289 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 290 CSPR_PORT_SIZE_16 | \ 291 CSPR_MSEL_NOR | \ 292 CSPR_V) 293 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) 294 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) 295 /* NOR Flash Timing Params */ 296 #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ 297 FTIM0_NOR_TEADC(0x5) | \ 298 FTIM0_NOR_TEAHC(0x5) 299 #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ 300 FTIM1_NOR_TRAD_NOR(0x0f) 301 #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ 302 FTIM2_NOR_TCH(0x4) | \ 303 FTIM2_NOR_TWP(0x1c) 304 #define CONFIG_SYS_NOR_FTIM3 0x0 305 306 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 307 #define CONFIG_SYS_FLASH_QUIET_TEST 308 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 309 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 310 311 #undef CONFIG_SYS_FLASH_CHECKSUM 312 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 313 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 314 315 /* CFI for NOR Flash */ 316 #define CONFIG_SYS_FLASH_EMPTY_INFO 317 318 /* NAND Flash on IFC */ 319 #define CONFIG_SYS_NAND_BASE 0xff800000 320 #ifdef CONFIG_PHYS_64BIT 321 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 322 #else 323 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 324 #endif 325 326 #define CONFIG_MTD_PARTITION 327 328 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 329 | CSPR_PORT_SIZE_8 \ 330 | CSPR_MSEL_NAND \ 331 | CSPR_V) 332 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 333 334 #if defined(CONFIG_TARGET_P1010RDB_PA) 335 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 336 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 337 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 338 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 339 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ 340 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ 341 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ 342 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) 343 344 #elif defined(CONFIG_TARGET_P1010RDB_PB) 345 #define CONFIG_SYS_NAND_ONFI_DETECTION 346 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 347 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 348 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 349 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 350 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 351 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 352 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ 353 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 354 #endif 355 356 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 357 #define CONFIG_SYS_MAX_NAND_DEVICE 1 358 359 #if defined(CONFIG_TARGET_P1010RDB_PA) 360 /* NAND Flash Timing Params */ 361 #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ 362 FTIM0_NAND_TWP(0x0C) | \ 363 FTIM0_NAND_TWCHT(0x04) | \ 364 FTIM0_NAND_TWH(0x05) 365 #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ 366 FTIM1_NAND_TWBE(0x1d) | \ 367 FTIM1_NAND_TRR(0x07) | \ 368 FTIM1_NAND_TRP(0x0c) 369 #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ 370 FTIM2_NAND_TREH(0x05) | \ 371 FTIM2_NAND_TWHRE(0x0f) 372 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 373 374 #elif defined(CONFIG_TARGET_P1010RDB_PB) 375 /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ 376 /* ONFI NAND Flash mode0 Timing Params */ 377 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ 378 FTIM0_NAND_TWP(0x18) | \ 379 FTIM0_NAND_TWCHT(0x07) | \ 380 FTIM0_NAND_TWH(0x0a)) 381 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ 382 FTIM1_NAND_TWBE(0x39) | \ 383 FTIM1_NAND_TRR(0x0e) | \ 384 FTIM1_NAND_TRP(0x18)) 385 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 386 FTIM2_NAND_TREH(0x0a) | \ 387 FTIM2_NAND_TWHRE(0x1e)) 388 #define CONFIG_SYS_NAND_FTIM3 0x0 389 #endif 390 391 #define CONFIG_SYS_NAND_DDR_LAW 11 392 393 /* Set up IFC registers for boot location NOR/NAND */ 394 #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT) 395 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 396 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 397 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 398 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 399 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 400 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 401 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 402 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 403 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 404 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 405 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 406 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 407 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 408 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 409 #else 410 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 411 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 412 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 413 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 414 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 415 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 416 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 417 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 418 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 419 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 420 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 421 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 422 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 423 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 424 #endif 425 426 /* CPLD on IFC */ 427 #define CONFIG_SYS_CPLD_BASE 0xffb00000 428 429 #ifdef CONFIG_PHYS_64BIT 430 #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull 431 #else 432 #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 433 #endif 434 435 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 436 | CSPR_PORT_SIZE_8 \ 437 | CSPR_MSEL_GPCM \ 438 | CSPR_V) 439 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) 440 #define CONFIG_SYS_CSOR3 0x0 441 /* CPLD Timing parameters for IFC CS3 */ 442 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 443 FTIM0_GPCM_TEADC(0x0e) | \ 444 FTIM0_GPCM_TEAHC(0x0e)) 445 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 446 FTIM1_GPCM_TRAD(0x1f)) 447 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 448 FTIM2_GPCM_TCH(0x8) | \ 449 FTIM2_GPCM_TWP(0x1f)) 450 #define CONFIG_SYS_CS3_FTIM3 0x0 451 452 #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ 453 defined(CONFIG_RAMBOOT_NAND) 454 #define CONFIG_SYS_RAMBOOT 455 #else 456 #undef CONFIG_SYS_RAMBOOT 457 #endif 458 459 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 460 #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) 461 #define CONFIG_A003399_NOR_WORKAROUND 462 #endif 463 #endif 464 465 #define CONFIG_SYS_INIT_RAM_LOCK 466 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 467 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 468 469 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 470 - GENERATED_GBL_DATA_SIZE) 471 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 472 473 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 474 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 475 476 /* 477 * Config the L2 Cache as L2 SRAM 478 */ 479 #if defined(CONFIG_SPL_BUILD) 480 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 481 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 482 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 483 #define CONFIG_SYS_L2_SIZE (256 << 10) 484 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 485 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 486 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 487 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 488 #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) 489 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) 490 #elif defined(CONFIG_MTD_RAW_NAND) 491 #ifdef CONFIG_TPL_BUILD 492 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 493 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 494 #define CONFIG_SYS_L2_SIZE (256 << 10) 495 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 496 #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 497 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 498 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 499 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 500 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 501 #else 502 #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 503 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 504 #define CONFIG_SYS_L2_SIZE (256 << 10) 505 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 506 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 507 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 508 #endif 509 #endif 510 #endif 511 512 /* Serial Port */ 513 #undef CONFIG_SERIAL_SOFTWARE_FIFO 514 #define CONFIG_SYS_NS16550_SERIAL 515 #define CONFIG_SYS_NS16550_REG_SIZE 1 516 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 517 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 518 #define CONFIG_NS16550_MIN_FUNCTIONS 519 #endif 520 521 #define CONFIG_SYS_BAUDRATE_TABLE \ 522 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 523 524 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 525 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 526 527 /* I2C */ 528 #if !CONFIG_IS_ENABLED(DM_I2C) 529 #define CONFIG_SYS_I2C 530 #define CONFIG_SYS_FSL_I2C_SPEED 400000 531 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 532 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 533 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 534 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 535 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 536 #else 537 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM 538 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 539 #endif 540 #define I2C_PCA9557_ADDR1 0x18 541 #define I2C_PCA9557_ADDR2 0x19 542 #define I2C_PCA9557_BUS_NUM 0 543 #define CONFIG_SYS_I2C_FSL 544 545 /* I2C EEPROM */ 546 #if defined(CONFIG_TARGET_P1010RDB_PB) 547 #define CONFIG_ID_EEPROM 548 #ifdef CONFIG_ID_EEPROM 549 #define CONFIG_SYS_I2C_EEPROM_NXID 550 #endif 551 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 552 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 553 #define CONFIG_SYS_EEPROM_BUS_NUM 0 554 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ 555 #endif 556 /* enable read and write access to EEPROM */ 557 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 558 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 559 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 560 561 /* RTC */ 562 #define CONFIG_RTC_PT7C4338 563 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 564 565 /* 566 * SPI interface will not be available in case of NAND boot SPI CS0 will be 567 * used for SLIC 568 */ 569 #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT) 570 /* eSPI - Enhanced SPI */ 571 #endif 572 573 #if defined(CONFIG_TSEC_ENET) 574 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 575 #define CONFIG_TSEC1 1 576 #define CONFIG_TSEC1_NAME "eTSEC1" 577 #define CONFIG_TSEC2 1 578 #define CONFIG_TSEC2_NAME "eTSEC2" 579 #define CONFIG_TSEC3 1 580 #define CONFIG_TSEC3_NAME "eTSEC3" 581 582 #define TSEC1_PHY_ADDR 1 583 #define TSEC2_PHY_ADDR 0 584 #define TSEC3_PHY_ADDR 2 585 586 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 587 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 588 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 589 590 #define TSEC1_PHYIDX 0 591 #define TSEC2_PHYIDX 0 592 #define TSEC3_PHYIDX 0 593 594 #define CONFIG_ETHPRIME "eTSEC1" 595 596 /* TBI PHY configuration for SGMII mode */ 597 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 598 TBICR_PHY_RESET \ 599 | TBICR_ANEG_ENABLE \ 600 | TBICR_FULL_DUPLEX \ 601 | TBICR_SPEED1_SET \ 602 ) 603 604 #endif /* CONFIG_TSEC_ENET */ 605 606 /* SATA */ 607 #define CONFIG_FSL_SATA_V2 608 609 #ifdef CONFIG_FSL_SATA 610 #define CONFIG_SYS_SATA_MAX_DEVICE 2 611 #define CONFIG_SATA1 612 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 613 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 614 #define CONFIG_SATA2 615 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 616 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 617 618 #define CONFIG_LBA48 619 #endif /* #ifdef CONFIG_FSL_SATA */ 620 621 #ifdef CONFIG_MMC 622 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 623 #endif 624 625 #define CONFIG_HAS_FSL_DR_USB 626 627 #if defined(CONFIG_HAS_FSL_DR_USB) 628 #ifdef CONFIG_USB_EHCI_HCD 629 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 630 #define CONFIG_USB_EHCI_FSL 631 #endif 632 #endif 633 634 /* 635 * Environment 636 */ 637 #if defined(CONFIG_SDCARD) 638 #define CONFIG_FSL_FIXED_MMC_LOCATION 639 #elif defined(CONFIG_MTD_RAW_NAND) 640 #ifdef CONFIG_TPL_BUILD 641 #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 642 #else 643 #if defined(CONFIG_TARGET_P1010RDB_PA) 644 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ 645 #elif defined(CONFIG_TARGET_P1010RDB_PB) 646 #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ 647 #endif 648 #endif 649 #endif 650 651 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 652 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 653 654 #undef CONFIG_WATCHDOG /* watchdog disabled */ 655 656 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \ 657 || defined(CONFIG_FSL_SATA) 658 #endif 659 660 /* 661 * Miscellaneous configurable options 662 */ 663 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 664 665 /* 666 * For booting Linux, the board info and command line data 667 * have to be in the first 64 MB of memory, since this is 668 * the maximum mapped by the Linux kernel during initialization. 669 */ 670 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 671 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 672 673 #if defined(CONFIG_CMD_KGDB) 674 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 675 #endif 676 677 /* 678 * Environment Configuration 679 */ 680 681 #if defined(CONFIG_TSEC_ENET) 682 #define CONFIG_HAS_ETH0 683 #define CONFIG_HAS_ETH1 684 #define CONFIG_HAS_ETH2 685 #endif 686 687 #define CONFIG_ROOTPATH "/opt/nfsroot" 688 #define CONFIG_BOOTFILE "uImage" 689 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 690 691 /* default location for tftp and bootm */ 692 #define CONFIG_LOADADDR 1000000 693 694 #define CONFIG_EXTRA_ENV_SETTINGS \ 695 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 696 "netdev=eth0\0" \ 697 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 698 "loadaddr=1000000\0" \ 699 "consoledev=ttyS0\0" \ 700 "ramdiskaddr=2000000\0" \ 701 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 702 "fdtaddr=1e00000\0" \ 703 "fdtfile=p1010rdb.dtb\0" \ 704 "bdev=sda1\0" \ 705 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ 706 "othbootargs=ramdisk_size=600000\0" \ 707 "usbfatboot=setenv bootargs root=/dev/ram rw " \ 708 "console=$consoledev,$baudrate $othbootargs; " \ 709 "usb start;" \ 710 "fatload usb 0:2 $loadaddr $bootfile;" \ 711 "fatload usb 0:2 $fdtaddr $fdtfile;" \ 712 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ 713 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 714 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 715 "console=$consoledev,$baudrate $othbootargs; " \ 716 "usb start;" \ 717 "ext2load usb 0:4 $loadaddr $bootfile;" \ 718 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 719 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 720 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 721 CONFIG_BOOTMODE 722 723 #if defined(CONFIG_TARGET_P1010RDB_PA) 724 #define CONFIG_BOOTMODE \ 725 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 726 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ 727 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ 728 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ 729 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ 730 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" 731 732 #elif defined(CONFIG_TARGET_P1010RDB_PB) 733 #define CONFIG_BOOTMODE \ 734 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 735 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ 736 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ 737 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ 738 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ 739 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ 740 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ 741 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ 742 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ 743 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" 744 #endif 745 746 #define CONFIG_RAMBOOTCOMMAND \ 747 "setenv bootargs root=/dev/ram rw " \ 748 "console=$consoledev,$baudrate $othbootargs; " \ 749 "tftp $ramdiskaddr $ramdiskfile;" \ 750 "tftp $loadaddr $bootfile;" \ 751 "tftp $fdtaddr $fdtfile;" \ 752 "bootm $loadaddr $ramdiskaddr $fdtaddr" 753 754 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 755 756 #include <asm/fsl_secure_boot.h> 757 758 #endif /* __CONFIG_H */ 759