1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2014-2020 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <env.h>
8 #include <log.h>
9 #include <asm/io.h>
10 #include <fsl_ddr_sdram.h>
11 #include <asm/processor.h>
12 #include <fsl_immap.h>
13 #include <fsl_ddr.h>
14 #include <fsl_errata.h>
15 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
16 defined(CONFIG_ARM)
17 #include <asm/arch/clock.h>
18 #endif
19 #include <linux/delay.h>
20
21 #define CTLR_INTLV_MASK 0x20000000
22
23 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) | \
24 defined(CONFIG_SYS_FSL_ERRATUM_A009803)
set_wait_for_bits_clear(void * ptr,u32 value,u32 bits)25 static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
26 {
27 int timeout = 1000;
28
29 ddr_out32(ptr, value);
30
31 while (ddr_in32(ptr) & bits) {
32 udelay(100);
33 timeout--;
34 }
35 if (timeout <= 0)
36 puts("Error: wait for clear timeout.\n");
37 }
38 #endif
39
40 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
41 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
42 #endif
43
44 /*
45 * regs has the to-be-set values for DDR controller registers
46 * ctrl_num is the DDR controller number
47 * step: 0 goes through the initialization in one pass
48 * 1 sets registers and returns before enabling controller
49 * 2 resumes from step 1 and continues to initialize
50 * Dividing the initialization to two steps to deassert DDR reset signal
51 * to comply with JEDEC specs for RDIMMs.
52 */
fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t * regs,unsigned int ctrl_num,int step)53 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
54 unsigned int ctrl_num, int step)
55 {
56 unsigned int i, bus_width;
57 struct ccsr_ddr __iomem *ddr;
58 u32 temp32;
59 u32 total_gb_size_per_controller;
60 int timeout;
61 int mod_bnds = 0;
62
63 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
64 u32 mr6;
65 u32 vref_seq1[3] = {0x80, 0x96, 0x16}; /* for range 1 */
66 u32 vref_seq2[3] = {0xc0, 0xf0, 0x70}; /* for range 2 */
67 u32 *vref_seq = vref_seq1;
68 #endif
69 #ifdef CONFIG_FSL_DDR_BIST
70 u32 mtcr, err_detect, err_sbe;
71 u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config;
72 #endif
73 #ifdef CONFIG_FSL_DDR_BIST
74 char buffer[CONFIG_SYS_CBSIZE];
75 #endif
76 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) || \
77 (defined(CONFIG_SYS_FSL_ERRATUM_A008378) && \
78 defined(CONFIG_SYS_FSL_DDRC_GEN4)) || \
79 defined(CONFIG_SYS_FSL_ERRATUM_A008109)
80 u32 val32;
81 #endif
82 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
83 unsigned int ddr_freq;
84 #endif
85 switch (ctrl_num) {
86 case 0:
87 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
88 break;
89 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
90 case 1:
91 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
92 break;
93 #endif
94 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
95 case 2:
96 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
97 break;
98 #endif
99 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
100 case 3:
101 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
102 break;
103 #endif
104 default:
105 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
106 return;
107 }
108 mod_bnds = regs->cs[0].config & CTLR_INTLV_MASK;
109
110 if (step == 2)
111 goto step2;
112
113 /* Set cdr1 first in case 0.9v VDD is enabled for some SoCs*/
114 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
115
116 if (regs->ddr_eor)
117 ddr_out32(&ddr->eor, regs->ddr_eor);
118
119 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
120 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
121 if (i == 0) {
122 if (mod_bnds) {
123 debug("modified bnds\n");
124 ddr_out32(&ddr->cs0_bnds,
125 (regs->cs[i].bnds & 0xfffefffe) >> 1);
126 ddr_out32(&ddr->cs0_config,
127 (regs->cs[i].config &
128 ~CTLR_INTLV_MASK));
129 } else {
130 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
131 ddr_out32(&ddr->cs0_config, regs->cs[i].config);
132 }
133 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
134
135 } else if (i == 1) {
136 if (mod_bnds) {
137 ddr_out32(&ddr->cs1_bnds,
138 (regs->cs[i].bnds & 0xfffefffe) >> 1);
139 } else {
140 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
141 }
142 ddr_out32(&ddr->cs1_config, regs->cs[i].config);
143 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
144
145 } else if (i == 2) {
146 if (mod_bnds) {
147 ddr_out32(&ddr->cs2_bnds,
148 (regs->cs[i].bnds & 0xfffefffe) >> 1);
149 } else {
150 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
151 }
152 ddr_out32(&ddr->cs2_config, regs->cs[i].config);
153 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
154
155 } else if (i == 3) {
156 if (mod_bnds) {
157 ddr_out32(&ddr->cs3_bnds,
158 (regs->cs[i].bnds & 0xfffefffe) >> 1);
159 } else {
160 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
161 }
162 ddr_out32(&ddr->cs3_config, regs->cs[i].config);
163 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
164 }
165 }
166
167 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
168 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
169 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
170 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
171 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
172 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
173 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6);
174 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7);
175 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8);
176 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9);
177 ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
178 ddr_out32(&ddr->dq_map_0, regs->dq_map_0);
179 ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
180 ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
181 ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
182 ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
183 ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
184 ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
185 ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
186 ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
187 ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
188 ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
189 ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
190 ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
191 ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9);
192 ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10);
193 ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11);
194 ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12);
195 ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13);
196 ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14);
197 ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15);
198 ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16);
199 ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
200 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
201 ddr_out32(&ddr->sdram_interval,
202 regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE);
203 #else
204 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
205 #endif
206 ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
207 ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
208 #ifndef CONFIG_SYS_FSL_DDR_EMU
209 /*
210 * Skip these two registers if running on emulator
211 * because emulator doesn't have skew between bytes.
212 */
213
214 if (regs->ddr_wrlvl_cntl_2)
215 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
216 if (regs->ddr_wrlvl_cntl_3)
217 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
218 #endif
219
220 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
221 ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
222 ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
223 ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3);
224 ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
225 ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
226 ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
227 #ifdef CONFIG_DEEP_SLEEP
228 if (is_warm_boot()) {
229 ddr_out32(&ddr->sdram_cfg_2,
230 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
231 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
232 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
233
234 /* DRAM VRef will not be trained */
235 ddr_out32(&ddr->ddr_cdr2,
236 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
237 } else
238 #endif
239 {
240 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
241 ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
242 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
243 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
244 }
245
246 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
247 /* part 1 of 2 */
248 if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
249 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
250 ddr_out32(&ddr->ddr_sdram_rcw_2,
251 regs->ddr_sdram_rcw_2 & ~0xf0);
252 }
253 ddr_out32(&ddr->err_disable, regs->err_disable |
254 DDR_ERR_DISABLE_APED);
255 }
256 #else
257 ddr_out32(&ddr->err_disable, regs->err_disable);
258 #endif
259 ddr_out32(&ddr->err_int_en, regs->err_int_en);
260 for (i = 0; i < 64; i++) {
261 if (regs->debug[i]) {
262 debug("Write to debug_%d as %08x\n",
263 i+1, regs->debug[i]);
264 ddr_out32(&ddr->debug[i], regs->debug[i]);
265 }
266 }
267
268 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
269 /* Part 1 of 2 */
270 if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
271 /* Disable DRAM VRef training */
272 ddr_out32(&ddr->ddr_cdr2,
273 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
274 /* disable transmit bit deskew */
275 temp32 = ddr_in32(&ddr->debug[28]);
276 temp32 |= DDR_TX_BD_DIS;
277 ddr_out32(&ddr->debug[28], temp32);
278 ddr_out32(&ddr->debug[25], 0x9000);
279 } else if (fsl_ddr_get_version(ctrl_num) == 0x50201) {
280 /* Output enable forced off */
281 ddr_out32(&ddr->debug[37], 1 << 31);
282 /* Enable Vref training */
283 ddr_out32(&ddr->ddr_cdr2,
284 regs->ddr_cdr2 | DDR_CDR2_VREF_TRAIN_EN);
285 } else {
286 debug("Erratum A008511 doesn't apply.\n");
287 }
288 #endif
289
290 #if defined(CONFIG_SYS_FSL_ERRATUM_A009803) || \
291 defined(CONFIG_SYS_FSL_ERRATUM_A008511)
292 /* Disable D_INIT */
293 ddr_out32(&ddr->sdram_cfg_2,
294 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
295 #endif
296
297 #ifdef CONFIG_SYS_FSL_ERRATUM_A009801
298 temp32 = ddr_in32(&ddr->debug[25]);
299 temp32 &= ~DDR_CAS_TO_PRE_SUB_MASK;
300 temp32 |= 9 << DDR_CAS_TO_PRE_SUB_SHIFT;
301 ddr_out32(&ddr->debug[25], temp32);
302 #endif
303
304 #ifdef CONFIG_SYS_FSL_ERRATUM_A010165
305 temp32 = get_ddr_freq(ctrl_num) / 1000000;
306 if ((temp32 > 1900) && (temp32 < 2300)) {
307 temp32 = ddr_in32(&ddr->debug[28]);
308 ddr_out32(&ddr->debug[28], temp32 | 0x000a0000);
309 }
310 #endif
311 /*
312 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
313 * deasserted. Clocks start when any chip select is enabled and clock
314 * control register is set. Because all DDR components are connected to
315 * one reset signal, this needs to be done in two steps. Step 1 is to
316 * get the clocks started. Step 2 resumes after reset signal is
317 * deasserted.
318 */
319 if (step == 1) {
320 udelay(200);
321 return;
322 }
323
324 step2:
325 /* Set, but do not enable the memory */
326 temp32 = regs->ddr_sdram_cfg;
327 temp32 &= ~(SDRAM_CFG_MEM_EN);
328 ddr_out32(&ddr->sdram_cfg, temp32);
329
330 /*
331 * 500 painful micro-seconds must elapse between
332 * the DDR clock setup and the DDR config enable.
333 * DDR2 need 200 us, and DDR3 need 500 us from spec,
334 * we choose the max, that is 500 us for all of case.
335 */
336 udelay(500);
337 mb();
338 isb();
339
340 #ifdef CONFIG_DEEP_SLEEP
341 if (is_warm_boot()) {
342 /* enter self-refresh */
343 temp32 = ddr_in32(&ddr->sdram_cfg_2);
344 temp32 |= SDRAM_CFG2_FRC_SR;
345 ddr_out32(&ddr->sdram_cfg_2, temp32);
346 /* do board specific memory setup */
347 board_mem_sleep_setup();
348
349 temp32 = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
350 } else
351 #endif
352 temp32 = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
353 /* Let the controller go */
354 ddr_out32(&ddr->sdram_cfg, temp32 | SDRAM_CFG_MEM_EN);
355 mb();
356 isb();
357
358 #if defined(CONFIG_SYS_FSL_ERRATUM_A008511) || \
359 defined(CONFIG_SYS_FSL_ERRATUM_A009803)
360 /* Part 2 of 2 */
361 timeout = 40;
362 /* Wait for idle. D_INIT needs to be cleared earlier, or timeout */
363 while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
364 (timeout > 0)) {
365 udelay(1000);
366 timeout--;
367 }
368 if (timeout <= 0) {
369 printf("Controler %d timeout, debug_2 = %x\n",
370 ctrl_num, ddr_in32(&ddr->debug[1]));
371 }
372
373 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
374 /* This erraum only applies to verion 5.2.0 */
375 if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
376 /* The vref setting sequence is different for range 2 */
377 if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
378 vref_seq = vref_seq2;
379
380 /* Set VREF */
381 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
382 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
383 continue;
384
385 mr6 = (regs->ddr_sdram_mode_10 >> 16) |
386 MD_CNTL_MD_EN |
387 MD_CNTL_CS_SEL(i) |
388 MD_CNTL_MD_SEL(6) |
389 0x00200000;
390 temp32 = mr6 | vref_seq[0];
391 set_wait_for_bits_clear(&ddr->sdram_md_cntl,
392 temp32, MD_CNTL_MD_EN);
393 udelay(1);
394 debug("MR6 = 0x%08x\n", temp32);
395 temp32 = mr6 | vref_seq[1];
396 set_wait_for_bits_clear(&ddr->sdram_md_cntl,
397 temp32, MD_CNTL_MD_EN);
398 udelay(1);
399 debug("MR6 = 0x%08x\n", temp32);
400 temp32 = mr6 | vref_seq[2];
401 set_wait_for_bits_clear(&ddr->sdram_md_cntl,
402 temp32, MD_CNTL_MD_EN);
403 udelay(1);
404 debug("MR6 = 0x%08x\n", temp32);
405 }
406 ddr_out32(&ddr->sdram_md_cntl, 0);
407 temp32 = ddr_in32(&ddr->debug[28]);
408 temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */
409 ddr_out32(&ddr->debug[28], temp32);
410 ddr_out32(&ddr->debug[1], 0x400); /* restart deskew */
411 /* wait for idle */
412 timeout = 40;
413 while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
414 (timeout > 0)) {
415 udelay(1000);
416 timeout--;
417 }
418 if (timeout <= 0) {
419 printf("Controler %d timeout, debug_2 = %x\n",
420 ctrl_num, ddr_in32(&ddr->debug[1]));
421 }
422 }
423 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
424
425 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
426 if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
427 /* if it's RDIMM */
428 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
429 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
430 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
431 continue;
432 set_wait_for_bits_clear(&ddr->sdram_md_cntl,
433 MD_CNTL_MD_EN |
434 MD_CNTL_CS_SEL(i) |
435 0x070000ed,
436 MD_CNTL_MD_EN);
437 udelay(1);
438 }
439 }
440
441 ddr_out32(&ddr->err_disable,
442 regs->err_disable & ~DDR_ERR_DISABLE_APED);
443 }
444 #endif
445 /* Restore D_INIT */
446 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
447 #endif
448
449 #if defined(CONFIG_SYS_FSL_ERRATUM_A008378) && defined(CONFIG_SYS_FSL_DDRC_GEN4)
450 /* Erratum applies when accumulated ECC is used, or DBI is enabled */
451 #define IS_ACC_ECC_EN(v) ((v) & 0x4)
452 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
453 if (has_erratum_a008378()) {
454 if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
455 IS_DBI(regs->ddr_sdram_cfg_3)) {
456 val32 = ddr_in32(&ddr->debug[28]);
457 val32 |= (0x9 << 20);
458 ddr_out32(&ddr->debug[28], val32);
459 }
460 debug("Applied errata CONFIG_SYS_FSL_ERRATUM_A008378\n");
461 }
462 #endif
463
464 #if defined(CONFIG_SYS_FSL_ERRATUM_A008109)
465 val32 = ddr_in32(&ddr->sdram_cfg_2) | 0x800; /* DDR_SLOW */
466 ddr_out32(&ddr->sdram_cfg_2, val32);
467
468 val32 = ddr_in32(&ddr->debug[18]) | 0x2;
469 ddr_out32(&ddr->debug[18], val32);
470
471 ddr_out32(&ddr->debug[28], 0x30000000);
472 debug("Applied errta CONFIG_SYS_FSL_ERRATUM_A008109\n");
473 #endif
474
475 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
476 ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
477 val32 = ddr_in32(&ddr->debug[28]);
478 val32 &= 0xff0fff00;
479 if (ddr_freq <= 1333)
480 val32 |= 0x0080006a;
481 else if (ddr_freq <= 1600)
482 val32 |= 0x0070006f;
483 else if (ddr_freq <= 1867)
484 val32 |= 0x00700076;
485 else if (ddr_freq <= 2133)
486 val32 |= 0x0060007b;
487
488 ddr_out32(&ddr->debug[28], val32);
489 debug("Applied errata CONFIG_SYS_FSL_ERRATUM_A009942\n");
490 #endif
491
492 total_gb_size_per_controller = 0;
493 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
494 if (!(regs->cs[i].config & 0x80000000))
495 continue;
496 total_gb_size_per_controller += 1 << (
497 ((regs->cs[i].config >> 14) & 0x3) + 2 +
498 ((regs->cs[i].config >> 8) & 0x7) + 12 +
499 ((regs->cs[i].config >> 4) & 0x3) + 0 +
500 ((regs->cs[i].config >> 0) & 0x7) + 8 +
501 ((regs->ddr_sdram_cfg_3 >> 4) & 0x3) +
502 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
503 26); /* minus 26 (count of 64M) */
504 }
505 /*
506 * total memory / bus width = transactions needed
507 * transactions needed / data rate = seconds
508 * to add plenty of buffer, double the time
509 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
510 * Let's wait for 800ms
511 */
512 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
513 >> SDRAM_CFG_DBW_SHIFT);
514 timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
515 (get_ddr_freq(ctrl_num) >> 20)) << 2;
516 total_gb_size_per_controller >>= 4; /* shift down to gb size */
517 debug("total %d GB\n", total_gb_size_per_controller);
518 debug("Need to wait up to %d * 10ms\n", timeout);
519
520 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
521 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
522 (timeout >= 0)) {
523 udelay(10000); /* throttle polling rate */
524 timeout--;
525 }
526
527 if (timeout <= 0)
528 printf("Waiting for D_INIT timeout. Memory may not work.\n");
529
530 if (mod_bnds) {
531 debug("Reset to original bnds\n");
532 ddr_out32(&ddr->cs0_bnds, regs->cs[0].bnds);
533 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
534 ddr_out32(&ddr->cs1_bnds, regs->cs[1].bnds);
535 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
536 ddr_out32(&ddr->cs2_bnds, regs->cs[2].bnds);
537 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
538 ddr_out32(&ddr->cs3_bnds, regs->cs[3].bnds);
539 #endif
540 #endif
541 #endif
542 ddr_out32(&ddr->cs0_config, regs->cs[0].config);
543 }
544
545 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
546 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
547 #endif
548
549 #ifdef CONFIG_DEEP_SLEEP
550 if (is_warm_boot()) {
551 /* exit self-refresh */
552 temp32 = ddr_in32(&ddr->sdram_cfg_2);
553 temp32 &= ~SDRAM_CFG2_FRC_SR;
554 ddr_out32(&ddr->sdram_cfg_2, temp32);
555 }
556 #endif
557
558 #ifdef CONFIG_FSL_DDR_BIST
559 #define BIST_PATTERN1 0xFFFFFFFF
560 #define BIST_PATTERN2 0x0
561 #define BIST_CR 0x80010000
562 #define BIST_CR_EN 0x80000000
563 #define BIST_CR_STAT 0x00000001
564 /* Perform build-in test on memory. Three-way interleaving is not yet
565 * supported by this code. */
566 if (env_get_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) {
567 puts("Running BIST test. This will take a while...");
568 cs0_config = ddr_in32(&ddr->cs0_config);
569 cs0_bnds = ddr_in32(&ddr->cs0_bnds);
570 cs1_bnds = ddr_in32(&ddr->cs1_bnds);
571 cs2_bnds = ddr_in32(&ddr->cs2_bnds);
572 cs3_bnds = ddr_in32(&ddr->cs3_bnds);
573 if (cs0_config & CTLR_INTLV_MASK) {
574 /* set bnds to non-interleaving */
575 ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1);
576 ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1);
577 ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1);
578 ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1);
579 }
580 ddr_out32(&ddr->mtp1, BIST_PATTERN1);
581 ddr_out32(&ddr->mtp2, BIST_PATTERN1);
582 ddr_out32(&ddr->mtp3, BIST_PATTERN2);
583 ddr_out32(&ddr->mtp4, BIST_PATTERN2);
584 ddr_out32(&ddr->mtp5, BIST_PATTERN1);
585 ddr_out32(&ddr->mtp6, BIST_PATTERN1);
586 ddr_out32(&ddr->mtp7, BIST_PATTERN2);
587 ddr_out32(&ddr->mtp8, BIST_PATTERN2);
588 ddr_out32(&ddr->mtp9, BIST_PATTERN1);
589 ddr_out32(&ddr->mtp10, BIST_PATTERN2);
590 mtcr = BIST_CR;
591 ddr_out32(&ddr->mtcr, mtcr);
592 timeout = 100;
593 while (timeout > 0 && (mtcr & BIST_CR_EN)) {
594 mdelay(1000);
595 timeout--;
596 mtcr = ddr_in32(&ddr->mtcr);
597 }
598 if (timeout <= 0)
599 puts("Timeout\n");
600 else
601 puts("Done\n");
602 err_detect = ddr_in32(&ddr->err_detect);
603 err_sbe = ddr_in32(&ddr->err_sbe);
604 if (mtcr & BIST_CR_STAT) {
605 printf("BIST test failed on controller %d.\n",
606 ctrl_num);
607 }
608 if (err_detect || (err_sbe & 0xffff)) {
609 printf("ECC error detected on controller %d.\n",
610 ctrl_num);
611 }
612
613 if (cs0_config & CTLR_INTLV_MASK) {
614 /* restore bnds registers */
615 ddr_out32(&ddr->cs0_bnds, cs0_bnds);
616 ddr_out32(&ddr->cs1_bnds, cs1_bnds);
617 ddr_out32(&ddr->cs2_bnds, cs2_bnds);
618 ddr_out32(&ddr->cs3_bnds, cs3_bnds);
619 }
620 }
621 #endif
622 }
623