1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <cpu_func.h>
10 #include <fdtdec.h>
11 #include <mmc.h>
12 #include <dm.h>
13 #include <asm/global_data.h>
14 #include <dm/device_compat.h>
15 #include <dm/pinctrl.h>
16 #include <linux/compat.h>
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/io.h>
20 #include <linux/sizes.h>
21 #include <power/regulator.h>
22 #include <asm/unaligned.h>
23
24 #include "tmio-common.h"
25
26 DECLARE_GLOBAL_DATA_PTR;
27
tmio_sd_readq(struct tmio_sd_priv * priv,unsigned int reg)28 static u64 tmio_sd_readq(struct tmio_sd_priv *priv, unsigned int reg)
29 {
30 return readq(priv->regbase + (reg << 1));
31 }
32
tmio_sd_writeq(struct tmio_sd_priv * priv,u64 val,unsigned int reg)33 static void tmio_sd_writeq(struct tmio_sd_priv *priv,
34 u64 val, unsigned int reg)
35 {
36 writeq(val, priv->regbase + (reg << 1));
37 }
38
tmio_sd_readw(struct tmio_sd_priv * priv,unsigned int reg)39 static u16 tmio_sd_readw(struct tmio_sd_priv *priv, unsigned int reg)
40 {
41 return readw(priv->regbase + (reg >> 1));
42 }
43
tmio_sd_writew(struct tmio_sd_priv * priv,u16 val,unsigned int reg)44 static void tmio_sd_writew(struct tmio_sd_priv *priv,
45 u16 val, unsigned int reg)
46 {
47 writew(val, priv->regbase + (reg >> 1));
48 }
49
tmio_sd_readl(struct tmio_sd_priv * priv,unsigned int reg)50 u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg)
51 {
52 u32 val;
53
54 if (priv->caps & TMIO_SD_CAP_64BIT)
55 return readl(priv->regbase + (reg << 1));
56 else if (priv->caps & TMIO_SD_CAP_16BIT) {
57 val = readw(priv->regbase + (reg >> 1)) & 0xffff;
58 if ((reg == TMIO_SD_RSP10) || (reg == TMIO_SD_RSP32) ||
59 (reg == TMIO_SD_RSP54) || (reg == TMIO_SD_RSP76)) {
60 val |= readw(priv->regbase + (reg >> 1) + 2) << 16;
61 }
62 return val;
63 } else
64 return readl(priv->regbase + reg);
65 }
66
tmio_sd_writel(struct tmio_sd_priv * priv,u32 val,unsigned int reg)67 void tmio_sd_writel(struct tmio_sd_priv *priv,
68 u32 val, unsigned int reg)
69 {
70 if (priv->caps & TMIO_SD_CAP_64BIT)
71 writel(val, priv->regbase + (reg << 1));
72 else if (priv->caps & TMIO_SD_CAP_16BIT) {
73 writew(val & 0xffff, priv->regbase + (reg >> 1));
74 if (reg == TMIO_SD_INFO1 || reg == TMIO_SD_INFO1_MASK ||
75 reg == TMIO_SD_INFO2 || reg == TMIO_SD_INFO2_MASK ||
76 reg == TMIO_SD_ARG)
77 writew(val >> 16, priv->regbase + (reg >> 1) + 2);
78 } else
79 writel(val, priv->regbase + reg);
80 }
81
tmio_sd_check_error(struct udevice * dev,struct mmc_cmd * cmd)82 static int tmio_sd_check_error(struct udevice *dev, struct mmc_cmd *cmd)
83 {
84 struct tmio_sd_priv *priv = dev_get_priv(dev);
85 u32 info2 = tmio_sd_readl(priv, TMIO_SD_INFO2);
86
87 if (info2 & TMIO_SD_INFO2_ERR_RTO) {
88 /*
89 * TIMEOUT must be returned for unsupported command. Do not
90 * display error log since this might be a part of sequence to
91 * distinguish between SD and MMC.
92 */
93 return -ETIMEDOUT;
94 }
95
96 if (info2 & TMIO_SD_INFO2_ERR_TO) {
97 dev_err(dev, "timeout error\n");
98 return -ETIMEDOUT;
99 }
100
101 if (info2 & (TMIO_SD_INFO2_ERR_END | TMIO_SD_INFO2_ERR_CRC |
102 TMIO_SD_INFO2_ERR_IDX)) {
103 if ((cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK) &&
104 (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200))
105 dev_err(dev, "communication out of sync\n");
106 return -EILSEQ;
107 }
108
109 if (info2 & (TMIO_SD_INFO2_ERR_ILA | TMIO_SD_INFO2_ERR_ILR |
110 TMIO_SD_INFO2_ERR_ILW)) {
111 dev_err(dev, "illegal access\n");
112 return -EIO;
113 }
114
115 return 0;
116 }
117
tmio_sd_wait_for_irq(struct udevice * dev,struct mmc_cmd * cmd,unsigned int reg,u32 flag)118 static int tmio_sd_wait_for_irq(struct udevice *dev, struct mmc_cmd *cmd,
119 unsigned int reg, u32 flag)
120 {
121 struct tmio_sd_priv *priv = dev_get_priv(dev);
122 long wait = 1000000;
123 int ret;
124
125 while (!(tmio_sd_readl(priv, reg) & flag)) {
126 if (wait-- < 0) {
127 dev_err(dev, "timeout\n");
128 return -ETIMEDOUT;
129 }
130
131 ret = tmio_sd_check_error(dev, cmd);
132 if (ret)
133 return ret;
134
135 udelay(1);
136 }
137
138 return 0;
139 }
140
141 #define tmio_pio_read_fifo(__width, __suffix) \
142 static void tmio_pio_read_fifo_##__width(struct tmio_sd_priv *priv, \
143 char *pbuf, uint blksz) \
144 { \
145 u##__width *buf = (u##__width *)pbuf; \
146 int i; \
147 \
148 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
149 for (i = 0; i < blksz / ((__width) / 8); i++) { \
150 *buf++ = tmio_sd_read##__suffix(priv, \
151 TMIO_SD_BUF); \
152 } \
153 } else { \
154 for (i = 0; i < blksz / ((__width) / 8); i++) { \
155 u##__width data; \
156 data = tmio_sd_read##__suffix(priv, \
157 TMIO_SD_BUF); \
158 put_unaligned(data, buf++); \
159 } \
160 } \
161 }
162
163 tmio_pio_read_fifo(64, q)
164 tmio_pio_read_fifo(32, l)
165 tmio_pio_read_fifo(16, w)
166
tmio_sd_pio_read_one_block(struct udevice * dev,struct mmc_cmd * cmd,char * pbuf,uint blocksize)167 static int tmio_sd_pio_read_one_block(struct udevice *dev, struct mmc_cmd *cmd,
168 char *pbuf, uint blocksize)
169 {
170 struct tmio_sd_priv *priv = dev_get_priv(dev);
171 int ret;
172
173 /* wait until the buffer is filled with data */
174 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
175 TMIO_SD_INFO2_BRE);
176 if (ret)
177 return ret;
178
179 /*
180 * Clear the status flag _before_ read the buffer out because
181 * TMIO_SD_INFO2_BRE is edge-triggered, not level-triggered.
182 */
183 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
184
185 if (priv->caps & TMIO_SD_CAP_64BIT)
186 tmio_pio_read_fifo_64(priv, pbuf, blocksize);
187 else if (priv->caps & TMIO_SD_CAP_16BIT)
188 tmio_pio_read_fifo_16(priv, pbuf, blocksize);
189 else
190 tmio_pio_read_fifo_32(priv, pbuf, blocksize);
191
192 return 0;
193 }
194
195 #define tmio_pio_write_fifo(__width, __suffix) \
196 static void tmio_pio_write_fifo_##__width(struct tmio_sd_priv *priv, \
197 const char *pbuf, uint blksz)\
198 { \
199 const u##__width *buf = (const u##__width *)pbuf; \
200 int i; \
201 \
202 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
203 for (i = 0; i < blksz / ((__width) / 8); i++) { \
204 tmio_sd_write##__suffix(priv, *buf++, \
205 TMIO_SD_BUF); \
206 } \
207 } else { \
208 for (i = 0; i < blksz / ((__width) / 8); i++) { \
209 u##__width data = get_unaligned(buf++); \
210 tmio_sd_write##__suffix(priv, data, \
211 TMIO_SD_BUF); \
212 } \
213 } \
214 }
215
216 tmio_pio_write_fifo(64, q)
217 tmio_pio_write_fifo(32, l)
218 tmio_pio_write_fifo(16, w)
219
tmio_sd_pio_write_one_block(struct udevice * dev,struct mmc_cmd * cmd,const char * pbuf,uint blocksize)220 static int tmio_sd_pio_write_one_block(struct udevice *dev, struct mmc_cmd *cmd,
221 const char *pbuf, uint blocksize)
222 {
223 struct tmio_sd_priv *priv = dev_get_priv(dev);
224 int ret;
225
226 /* wait until the buffer becomes empty */
227 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
228 TMIO_SD_INFO2_BWE);
229 if (ret)
230 return ret;
231
232 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
233
234 if (priv->caps & TMIO_SD_CAP_64BIT)
235 tmio_pio_write_fifo_64(priv, pbuf, blocksize);
236 else if (priv->caps & TMIO_SD_CAP_16BIT)
237 tmio_pio_write_fifo_16(priv, pbuf, blocksize);
238 else
239 tmio_pio_write_fifo_32(priv, pbuf, blocksize);
240
241 return 0;
242 }
243
tmio_sd_pio_xfer(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)244 static int tmio_sd_pio_xfer(struct udevice *dev, struct mmc_cmd *cmd,
245 struct mmc_data *data)
246 {
247 const char *src = data->src;
248 char *dest = data->dest;
249 int i, ret;
250
251 for (i = 0; i < data->blocks; i++) {
252 if (data->flags & MMC_DATA_READ)
253 ret = tmio_sd_pio_read_one_block(dev, cmd, dest,
254 data->blocksize);
255 else
256 ret = tmio_sd_pio_write_one_block(dev, cmd, src,
257 data->blocksize);
258 if (ret)
259 return ret;
260
261 if (data->flags & MMC_DATA_READ)
262 dest += data->blocksize;
263 else
264 src += data->blocksize;
265 }
266
267 return 0;
268 }
269
tmio_sd_dma_start(struct tmio_sd_priv * priv,dma_addr_t dma_addr)270 static void tmio_sd_dma_start(struct tmio_sd_priv *priv,
271 dma_addr_t dma_addr)
272 {
273 u32 tmp;
274
275 tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO1);
276 tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO2);
277
278 /* enable DMA */
279 tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
280 tmp |= TMIO_SD_EXTMODE_DMA_EN;
281 tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
282
283 tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_L);
284
285 /* suppress the warning "right shift count >= width of type" */
286 dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
287
288 tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_H);
289
290 tmio_sd_writel(priv, TMIO_SD_DMA_CTL_START, TMIO_SD_DMA_CTL);
291 }
292
tmio_sd_dma_wait_for_irq(struct udevice * dev,u32 flag,unsigned int blocks)293 static int tmio_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
294 unsigned int blocks)
295 {
296 struct tmio_sd_priv *priv = dev_get_priv(dev);
297 long wait = 1000000 + 10 * blocks;
298
299 while (!(tmio_sd_readl(priv, TMIO_SD_DMA_INFO1) & flag)) {
300 if (wait-- < 0) {
301 dev_err(dev, "timeout during DMA\n");
302 return -ETIMEDOUT;
303 }
304
305 udelay(10);
306 }
307
308 if (tmio_sd_readl(priv, TMIO_SD_DMA_INFO2)) {
309 dev_err(dev, "error during DMA\n");
310 return -EIO;
311 }
312
313 return 0;
314 }
315
tmio_sd_dma_xfer(struct udevice * dev,struct mmc_data * data)316 static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
317 {
318 struct tmio_sd_priv *priv = dev_get_priv(dev);
319 size_t len = data->blocks * data->blocksize;
320 void *buf;
321 enum dma_data_direction dir;
322 dma_addr_t dma_addr;
323 u32 poll_flag, tmp;
324 int ret;
325
326 tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
327
328 tmp |= priv->idma_bus_width;
329
330 if (data->flags & MMC_DATA_READ) {
331 buf = data->dest;
332 dir = DMA_FROM_DEVICE;
333 /*
334 * The DMA READ completion flag position differs on Socionext
335 * and Renesas SoCs. It is bit 20 on Socionext SoCs and using
336 * bit 17 is a hardware bug and forbidden. It is either bit 17
337 * or bit 20 on Renesas SoCs, depending on SoC.
338 */
339 poll_flag = priv->read_poll_flag;
340 tmp |= TMIO_SD_DMA_MODE_DIR_RD;
341 } else {
342 buf = (void *)data->src;
343 dir = DMA_TO_DEVICE;
344 poll_flag = TMIO_SD_DMA_INFO1_END_WR;
345 tmp &= ~TMIO_SD_DMA_MODE_DIR_RD;
346 }
347
348 tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
349
350 dma_addr = dma_map_single(buf, len, dir);
351
352 tmio_sd_dma_start(priv, dma_addr);
353
354 ret = tmio_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
355
356 if (poll_flag == TMIO_SD_DMA_INFO1_END_RD)
357 udelay(1);
358
359 dma_unmap_single(dma_addr, len, dir);
360
361 return ret;
362 }
363
364 /* check if the address is DMA'able */
tmio_sd_addr_is_dmaable(struct mmc_data * data)365 static bool tmio_sd_addr_is_dmaable(struct mmc_data *data)
366 {
367 uintptr_t addr = (uintptr_t)data->src;
368
369 if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN))
370 return false;
371
372 #if defined(CONFIG_RCAR_GEN3)
373 if (!(data->flags & MMC_DATA_READ) && !IS_ALIGNED(addr, 128))
374 return false;
375 /* Gen3 DMA has 32bit limit */
376 if (addr >> 32)
377 return false;
378 #endif
379
380 #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
381 defined(CONFIG_SPL_BUILD)
382 /*
383 * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
384 * of L2, which is unreachable from the DMA engine.
385 */
386 if (addr < CONFIG_SPL_STACK)
387 return false;
388 #endif
389
390 return true;
391 }
392
tmio_sd_send_cmd(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)393 int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
394 struct mmc_data *data)
395 {
396 struct tmio_sd_priv *priv = dev_get_priv(dev);
397 int ret;
398 u32 tmp;
399
400 if (tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_CBSY) {
401 dev_err(dev, "command busy\n");
402 return -EBUSY;
403 }
404
405 /* clear all status flags */
406 tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
407 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
408
409 /* disable DMA once */
410 tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
411 tmp &= ~TMIO_SD_EXTMODE_DMA_EN;
412 tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
413
414 tmio_sd_writel(priv, cmd->cmdarg, TMIO_SD_ARG);
415
416 tmp = cmd->cmdidx;
417
418 if (data) {
419 tmio_sd_writel(priv, data->blocksize, TMIO_SD_SIZE);
420 tmio_sd_writel(priv, data->blocks, TMIO_SD_SECCNT);
421
422 /* Do not send CMD12 automatically */
423 tmp |= TMIO_SD_CMD_NOSTOP | TMIO_SD_CMD_DATA;
424
425 if (data->blocks > 1)
426 tmp |= TMIO_SD_CMD_MULTI;
427
428 if (data->flags & MMC_DATA_READ)
429 tmp |= TMIO_SD_CMD_RD;
430 }
431
432 /*
433 * Do not use the response type auto-detection on this hardware.
434 * CMD8, for example, has different response types on SD and eMMC,
435 * while this controller always assumes the response type for SD.
436 * Set the response type manually.
437 */
438 switch (cmd->resp_type) {
439 case MMC_RSP_NONE:
440 tmp |= TMIO_SD_CMD_RSP_NONE;
441 break;
442 case MMC_RSP_R1:
443 tmp |= TMIO_SD_CMD_RSP_R1;
444 break;
445 case MMC_RSP_R1b:
446 tmp |= TMIO_SD_CMD_RSP_R1B;
447 break;
448 case MMC_RSP_R2:
449 tmp |= TMIO_SD_CMD_RSP_R2;
450 break;
451 case MMC_RSP_R3:
452 tmp |= TMIO_SD_CMD_RSP_R3;
453 break;
454 default:
455 dev_err(dev, "unknown response type\n");
456 return -EINVAL;
457 }
458
459 dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
460 cmd->cmdidx, tmp, cmd->cmdarg);
461 tmio_sd_writel(priv, tmp, TMIO_SD_CMD);
462
463 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
464 TMIO_SD_INFO1_RSP);
465 if (ret)
466 return ret;
467
468 if (cmd->resp_type & MMC_RSP_136) {
469 u32 rsp_127_104 = tmio_sd_readl(priv, TMIO_SD_RSP76);
470 u32 rsp_103_72 = tmio_sd_readl(priv, TMIO_SD_RSP54);
471 u32 rsp_71_40 = tmio_sd_readl(priv, TMIO_SD_RSP32);
472 u32 rsp_39_8 = tmio_sd_readl(priv, TMIO_SD_RSP10);
473
474 cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
475 ((rsp_103_72 & 0xff000000) >> 24);
476 cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) |
477 ((rsp_71_40 & 0xff000000) >> 24);
478 cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) |
479 ((rsp_39_8 & 0xff000000) >> 24);
480 cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
481 } else {
482 /* bit 39-8 */
483 cmd->response[0] = tmio_sd_readl(priv, TMIO_SD_RSP10);
484 }
485
486 if (data) {
487 /* use DMA if the HW supports it and the buffer is aligned */
488 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL &&
489 tmio_sd_addr_is_dmaable(data))
490 ret = tmio_sd_dma_xfer(dev, data);
491 else
492 ret = tmio_sd_pio_xfer(dev, cmd, data);
493 if (ret)
494 return ret;
495
496 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
497 TMIO_SD_INFO1_CMP);
498 if (ret)
499 return ret;
500 }
501
502 return tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
503 TMIO_SD_INFO2_SCLKDIVEN);
504 }
505
tmio_sd_set_bus_width(struct tmio_sd_priv * priv,struct mmc * mmc)506 static int tmio_sd_set_bus_width(struct tmio_sd_priv *priv,
507 struct mmc *mmc)
508 {
509 u32 val, tmp;
510
511 switch (mmc->bus_width) {
512 case 0:
513 case 1:
514 val = TMIO_SD_OPTION_WIDTH_1;
515 break;
516 case 4:
517 val = TMIO_SD_OPTION_WIDTH_4;
518 break;
519 case 8:
520 val = TMIO_SD_OPTION_WIDTH_8;
521 break;
522 default:
523 return -EINVAL;
524 }
525
526 tmp = tmio_sd_readl(priv, TMIO_SD_OPTION);
527 tmp &= ~TMIO_SD_OPTION_WIDTH_MASK;
528 tmp |= val;
529 tmio_sd_writel(priv, tmp, TMIO_SD_OPTION);
530
531 return 0;
532 }
533
tmio_sd_set_ddr_mode(struct tmio_sd_priv * priv,struct mmc * mmc)534 static void tmio_sd_set_ddr_mode(struct tmio_sd_priv *priv,
535 struct mmc *mmc)
536 {
537 u32 tmp;
538
539 tmp = tmio_sd_readl(priv, TMIO_SD_IF_MODE);
540 if (mmc->ddr_mode)
541 tmp |= TMIO_SD_IF_MODE_DDR;
542 else
543 tmp &= ~TMIO_SD_IF_MODE_DDR;
544 tmio_sd_writel(priv, tmp, TMIO_SD_IF_MODE);
545 }
546
tmio_sd_clk_get_rate(struct tmio_sd_priv * priv)547 static ulong tmio_sd_clk_get_rate(struct tmio_sd_priv *priv)
548 {
549 return priv->clk_get_rate(priv);
550 }
551
tmio_sd_set_clk_rate(struct tmio_sd_priv * priv,struct mmc * mmc)552 static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, struct mmc *mmc)
553 {
554 unsigned int divisor;
555 u32 tmp, val = 0;
556 ulong mclk;
557
558 if (mmc->clock) {
559 mclk = tmio_sd_clk_get_rate(priv);
560
561 divisor = DIV_ROUND_UP(mclk, mmc->clock);
562
563 /* Do not set divider to 0xff in DDR mode */
564 if (mmc->ddr_mode && (divisor == 1))
565 divisor = 2;
566
567 if (divisor <= 1)
568 val = (priv->caps & TMIO_SD_CAP_RCAR) ?
569 TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1;
570 else if (divisor <= 2)
571 val = TMIO_SD_CLKCTL_DIV2;
572 else if (divisor <= 4)
573 val = TMIO_SD_CLKCTL_DIV4;
574 else if (divisor <= 8)
575 val = TMIO_SD_CLKCTL_DIV8;
576 else if (divisor <= 16)
577 val = TMIO_SD_CLKCTL_DIV16;
578 else if (divisor <= 32)
579 val = TMIO_SD_CLKCTL_DIV32;
580 else if (divisor <= 64)
581 val = TMIO_SD_CLKCTL_DIV64;
582 else if (divisor <= 128)
583 val = TMIO_SD_CLKCTL_DIV128;
584 else if (divisor <= 256)
585 val = TMIO_SD_CLKCTL_DIV256;
586 else if (divisor <= 512 || !(priv->caps & TMIO_SD_CAP_DIV1024))
587 val = TMIO_SD_CLKCTL_DIV512;
588 else
589 val = TMIO_SD_CLKCTL_DIV1024;
590 }
591
592 tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
593 if (mmc->clock &&
594 !((tmp & TMIO_SD_CLKCTL_SCLKEN) &&
595 ((tmp & TMIO_SD_CLKCTL_DIV_MASK) == val))) {
596 /*
597 * Stop the clock before changing its rate
598 * to avoid a glitch signal
599 */
600 tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
601 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
602
603 /* Change the clock rate. */
604 tmp &= ~TMIO_SD_CLKCTL_DIV_MASK;
605 tmp |= val;
606 }
607
608 /* Enable or Disable the clock */
609 if (mmc->clk_disable) {
610 tmp |= TMIO_SD_CLKCTL_OFFEN;
611 tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
612 } else {
613 tmp &= ~TMIO_SD_CLKCTL_OFFEN;
614 tmp |= TMIO_SD_CLKCTL_SCLKEN;
615 }
616
617 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
618
619 udelay(1000);
620 }
621
tmio_sd_set_pins(struct udevice * dev)622 static void tmio_sd_set_pins(struct udevice *dev)
623 {
624 __maybe_unused struct mmc *mmc = mmc_get_mmc_dev(dev);
625
626 #ifdef CONFIG_DM_REGULATOR
627 struct tmio_sd_priv *priv = dev_get_priv(dev);
628
629 if (priv->vqmmc_dev) {
630 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
631 regulator_set_value(priv->vqmmc_dev, 1800000);
632 else
633 regulator_set_value(priv->vqmmc_dev, 3300000);
634 regulator_set_enable(priv->vqmmc_dev, true);
635 }
636 #endif
637
638 #ifdef CONFIG_PINCTRL
639 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
640 pinctrl_select_state(dev, "state_uhs");
641 else
642 pinctrl_select_state(dev, "default");
643 #endif
644 }
645
tmio_sd_set_ios(struct udevice * dev)646 int tmio_sd_set_ios(struct udevice *dev)
647 {
648 struct tmio_sd_priv *priv = dev_get_priv(dev);
649 struct mmc *mmc = mmc_get_mmc_dev(dev);
650 int ret;
651
652 dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
653 mmc->clock, mmc->ddr_mode, mmc->bus_width);
654
655 tmio_sd_set_clk_rate(priv, mmc);
656 ret = tmio_sd_set_bus_width(priv, mmc);
657 if (ret)
658 return ret;
659 tmio_sd_set_ddr_mode(priv, mmc);
660 tmio_sd_set_pins(dev);
661
662 return 0;
663 }
664
tmio_sd_get_cd(struct udevice * dev)665 int tmio_sd_get_cd(struct udevice *dev)
666 {
667 struct tmio_sd_priv *priv = dev_get_priv(dev);
668
669 if (priv->caps & TMIO_SD_CAP_NONREMOVABLE)
670 return 1;
671
672 return !!(tmio_sd_readl(priv, TMIO_SD_INFO1) &
673 TMIO_SD_INFO1_CD);
674 }
675
tmio_sd_host_init(struct tmio_sd_priv * priv)676 static void tmio_sd_host_init(struct tmio_sd_priv *priv)
677 {
678 u32 tmp;
679
680 /* soft reset of the host */
681 tmp = tmio_sd_readl(priv, TMIO_SD_SOFT_RST);
682 tmp &= ~TMIO_SD_SOFT_RST_RSTX;
683 tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
684 tmp |= TMIO_SD_SOFT_RST_RSTX;
685 tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
686
687 /* FIXME: implement eMMC hw_reset */
688
689 tmio_sd_writel(priv, TMIO_SD_STOP_SEC, TMIO_SD_STOP);
690
691 /*
692 * Connected to 32bit AXI.
693 * This register dropped backward compatibility at version 0x10.
694 * Write an appropriate value depending on the IP version.
695 */
696 if (priv->version >= 0x10) {
697 if (priv->caps & TMIO_SD_CAP_64BIT)
698 tmio_sd_writel(priv, 0x000, TMIO_SD_HOST_MODE);
699 else
700 tmio_sd_writel(priv, 0x101, TMIO_SD_HOST_MODE);
701 } else {
702 tmio_sd_writel(priv, 0x0, TMIO_SD_HOST_MODE);
703 }
704
705 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL) {
706 tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
707 tmp |= TMIO_SD_DMA_MODE_ADDR_INC;
708 tmp |= priv->idma_bus_width;
709 tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
710 }
711 }
712
tmio_sd_bind(struct udevice * dev)713 int tmio_sd_bind(struct udevice *dev)
714 {
715 struct tmio_sd_plat *plat = dev_get_plat(dev);
716
717 return mmc_bind(dev, &plat->mmc, &plat->cfg);
718 }
719
tmio_sd_probe(struct udevice * dev,u32 quirks)720 int tmio_sd_probe(struct udevice *dev, u32 quirks)
721 {
722 struct tmio_sd_plat *plat = dev_get_plat(dev);
723 struct tmio_sd_priv *priv = dev_get_priv(dev);
724 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
725 fdt_addr_t base;
726 ulong mclk;
727 int ret;
728
729 base = dev_read_addr(dev);
730 if (base == FDT_ADDR_T_NONE)
731 return -EINVAL;
732
733 priv->regbase = devm_ioremap(dev, base, SZ_2K);
734 if (!priv->regbase)
735 return -ENOMEM;
736
737 #ifdef CONFIG_DM_REGULATOR
738 device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev);
739 if (priv->vqmmc_dev)
740 regulator_set_value(priv->vqmmc_dev, 3300000);
741 #endif
742
743 ret = mmc_of_parse(dev, &plat->cfg);
744 if (ret < 0) {
745 dev_err(dev, "failed to parse host caps\n");
746 return ret;
747 }
748
749 plat->cfg.name = dev->name;
750 plat->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
751
752 if (quirks)
753 priv->caps = quirks;
754
755 priv->version = tmio_sd_readl(priv, TMIO_SD_VERSION) &
756 TMIO_SD_VERSION_IP;
757 dev_dbg(dev, "version %x\n", priv->version);
758 if (priv->version >= 0x10) {
759 priv->caps |= TMIO_SD_CAP_DMA_INTERNAL;
760 priv->caps |= TMIO_SD_CAP_DIV1024;
761 }
762
763 if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
764 NULL))
765 priv->caps |= TMIO_SD_CAP_NONREMOVABLE;
766
767 tmio_sd_host_init(priv);
768
769 mclk = tmio_sd_clk_get_rate(priv);
770
771 plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
772 plat->cfg.f_min = mclk /
773 (priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512);
774 plat->cfg.f_max = mclk;
775 if (quirks & TMIO_SD_CAP_16BIT)
776 plat->cfg.b_max = U16_MAX; /* max value of TMIO_SD_SECCNT */
777 else
778 plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */
779
780 upriv->mmc = &plat->mmc;
781
782 return 0;
783 }
784