1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  *  Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
4  */
5 
6 #ifndef _RESET_MANAGER_SOC64_H_
7 #define _RESET_MANAGER_SOC64_H_
8 
9 void reset_deassert_peripherals_handoff(void);
10 int cpu_has_been_warmreset(void);
11 void print_reset_info(void);
12 void socfpga_bridges_reset(int enable);
13 
14 #define RSTMGR_SOC64_STATUS	0x00
15 #define RSTMGR_SOC64_MPUMODRST	0x20
16 #define RSTMGR_SOC64_PER0MODRST	0x24
17 #define RSTMGR_SOC64_PER1MODRST	0x28
18 #define RSTMGR_SOC64_BRGMODRST	0x2c
19 
20 #define RSTMGR_MPUMODRST_CORE0		0
21 #define RSTMGR_PER0MODRST_OCP_MASK	0x0020bf00
22 #define RSTMGR_BRGMODRST_DDRSCH_MASK	0X00000040
23 #define RSTMGR_BRGMODRST_FPGA2SOC_MASK	0x00000004
24 
25 /* SDM, Watchdogs and MPU warm reset mask */
26 #define RSTMGR_STAT_SDMWARMRST		BIT(1)
27 #define RSTMGR_STAT_MPU0RST_BITPOS	8
28 #define RSTMGR_STAT_L4WD0RST_BITPOS	16
29 #define RSTMGR_L4WD_MPU_WARMRESET_MASK	(RSTMGR_STAT_SDMWARMRST | \
30 		GENMASK(RSTMGR_STAT_MPU0RST_BITPOS + 3, \
31 			RSTMGR_STAT_MPU0RST_BITPOS) | \
32 		GENMASK(RSTMGR_STAT_L4WD0RST_BITPOS + 3, \
33 			RSTMGR_STAT_L4WD0RST_BITPOS))
34 
35 /*
36  * SocFPGA Stratix10 reset IDs, bank mapping is as follows:
37  * 0 ... mpumodrst
38  * 1 ... per0modrst
39  * 2 ... per1modrst
40  * 3 ... brgmodrst
41  */
42 #define RSTMGR_L4WD0		RSTMGR_DEFINE(2, 0)
43 #define RSTMGR_OSC1TIMER0	RSTMGR_DEFINE(2, 4)
44 #define RSTMGR_UART0		RSTMGR_DEFINE(2, 16)
45 
46 #endif /* _RESET_MANAGER_SOC64_H_ */
47