1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2018 MediaTek Inc. 4 * 5 * Author: Weijie Gao <weijie.gao@mediatek.com> 6 * Author: Mark Lee <mark-mc.lee@mediatek.com> 7 */ 8 9 #ifndef _MTK_ETH_H_ 10 #define _MTK_ETH_H_ 11 12 /* Frame Engine Register Bases */ 13 #include <linux/bitops.h> 14 #define PDMA_BASE 0x0800 15 #define GDMA1_BASE 0x0500 16 #define GDMA2_BASE 0x1500 17 #define GMAC_BASE 0x10000 18 19 /* Ethernet subsystem registers */ 20 21 #define ETHSYS_SYSCFG0_REG 0x14 22 #define SYSCFG0_GE_MODE_S(n) (12 + ((n) * 2)) 23 #define SYSCFG0_GE_MODE_M 0x3 24 #define SYSCFG0_SGMII_SEL_M (0x3 << 8) 25 #define SYSCFG0_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8)) 26 27 #define ETHSYS_CLKCFG0_REG 0x2c 28 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 29 30 /* SYSCFG0_GE_MODE: GE Modes */ 31 #define GE_MODE_RGMII 0 32 #define GE_MODE_MII 1 33 #define GE_MODE_MII_PHY 2 34 #define GE_MODE_RMII 3 35 36 /* SGMII subsystem config registers */ 37 #define SGMSYS_PCS_CONTROL_1 0x0 38 #define SGMII_LINK_STATUS BIT(18) 39 #define SGMII_AN_ENABLE BIT(12) 40 #define SGMII_AN_RESTART BIT(9) 41 42 #define SGMSYS_SGMII_MODE 0x20 43 #define SGMII_FORCE_MODE 0x31120019 44 45 #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 46 #define SGMII_PHYA_PWD BIT(4) 47 48 #define SGMSYS_GEN2_SPEED 0x2028 49 #define SGMSYS_GEN2_SPEED_V2 0x128 50 #define SGMSYS_SPEED_2500 BIT(2) 51 52 /* Frame Engine Registers */ 53 54 /* PDMA */ 55 #define TX_BASE_PTR_REG(n) (0x000 + (n) * 0x10) 56 #define TX_MAX_CNT_REG(n) (0x004 + (n) * 0x10) 57 #define TX_CTX_IDX_REG(n) (0x008 + (n) * 0x10) 58 #define TX_DTX_IDX_REG(n) (0x00c + (n) * 0x10) 59 60 #define RX_BASE_PTR_REG(n) (0x100 + (n) * 0x10) 61 #define RX_MAX_CNT_REG(n) (0x104 + (n) * 0x10) 62 #define RX_CRX_IDX_REG(n) (0x108 + (n) * 0x10) 63 #define RX_DRX_IDX_REG(n) (0x10c + (n) * 0x10) 64 65 #define PDMA_GLO_CFG_REG 0x204 66 #define TX_WB_DDONE BIT(6) 67 #define RX_DMA_BUSY BIT(3) 68 #define RX_DMA_EN BIT(2) 69 #define TX_DMA_BUSY BIT(1) 70 #define TX_DMA_EN BIT(0) 71 72 #define PDMA_RST_IDX_REG 0x208 73 #define RST_DRX_IDX0 BIT(16) 74 #define RST_DTX_IDX0 BIT(0) 75 76 /* GDMA */ 77 #define GDMA_IG_CTRL_REG 0x000 78 #define GDM_ICS_EN BIT(22) 79 #define GDM_TCS_EN BIT(21) 80 #define GDM_UCS_EN BIT(20) 81 #define STRP_CRC BIT(16) 82 #define MYMAC_DP_S 12 83 #define MYMAC_DP_M 0xf000 84 #define BC_DP_S 8 85 #define BC_DP_M 0xf00 86 #define MC_DP_S 4 87 #define MC_DP_M 0xf0 88 #define UN_DP_S 0 89 #define UN_DP_M 0x0f 90 91 #define GDMA_MAC_LSB_REG 0x008 92 93 #define GDMA_MAC_MSB_REG 0x00c 94 95 /* MYMAC_DP/BC_DP/MC_DP/UN_DP: Destination ports */ 96 #define DP_PDMA 0 97 #define DP_GDMA1 1 98 #define DP_GDMA2 2 99 #define DP_PPE 4 100 #define DP_QDMA 5 101 #define DP_DISCARD 7 102 103 /* GMAC Registers */ 104 105 #define GMAC_PIAC_REG 0x0004 106 #define PHY_ACS_ST BIT(31) 107 #define MDIO_REG_ADDR_S 25 108 #define MDIO_REG_ADDR_M 0x3e000000 109 #define MDIO_PHY_ADDR_S 20 110 #define MDIO_PHY_ADDR_M 0x1f00000 111 #define MDIO_CMD_S 18 112 #define MDIO_CMD_M 0xc0000 113 #define MDIO_ST_S 16 114 #define MDIO_ST_M 0x30000 115 #define MDIO_RW_DATA_S 0 116 #define MDIO_RW_DATA_M 0xffff 117 118 /* MDIO_CMD: MDIO commands */ 119 #define MDIO_CMD_ADDR 0 120 #define MDIO_CMD_WRITE 1 121 #define MDIO_CMD_READ 2 122 #define MDIO_CMD_READ_C45 3 123 124 /* MDIO_ST: MDIO start field */ 125 #define MDIO_ST_C45 0 126 #define MDIO_ST_C22 1 127 128 #define GMAC_PORT_MCR(p) (0x0100 + (p) * 0x100) 129 #define MAC_RX_PKT_LEN_S 24 130 #define MAC_RX_PKT_LEN_M 0x3000000 131 #define IPG_CFG_S 18 132 #define IPG_CFG_M 0xc0000 133 #define MAC_MODE BIT(16) 134 #define FORCE_MODE BIT(15) 135 #define MAC_TX_EN BIT(14) 136 #define MAC_RX_EN BIT(13) 137 #define BKOFF_EN BIT(9) 138 #define BACKPR_EN BIT(8) 139 #define FORCE_RX_FC BIT(5) 140 #define FORCE_TX_FC BIT(4) 141 #define FORCE_SPD_S 2 142 #define FORCE_SPD_M 0x0c 143 #define FORCE_DPX BIT(1) 144 #define FORCE_LINK BIT(0) 145 146 /* Values of IPG_CFG */ 147 #define IPG_96BIT 0 148 #define IPG_96BIT_WITH_SHORT_IPG 1 149 #define IPG_64BIT 2 150 151 /* MAC_RX_PKT_LEN: Max RX packet length */ 152 #define MAC_RX_PKT_LEN_1518 0 153 #define MAC_RX_PKT_LEN_1536 1 154 #define MAC_RX_PKT_LEN_1552 2 155 #define MAC_RX_PKT_LEN_JUMBO 3 156 157 /* FORCE_SPD: Forced link speed */ 158 #define SPEED_10M 0 159 #define SPEED_100M 1 160 #define SPEED_1000M 2 161 162 #define GMAC_TRGMII_RCK_CTRL 0x300 163 #define RX_RST BIT(31) 164 #define RXC_DQSISEL BIT(30) 165 166 #define GMAC_TRGMII_TD_ODT(n) (0x354 + (n) * 8) 167 #define TD_DM_DRVN_S 4 168 #define TD_DM_DRVN_M 0xf0 169 #define TD_DM_DRVP_S 0 170 #define TD_DM_DRVP_M 0x0f 171 172 /* MT7530 Registers */ 173 174 #define PCR_REG(p) (0x2004 + (p) * 0x100) 175 #define PORT_MATRIX_S 16 176 #define PORT_MATRIX_M 0xff0000 177 178 #define PVC_REG(p) (0x2010 + (p) * 0x100) 179 #define STAG_VPID_S 16 180 #define STAG_VPID_M 0xffff0000 181 #define VLAN_ATTR_S 6 182 #define VLAN_ATTR_M 0xc0 183 184 /* VLAN_ATTR: VLAN attributes */ 185 #define VLAN_ATTR_USER 0 186 #define VLAN_ATTR_STACK 1 187 #define VLAN_ATTR_TRANSLATION 2 188 #define VLAN_ATTR_TRANSPARENT 3 189 190 #define PMCR_REG(p) (0x3000 + (p) * 0x100) 191 /* XXX: all fields of MT7530 are defined under GMAC_PORT_MCR 192 * MT7531 specific fields are defined below 193 */ 194 #define FORCE_MODE_EEE1G BIT(25) 195 #define FORCE_MODE_EEE100 BIT(26) 196 #define FORCE_MODE_TX_FC BIT(27) 197 #define FORCE_MODE_RX_FC BIT(28) 198 #define FORCE_MODE_DPX BIT(29) 199 #define FORCE_MODE_SPD BIT(30) 200 #define FORCE_MODE_LNK BIT(31) 201 #define MT7531_FORCE_MODE FORCE_MODE_EEE1G | FORCE_MODE_EEE100 |\ 202 FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \ 203 FORCE_MODE_DPX | FORCE_MODE_SPD | \ 204 FORCE_MODE_LNK 205 206 /* MT7531 SGMII Registers */ 207 #define MT7531_SGMII_REG_BASE 0x5000 208 #define MT7531_SGMII_REG_PORT_BASE 0x1000 209 #define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \ 210 (p) * MT7531_SGMII_REG_PORT_BASE + (r)) 211 #define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(((p) - 5), 0x00) 212 #define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(((p) - 5), 0x20) 213 #define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(((p) - 5), 0xe8) 214 #define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(((p) - 5), 0x128) 215 /* XXX: all fields of MT7531 SGMII are defined under SGMSYS */ 216 217 /* MT753x System Control Register */ 218 #define SYS_CTRL_REG 0x7000 219 #define SW_PHY_RST BIT(2) 220 #define SW_SYS_RST BIT(1) 221 #define SW_REG_RST BIT(0) 222 223 /* MT7531 */ 224 #define MT7531_PHY_IAC 0x701c 225 /* XXX: all fields are defined under GMAC_PIAC_REG */ 226 227 #define MT7531_CLKGEN_CTRL 0x7500 228 #define CLK_SKEW_OUT_S 8 229 #define CLK_SKEW_OUT_M 0x300 230 #define CLK_SKEW_IN_S 6 231 #define CLK_SKEW_IN_M 0xc0 232 #define RXCLK_NO_DELAY BIT(5) 233 #define TXCLK_NO_REVERSE BIT(4) 234 #define GP_MODE_S 1 235 #define GP_MODE_M 0x06 236 #define GP_CLK_EN BIT(0) 237 238 /* Values of GP_MODE */ 239 #define GP_MODE_RGMII 0 240 #define GP_MODE_MII 1 241 #define GP_MODE_REV_MII 2 242 243 /* Values of CLK_SKEW_IN */ 244 #define CLK_SKEW_IN_NO_CHANGE 0 245 #define CLK_SKEW_IN_DELAY_100PPS 1 246 #define CLK_SKEW_IN_DELAY_200PPS 2 247 #define CLK_SKEW_IN_REVERSE 3 248 249 /* Values of CLK_SKEW_OUT */ 250 #define CLK_SKEW_OUT_NO_CHANGE 0 251 #define CLK_SKEW_OUT_DELAY_100PPS 1 252 #define CLK_SKEW_OUT_DELAY_200PPS 2 253 #define CLK_SKEW_OUT_REVERSE 3 254 255 #define HWTRAP_REG 0x7800 256 /* MT7530 Modified Hardware Trap Status Registers */ 257 #define MHWTRAP_REG 0x7804 258 #define CHG_TRAP BIT(16) 259 #define LOOPDET_DIS BIT(14) 260 #define P5_INTF_SEL_S 13 261 #define P5_INTF_SEL_M 0x2000 262 #define SMI_ADDR_S 11 263 #define SMI_ADDR_M 0x1800 264 #define XTAL_FSEL_S 9 265 #define XTAL_FSEL_M 0x600 266 #define P6_INTF_DIS BIT(8) 267 #define P5_INTF_MODE_S 7 268 #define P5_INTF_MODE_M 0x80 269 #define P5_INTF_DIS BIT(6) 270 #define C_MDIO_BPS BIT(5) 271 #define CHIP_MODE_S 0 272 #define CHIP_MODE_M 0x0f 273 274 /* P5_INTF_SEL: Interface type of Port5 */ 275 #define P5_INTF_SEL_GPHY 0 276 #define P5_INTF_SEL_GMAC5 1 277 278 /* P5_INTF_MODE: Interface mode of Port5 */ 279 #define P5_INTF_MODE_GMII_MII 0 280 #define P5_INTF_MODE_RGMII 1 281 282 #define MT7530_P6ECR 0x7830 283 #define P6_INTF_MODE_M 0x3 284 #define P6_INTF_MODE_S 0 285 286 /* P6_INTF_MODE: Interface mode of Port6 */ 287 #define P6_INTF_MODE_RGMII 0 288 #define P6_INTF_MODE_TRGMII 1 289 290 #define NUM_TRGMII_CTRL 5 291 292 #define MT7530_TRGMII_RD(n) (0x7a10 + (n) * 8) 293 #define RD_TAP_S 0 294 #define RD_TAP_M 0x7f 295 296 #define MT7530_TRGMII_TD_ODT(n) (0x7a54 + (n) * 8) 297 /* XXX: all fields are defined under GMAC_TRGMII_TD_ODT */ 298 299 /* TOP Signals Status Register */ 300 #define MT7531_TOP_SIG_SR 0x780c 301 #define PAD_MCM_SMI_EN BIT(0) 302 #define PAD_DUAL_SGMII_EN BIT(1) 303 304 /* MT7531 PLLGP Registers */ 305 #define MT7531_PLLGP_EN 0x7820 306 #define EN_COREPLL BIT(2) 307 #define SW_CLKSW BIT(1) 308 #define SW_PLLGP BIT(0) 309 310 #define MT7531_PLLGP_CR0 0x78a8 311 #define RG_COREPLL_EN BIT(22) 312 #define RG_COREPLL_POSDIV_S 23 313 #define RG_COREPLL_POSDIV_M 0x3800000 314 #define RG_COREPLL_SDM_PCW_S 1 315 #define RG_COREPLL_SDM_PCW_M 0x3ffffe 316 #define RG_COREPLL_SDM_PCW_CHG BIT(0) 317 318 /* MT7531 RGMII and SGMII PLL clock */ 319 #define MT7531_ANA_PLLGP_CR2 0x78b0 320 #define MT7531_ANA_PLLGP_CR5 0x78bc 321 322 /* MT7531 GPIO GROUP IOLB SMT0 Control */ 323 #define MT7531_SMT0_IOLB 0x7f04 324 #define SMT_IOLB_5_SMI_MDC_EN BIT(5) 325 326 /* MT7530 GPHY MDIO Indirect Access Registers */ 327 #define MII_MMD_ACC_CTL_REG 0x0d 328 #define MMD_CMD_S 14 329 #define MMD_CMD_M 0xc000 330 #define MMD_DEVAD_S 0 331 #define MMD_DEVAD_M 0x1f 332 333 /* MMD_CMD: MMD commands */ 334 #define MMD_ADDR 0 335 #define MMD_DATA 1 336 #define MMD_DATA_RW_POST_INC 2 337 #define MMD_DATA_W_POST_INC 3 338 339 #define MII_MMD_ADDR_DATA_REG 0x0e 340 341 /* MT7530 GPHY MDIO MMD Registers */ 342 #define CORE_PLL_GROUP2 0x401 343 #define RG_SYSPLL_EN_NORMAL BIT(15) 344 #define RG_SYSPLL_VODEN BIT(14) 345 #define RG_SYSPLL_POSDIV_S 5 346 #define RG_SYSPLL_POSDIV_M 0x60 347 348 #define CORE_PLL_GROUP4 0x403 349 #define MT7531_BYPASS_MODE BIT(4) 350 #define MT7531_POWER_ON_OFF BIT(5) 351 #define RG_SYSPLL_DDSFBK_EN BIT(12) 352 #define RG_SYSPLL_BIAS_EN BIT(11) 353 #define RG_SYSPLL_BIAS_LPF_EN BIT(10) 354 355 #define CORE_PLL_GROUP5 0x404 356 #define RG_LCDDS_PCW_NCPO1_S 0 357 #define RG_LCDDS_PCW_NCPO1_M 0xffff 358 359 #define CORE_PLL_GROUP6 0x405 360 #define RG_LCDDS_PCW_NCPO0_S 0 361 #define RG_LCDDS_PCW_NCPO0_M 0xffff 362 363 #define CORE_PLL_GROUP7 0x406 364 #define RG_LCDDS_PWDB BIT(15) 365 #define RG_LCDDS_ISO_EN BIT(13) 366 #define RG_LCCDS_C_S 4 367 #define RG_LCCDS_C_M 0x70 368 #define RG_LCDDS_PCW_NCPO_CHG BIT(3) 369 370 #define CORE_PLL_GROUP10 0x409 371 #define RG_LCDDS_SSC_DELTA_S 0 372 #define RG_LCDDS_SSC_DELTA_M 0xfff 373 374 #define CORE_PLL_GROUP11 0x40a 375 #define RG_LCDDS_SSC_DELTA1_S 0 376 #define RG_LCDDS_SSC_DELTA1_M 0xfff 377 378 #define CORE_GSWPLL_GRP1 0x40d 379 #define RG_GSWPLL_POSDIV_200M_S 12 380 #define RG_GSWPLL_POSDIV_200M_M 0x3000 381 #define RG_GSWPLL_EN_PRE BIT(11) 382 #define RG_GSWPLL_FBKDIV_200M_S 0 383 #define RG_GSWPLL_FBKDIV_200M_M 0xff 384 385 #define CORE_GSWPLL_GRP2 0x40e 386 #define RG_GSWPLL_POSDIV_500M_S 8 387 #define RG_GSWPLL_POSDIV_500M_M 0x300 388 #define RG_GSWPLL_FBKDIV_500M_S 0 389 #define RG_GSWPLL_FBKDIV_500M_M 0xff 390 391 #define CORE_TRGMII_GSW_CLK_CG 0x410 392 #define REG_GSWCK_EN BIT(0) 393 #define REG_TRGMIICK_EN BIT(1) 394 395 /* Extend PHY Control Register 3 */ 396 #define PHY_EXT_REG_14 0x14 397 398 /* Fields of PHY_EXT_REG_14 */ 399 #define PHY_EN_DOWN_SHFIT BIT(4) 400 401 /* Extend PHY Control Register 4 */ 402 #define PHY_EXT_REG_17 0x17 403 404 /* Fields of PHY_EXT_REG_17 */ 405 #define PHY_LINKDOWN_POWER_SAVING_EN BIT(4) 406 407 /* PHY RXADC Control Register 7 */ 408 #define PHY_DEV1E_REG_0C6 0x0c6 409 410 /* Fields of PHY_DEV1E_REG_0C6 */ 411 #define PHY_POWER_SAVING_S 8 412 #define PHY_POWER_SAVING_M 0x300 413 #define PHY_POWER_SAVING_TX 0x0 414 415 #endif /* _MTK_ETH_H_ */ 416