1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Broadcom STB PCIe controller driver
4 *
5 * Copyright (C) 2020 Samsung Electronics Co., Ltd.
6 *
7 * Based on upstream Linux kernel driver:
8 * drivers/pci/controller/pcie-brcmstb.c
9 * Copyright (C) 2009 - 2017 Broadcom
10 *
11 * Based driver by Nicolas Saenz Julienne
12 * Copyright (C) 2020 Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
13 */
14
15 #include <common.h>
16 #include <errno.h>
17 #include <dm.h>
18 #include <dm/ofnode.h>
19 #include <pci.h>
20 #include <asm/io.h>
21 #include <linux/bitfield.h>
22 #include <linux/log2.h>
23 #include <linux/iopoll.h>
24
25 /* Offset of the mandatory PCIe capability config registers */
26 #define BRCM_PCIE_CAP_REGS 0x00ac
27
28 /* The PCIe controller register offsets */
29 #define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1 0x0188
30 #define VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
31 #define VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN 0x0
32
33 #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
34 #define CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
35
36 #define PCIE_RC_DL_MDIO_ADDR 0x1100
37 #define PCIE_RC_DL_MDIO_WR_DATA 0x1104
38 #define PCIE_RC_DL_MDIO_RD_DATA 0x1108
39
40 #define PCIE_MISC_MISC_CTRL 0x4008
41 #define MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
42 #define MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
43 #define MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
44 #define MISC_CTRL_MAX_BURST_SIZE_128 0x0
45 #define MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
46
47 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
48 #define PCIE_MEM_WIN0_LO(win) \
49 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
50
51 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
52 #define PCIE_MEM_WIN0_HI(win) \
53 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)
54
55 #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
56 #define RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
57
58 #define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
59 #define RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
60 #define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
61
62 #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
63 #define RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
64
65 #define PCIE_MISC_PCIE_STATUS 0x4068
66 #define STATUS_PCIE_PORT_MASK 0x80
67 #define STATUS_PCIE_PORT_SHIFT 7
68 #define STATUS_PCIE_DL_ACTIVE_MASK 0x20
69 #define STATUS_PCIE_DL_ACTIVE_SHIFT 5
70 #define STATUS_PCIE_PHYLINKUP_MASK 0x10
71 #define STATUS_PCIE_PHYLINKUP_SHIFT 4
72
73 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
74 #define MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
75 #define MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
76 #define MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT 12
77 #define PCIE_MEM_WIN0_BASE_LIMIT(win) \
78 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)
79
80 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
81 #define MEM_WIN0_BASE_HI_BASE_MASK 0xff
82 #define PCIE_MEM_WIN0_BASE_HI(win) \
83 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)
84
85 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
86 #define PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
87 #define PCIE_MEM_WIN0_LIMIT_HI(win) \
88 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
89
90 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
91 #define PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
92 #define PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
93
94 #define PCIE_MSI_INTR2_CLR 0x4508
95 #define PCIE_MSI_INTR2_MASK_SET 0x4510
96
97 #define PCIE_EXT_CFG_DATA 0x8000
98
99 #define PCIE_EXT_CFG_INDEX 0x9000
100 #define PCIE_EXT_BUSNUM_SHIFT 20
101 #define PCIE_EXT_SLOT_SHIFT 15
102 #define PCIE_EXT_FUNC_SHIFT 12
103
104 #define PCIE_RGR1_SW_INIT_1 0x9210
105 #define RGR1_SW_INIT_1_PERST_MASK 0x1
106 #define RGR1_SW_INIT_1_INIT_MASK 0x2
107
108 /* PCIe parameters */
109 #define BRCM_NUM_PCIE_OUT_WINS 4
110
111 /* MDIO registers */
112 #define MDIO_PORT0 0x0
113 #define MDIO_DATA_MASK 0x7fffffff
114 #define MDIO_DATA_SHIFT 0
115 #define MDIO_PORT_MASK 0xf0000
116 #define MDIO_PORT_SHIFT 16
117 #define MDIO_REGAD_MASK 0xffff
118 #define MDIO_REGAD_SHIFT 0
119 #define MDIO_CMD_MASK 0xfff00000
120 #define MDIO_CMD_SHIFT 20
121 #define MDIO_CMD_READ 0x1
122 #define MDIO_CMD_WRITE 0x0
123 #define MDIO_DATA_DONE_MASK 0x80000000
124 #define SSC_REGS_ADDR 0x1100
125 #define SET_ADDR_OFFSET 0x1f
126 #define SSC_CNTL_OFFSET 0x2
127 #define SSC_CNTL_OVRD_EN_MASK 0x8000
128 #define SSC_CNTL_OVRD_VAL_MASK 0x4000
129 #define SSC_STATUS_OFFSET 0x1
130 #define SSC_STATUS_SSC_MASK 0x400
131 #define SSC_STATUS_SSC_SHIFT 10
132 #define SSC_STATUS_PLL_LOCK_MASK 0x800
133 #define SSC_STATUS_PLL_LOCK_SHIFT 11
134
135 /**
136 * struct brcm_pcie - the PCIe controller state
137 * @base: Base address of memory mapped IO registers of the controller
138 * @gen: Non-zero value indicates limitation of the PCIe controller operation
139 * to a specific generation (1, 2 or 3)
140 * @ssc: true indicates active Spread Spectrum Clocking operation
141 */
142 struct brcm_pcie {
143 void __iomem *base;
144
145 int gen;
146 bool ssc;
147 };
148
149 /**
150 * brcm_pcie_encode_ibar_size() - Encode the inbound "BAR" region size
151 * @size: The inbound region size
152 *
153 * This function converts size of the inbound "BAR" region to the non-linear
154 * values of the PCIE_MISC_RC_BAR[123]_CONFIG_LO register SIZE field.
155 *
156 * Return: The encoded inbound region size
157 */
brcm_pcie_encode_ibar_size(u64 size)158 static int brcm_pcie_encode_ibar_size(u64 size)
159 {
160 int log2_in = ilog2(size);
161
162 if (log2_in >= 12 && log2_in <= 15)
163 /* Covers 4KB to 32KB (inclusive) */
164 return (log2_in - 12) + 0x1c;
165 else if (log2_in >= 16 && log2_in <= 37)
166 /* Covers 64KB to 32GB, (inclusive) */
167 return log2_in - 15;
168
169 /* Something is awry so disable */
170 return 0;
171 }
172
173 /**
174 * brcm_pcie_rc_mode() - Check if PCIe controller is in RC mode
175 * @pcie: Pointer to the PCIe controller state
176 *
177 * The controller is capable of serving in both RC and EP roles.
178 *
179 * Return: true for RC mode, false for EP mode.
180 */
brcm_pcie_rc_mode(struct brcm_pcie * pcie)181 static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
182 {
183 u32 val;
184
185 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
186
187 return (val & STATUS_PCIE_PORT_MASK) >> STATUS_PCIE_PORT_SHIFT;
188 }
189
190 /**
191 * brcm_pcie_link_up() - Check whether the PCIe link is up
192 * @pcie: Pointer to the PCIe controller state
193 *
194 * Return: true if the link is up, false otherwise.
195 */
brcm_pcie_link_up(struct brcm_pcie * pcie)196 static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
197 {
198 u32 val, dla, plu;
199
200 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
201 dla = (val & STATUS_PCIE_DL_ACTIVE_MASK) >> STATUS_PCIE_DL_ACTIVE_SHIFT;
202 plu = (val & STATUS_PCIE_PHYLINKUP_MASK) >> STATUS_PCIE_PHYLINKUP_SHIFT;
203
204 return dla && plu;
205 }
206
brcm_pcie_config_address(const struct udevice * dev,pci_dev_t bdf,uint offset,void ** paddress)207 static int brcm_pcie_config_address(const struct udevice *dev, pci_dev_t bdf,
208 uint offset, void **paddress)
209 {
210 struct brcm_pcie *pcie = dev_get_priv(dev);
211 unsigned int pci_bus = PCI_BUS(bdf);
212 unsigned int pci_dev = PCI_DEV(bdf);
213 unsigned int pci_func = PCI_FUNC(bdf);
214 int idx;
215
216 /*
217 * Busses 0 (host PCIe bridge) and 1 (its immediate child)
218 * are limited to a single device each
219 */
220 if (pci_bus < 2 && pci_dev > 0)
221 return -EINVAL;
222
223 /* Accesses to the RC go right to the RC registers */
224 if (pci_bus == 0) {
225 *paddress = pcie->base + offset;
226 return 0;
227 }
228
229 /* For devices, write to the config space index register */
230 idx = (pci_bus << PCIE_EXT_BUSNUM_SHIFT)
231 | (pci_dev << PCIE_EXT_SLOT_SHIFT)
232 | (pci_func << PCIE_EXT_FUNC_SHIFT);
233
234 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
235 *paddress = pcie->base + PCIE_EXT_CFG_DATA + offset;
236
237 return 0;
238 }
239
brcm_pcie_read_config(const struct udevice * bus,pci_dev_t bdf,uint offset,ulong * valuep,enum pci_size_t size)240 static int brcm_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
241 uint offset, ulong *valuep,
242 enum pci_size_t size)
243 {
244 return pci_generic_mmap_read_config(bus, brcm_pcie_config_address,
245 bdf, offset, valuep, size);
246 }
247
brcm_pcie_write_config(struct udevice * bus,pci_dev_t bdf,uint offset,ulong value,enum pci_size_t size)248 static int brcm_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
249 uint offset, ulong value,
250 enum pci_size_t size)
251 {
252 return pci_generic_mmap_write_config(bus, brcm_pcie_config_address,
253 bdf, offset, value, size);
254 }
255
link_speed_to_str(unsigned int cls)256 static const char *link_speed_to_str(unsigned int cls)
257 {
258 switch (cls) {
259 case PCI_EXP_LNKSTA_CLS_2_5GB: return "2.5";
260 case PCI_EXP_LNKSTA_CLS_5_0GB: return "5.0";
261 case PCI_EXP_LNKSTA_CLS_8_0GB: return "8.0";
262 default:
263 break;
264 }
265
266 return "??";
267 }
268
brcm_pcie_mdio_form_pkt(unsigned int port,unsigned int regad,unsigned int cmd)269 static u32 brcm_pcie_mdio_form_pkt(unsigned int port, unsigned int regad,
270 unsigned int cmd)
271 {
272 u32 pkt;
273
274 pkt = (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
275 pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
276 pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
277
278 return pkt;
279 }
280
281 /**
282 * brcm_pcie_mdio_read() - Perform a register read on the internal MDIO bus
283 * @base: Pointer to the PCIe controller IO registers
284 * @port: The MDIO port number
285 * @regad: The register address
286 * @val: A pointer at which to store the read value
287 *
288 * Return: 0 on success and register value in @val, negative error value
289 * on failure.
290 */
brcm_pcie_mdio_read(void __iomem * base,unsigned int port,unsigned int regad,u32 * val)291 static int brcm_pcie_mdio_read(void __iomem *base, unsigned int port,
292 unsigned int regad, u32 *val)
293 {
294 u32 data, addr;
295 int ret;
296
297 addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ);
298 writel(addr, base + PCIE_RC_DL_MDIO_ADDR);
299 readl(base + PCIE_RC_DL_MDIO_ADDR);
300
301 ret = readl_poll_timeout(base + PCIE_RC_DL_MDIO_RD_DATA, data,
302 (data & MDIO_DATA_DONE_MASK), 100);
303
304 *val = data & MDIO_DATA_MASK;
305
306 return ret;
307 }
308
309 /**
310 * brcm_pcie_mdio_write() - Perform a register write on the internal MDIO bus
311 * @base: Pointer to the PCIe controller IO registers
312 * @port: The MDIO port number
313 * @regad: Address of the register
314 * @wrdata: The value to write
315 *
316 * Return: 0 on success, negative error value on failure.
317 */
brcm_pcie_mdio_write(void __iomem * base,unsigned int port,unsigned int regad,u16 wrdata)318 static int brcm_pcie_mdio_write(void __iomem *base, unsigned int port,
319 unsigned int regad, u16 wrdata)
320 {
321 u32 data, addr;
322
323 addr = brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE);
324 writel(addr, base + PCIE_RC_DL_MDIO_ADDR);
325 readl(base + PCIE_RC_DL_MDIO_ADDR);
326 writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA);
327
328 return readl_poll_timeout(base + PCIE_RC_DL_MDIO_WR_DATA, data,
329 !(data & MDIO_DATA_DONE_MASK), 100);
330 }
331
332 /**
333 * brcm_pcie_set_ssc() - Configure the controller for Spread Spectrum Clocking
334 * @base: pointer to the PCIe controller IO registers
335 *
336 * Return: 0 on success, negative error value on failure.
337 */
brcm_pcie_set_ssc(void __iomem * base)338 static int brcm_pcie_set_ssc(void __iomem *base)
339 {
340 int pll, ssc;
341 int ret;
342 u32 tmp;
343
344 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET,
345 SSC_REGS_ADDR);
346 if (ret < 0)
347 return ret;
348
349 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET, &tmp);
350 if (ret < 0)
351 return ret;
352
353 tmp |= (SSC_CNTL_OVRD_EN_MASK | SSC_CNTL_OVRD_VAL_MASK);
354
355 ret = brcm_pcie_mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, tmp);
356 if (ret < 0)
357 return ret;
358
359 udelay(1000);
360 ret = brcm_pcie_mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET, &tmp);
361 if (ret < 0)
362 return ret;
363
364 ssc = (tmp & SSC_STATUS_SSC_MASK) >> SSC_STATUS_SSC_SHIFT;
365 pll = (tmp & SSC_STATUS_PLL_LOCK_MASK) >> SSC_STATUS_PLL_LOCK_SHIFT;
366
367 return ssc && pll ? 0 : -EIO;
368 }
369
370 /**
371 * brcm_pcie_set_gen() - Limits operation to a specific generation (1, 2 or 3)
372 * @pcie: pointer to the PCIe controller state
373 * @gen: PCIe generation to limit the controller's operation to
374 */
brcm_pcie_set_gen(struct brcm_pcie * pcie,unsigned int gen)375 static void brcm_pcie_set_gen(struct brcm_pcie *pcie, unsigned int gen)
376 {
377 void __iomem *cap_base = pcie->base + BRCM_PCIE_CAP_REGS;
378
379 u16 lnkctl2 = readw(cap_base + PCI_EXP_LNKCTL2);
380 u32 lnkcap = readl(cap_base + PCI_EXP_LNKCAP);
381
382 lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
383 writel(lnkcap, cap_base + PCI_EXP_LNKCAP);
384
385 lnkctl2 = (lnkctl2 & ~0xf) | gen;
386 writew(lnkctl2, cap_base + PCI_EXP_LNKCTL2);
387 }
388
brcm_pcie_set_outbound_win(struct brcm_pcie * pcie,unsigned int win,u64 phys_addr,u64 pcie_addr,u64 size)389 static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
390 unsigned int win, u64 phys_addr,
391 u64 pcie_addr, u64 size)
392 {
393 void __iomem *base = pcie->base;
394 u32 phys_addr_mb_high, limit_addr_mb_high;
395 phys_addr_t phys_addr_mb, limit_addr_mb;
396 int high_addr_shift;
397 u32 tmp;
398
399 /* Set the base of the pcie_addr window */
400 writel(lower_32_bits(pcie_addr), base + PCIE_MEM_WIN0_LO(win));
401 writel(upper_32_bits(pcie_addr), base + PCIE_MEM_WIN0_HI(win));
402
403 /* Write the addr base & limit lower bits (in MBs) */
404 phys_addr_mb = phys_addr / SZ_1M;
405 limit_addr_mb = (phys_addr + size - 1) / SZ_1M;
406
407 tmp = readl(base + PCIE_MEM_WIN0_BASE_LIMIT(win));
408 u32p_replace_bits(&tmp, phys_addr_mb,
409 MEM_WIN0_BASE_LIMIT_BASE_MASK);
410 u32p_replace_bits(&tmp, limit_addr_mb,
411 MEM_WIN0_BASE_LIMIT_LIMIT_MASK);
412 writel(tmp, base + PCIE_MEM_WIN0_BASE_LIMIT(win));
413
414 /* Write the cpu & limit addr upper bits */
415 high_addr_shift = MEM_WIN0_BASE_LIMIT_BASE_HI_SHIFT;
416 phys_addr_mb_high = phys_addr_mb >> high_addr_shift;
417 tmp = readl(base + PCIE_MEM_WIN0_BASE_HI(win));
418 u32p_replace_bits(&tmp, phys_addr_mb_high,
419 MEM_WIN0_BASE_HI_BASE_MASK);
420 writel(tmp, base + PCIE_MEM_WIN0_BASE_HI(win));
421
422 limit_addr_mb_high = limit_addr_mb >> high_addr_shift;
423 tmp = readl(base + PCIE_MEM_WIN0_LIMIT_HI(win));
424 u32p_replace_bits(&tmp, limit_addr_mb_high,
425 PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK);
426 writel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win));
427 }
428
brcm_pcie_probe(struct udevice * dev)429 static int brcm_pcie_probe(struct udevice *dev)
430 {
431 struct udevice *ctlr = pci_get_controller(dev);
432 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
433 struct brcm_pcie *pcie = dev_get_priv(dev);
434 void __iomem *base = pcie->base;
435 struct pci_region region;
436 bool ssc_good = false;
437 int num_out_wins = 0;
438 u64 rc_bar2_offset, rc_bar2_size;
439 unsigned int scb_size_val;
440 int i, ret;
441 u16 nlw, cls, lnksta;
442 u32 tmp;
443
444 /*
445 * Reset the bridge, assert the fundamental reset. Note for some SoCs,
446 * e.g. BCM7278, the fundamental reset should not be asserted here.
447 * This will need to be changed when support for other SoCs is added.
448 */
449 setbits_le32(base + PCIE_RGR1_SW_INIT_1,
450 RGR1_SW_INIT_1_INIT_MASK | RGR1_SW_INIT_1_PERST_MASK);
451 /*
452 * The delay is a safety precaution to preclude the reset signal
453 * from looking like a glitch.
454 */
455 udelay(100);
456
457 /* Take the bridge out of reset */
458 clrbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK);
459
460 clrbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
461 PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
462
463 /* Wait for SerDes to be stable */
464 udelay(100);
465
466 /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
467 clrsetbits_le32(base + PCIE_MISC_MISC_CTRL,
468 MISC_CTRL_MAX_BURST_SIZE_MASK,
469 MISC_CTRL_SCB_ACCESS_EN_MASK |
470 MISC_CTRL_CFG_READ_UR_MODE_MASK |
471 MISC_CTRL_MAX_BURST_SIZE_128);
472
473 pci_get_dma_regions(dev, ®ion, 0);
474 rc_bar2_offset = region.bus_start - region.phys_start;
475 rc_bar2_size = 1ULL << fls64(region.size - 1);
476
477 tmp = lower_32_bits(rc_bar2_offset);
478 u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size),
479 RC_BAR2_CONFIG_LO_SIZE_MASK);
480 writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
481 writel(upper_32_bits(rc_bar2_offset),
482 base + PCIE_MISC_RC_BAR2_CONFIG_HI);
483
484 scb_size_val = rc_bar2_size ?
485 ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */
486
487 tmp = readl(base + PCIE_MISC_MISC_CTRL);
488 u32p_replace_bits(&tmp, scb_size_val,
489 MISC_CTRL_SCB0_SIZE_MASK);
490 writel(tmp, base + PCIE_MISC_MISC_CTRL);
491
492 /* Disable the PCIe->GISB memory window (RC_BAR1) */
493 clrbits_le32(base + PCIE_MISC_RC_BAR1_CONFIG_LO,
494 RC_BAR1_CONFIG_LO_SIZE_MASK);
495
496 /* Disable the PCIe->SCB memory window (RC_BAR3) */
497 clrbits_le32(base + PCIE_MISC_RC_BAR3_CONFIG_LO,
498 RC_BAR3_CONFIG_LO_SIZE_MASK);
499
500 /* Mask all interrupts since we are not handling any yet */
501 writel(0xffffffff, base + PCIE_MSI_INTR2_MASK_SET);
502
503 /* Clear any interrupts we find on boot */
504 writel(0xffffffff, base + PCIE_MSI_INTR2_CLR);
505
506 if (pcie->gen)
507 brcm_pcie_set_gen(pcie, pcie->gen);
508
509 /* Unassert the fundamental reset */
510 clrbits_le32(pcie->base + PCIE_RGR1_SW_INIT_1,
511 RGR1_SW_INIT_1_PERST_MASK);
512
513 /* Give the RC/EP time to wake up, before trying to configure RC.
514 * Intermittently check status for link-up, up to a total of 100ms.
515 */
516 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
517 mdelay(5);
518
519 if (!brcm_pcie_link_up(pcie)) {
520 printf("PCIe BRCM: link down\n");
521 return -EINVAL;
522 }
523
524 if (!brcm_pcie_rc_mode(pcie)) {
525 printf("PCIe misconfigured; is in EP mode\n");
526 return -EINVAL;
527 }
528
529 for (i = 0; i < hose->region_count; i++) {
530 struct pci_region *reg = &hose->regions[i];
531
532 if (reg->flags != PCI_REGION_MEM)
533 continue;
534
535 if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS)
536 return -EINVAL;
537
538 brcm_pcie_set_outbound_win(pcie, num_out_wins, reg->phys_start,
539 reg->bus_start, reg->size);
540
541 num_out_wins++;
542 }
543
544 /*
545 * For config space accesses on the RC, show the right class for
546 * a PCIe-PCIe bridge (the default setting is to be EP mode).
547 */
548 clrsetbits_le32(base + PCIE_RC_CFG_PRIV1_ID_VAL3,
549 CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK, 0x060400);
550
551 if (pcie->ssc) {
552 ret = brcm_pcie_set_ssc(pcie->base);
553 if (!ret)
554 ssc_good = true;
555 else
556 printf("PCIe BRCM: failed attempt to enter SSC mode\n");
557 }
558
559 lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
560 cls = lnksta & PCI_EXP_LNKSTA_CLS;
561 nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
562
563 printf("PCIe BRCM: link up, %s Gbps x%u %s\n", link_speed_to_str(cls),
564 nlw, ssc_good ? "(SSC)" : "(!SSC)");
565
566 /* PCIe->SCB endian mode for BAR */
567 clrsetbits_le32(base + PCIE_RC_CFG_VENDOR_SPECIFIC_REG1,
568 VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK,
569 VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN);
570 /*
571 * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
572 * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
573 */
574 setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
575 PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK);
576
577 return 0;
578 }
579
brcm_pcie_remove(struct udevice * dev)580 static int brcm_pcie_remove(struct udevice *dev)
581 {
582 struct brcm_pcie *pcie = dev_get_priv(dev);
583 void __iomem *base = pcie->base;
584
585 /* Assert fundamental reset */
586 setbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_PERST_MASK);
587
588 /* Turn off SerDes */
589 setbits_le32(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG,
590 PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
591
592 /* Shutdown bridge */
593 setbits_le32(base + PCIE_RGR1_SW_INIT_1, RGR1_SW_INIT_1_INIT_MASK);
594
595 return 0;
596 }
597
brcm_pcie_of_to_plat(struct udevice * dev)598 static int brcm_pcie_of_to_plat(struct udevice *dev)
599 {
600 struct brcm_pcie *pcie = dev_get_priv(dev);
601 ofnode dn = dev_ofnode(dev);
602 u32 max_link_speed;
603 int ret;
604
605 /* Get the controller base address */
606 pcie->base = dev_read_addr_ptr(dev);
607 if (!pcie->base)
608 return -EINVAL;
609
610 pcie->ssc = ofnode_read_bool(dn, "brcm,enable-ssc");
611
612 ret = ofnode_read_u32(dn, "max-link-speed", &max_link_speed);
613 if (ret < 0 || max_link_speed > 4)
614 pcie->gen = 0;
615 else
616 pcie->gen = max_link_speed;
617
618 return 0;
619 }
620
621 static const struct dm_pci_ops brcm_pcie_ops = {
622 .read_config = brcm_pcie_read_config,
623 .write_config = brcm_pcie_write_config,
624 };
625
626 static const struct udevice_id brcm_pcie_ids[] = {
627 { .compatible = "brcm,bcm2711-pcie" },
628 { }
629 };
630
631 U_BOOT_DRIVER(pcie_brcm_base) = {
632 .name = "pcie_brcm",
633 .id = UCLASS_PCI,
634 .ops = &brcm_pcie_ops,
635 .of_match = brcm_pcie_ids,
636 .probe = brcm_pcie_probe,
637 .remove = brcm_pcie_remove,
638 .of_to_plat = brcm_pcie_of_to_plat,
639 .priv_auto = sizeof(struct brcm_pcie),
640 .flags = DM_FLAG_OS_PREPARE,
641 };
642