1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2020 Broadcom
4 *
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <generic-phy.h>
11 #include <pci.h>
12 #include <malloc.h>
13 #include <asm/io.h>
14 #include <dm/device_compat.h>
15 #include <linux/log2.h>
16
17 #define EP_PERST_SOURCE_SELECT_SHIFT 2
18 #define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT)
19 #define EP_MODE_SURVIVE_PERST_SHIFT 1
20 #define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT)
21 #define RC_PCIE_RST_OUTPUT_SHIFT 0
22 #define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT)
23
24 #define CFG_IND_ADDR_MASK 0x00001ffc
25
26 #define CFG_ADDR_BUS_NUM_SHIFT 20
27 #define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
28 #define CFG_ADDR_DEV_NUM_SHIFT 15
29 #define CFG_ADDR_DEV_NUM_MASK 0x000f8000
30 #define CFG_ADDR_FUNC_NUM_SHIFT 12
31 #define CFG_ADDR_FUNC_NUM_MASK 0x00007000
32 #define CFG_ADDR_REG_NUM_SHIFT 2
33 #define CFG_ADDR_REG_NUM_MASK 0x00000ffc
34 #define CFG_ADDR_CFG_TYPE_SHIFT 0
35 #define CFG_ADDR_CFG_TYPE_MASK 0x00000003
36
37 #define IPROC_PCI_PM_CAP 0x48
38 #define IPROC_PCI_PM_CAP_MASK 0xffff
39 #define IPROC_PCI_EXP_CAP 0xac
40
41 #define IPROC_PCIE_REG_INVALID 0xffff
42
43 #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
44 #define PCI_EXP_RTCTL 28 /* Root Control */
45 /* CRS Software Visibility capability */
46 #define PCI_EXP_RTCAP_CRSVIS 0x0001
47
48 #define PCI_EXP_LNKSTA 18 /* Link Status */
49 #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
50
51 #define PCIE_PHYLINKUP_SHIFT 3
52 #define PCIE_PHYLINKUP BIT(PCIE_PHYLINKUP_SHIFT)
53 #define PCIE_DL_ACTIVE_SHIFT 2
54 #define PCIE_DL_ACTIVE BIT(PCIE_DL_ACTIVE_SHIFT)
55
56 /* derive the enum index of the outbound/inbound mapping registers */
57 #define MAP_REG(base_reg, index) ((base_reg) + (index) * 2)
58
59 /*
60 * Maximum number of outbound mapping window sizes that can be supported by any
61 * OARR/OMAP mapping pair
62 */
63 #define MAX_NUM_OB_WINDOW_SIZES 4
64
65 #define OARR_VALID_SHIFT 0
66 #define OARR_VALID BIT(OARR_VALID_SHIFT)
67 #define OARR_SIZE_CFG_SHIFT 1
68
69 /*
70 * Maximum number of inbound mapping region sizes that can be supported by an
71 * IARR
72 */
73 #define MAX_NUM_IB_REGION_SIZES 9
74
75 #define IMAP_VALID_SHIFT 0
76 #define IMAP_VALID BIT(IMAP_VALID_SHIFT)
77
78 #define APB_ERR_EN_SHIFT 0
79 #define APB_ERR_EN BIT(APB_ERR_EN_SHIFT)
80
81 /**
82 * iProc PCIe host registers
83 */
84 enum iproc_pcie_reg {
85 /* clock/reset signal control */
86 IPROC_PCIE_CLK_CTRL = 0,
87
88 /*
89 * To allow MSI to be steered to an external MSI controller (e.g., ARM
90 * GICv3 ITS)
91 */
92 IPROC_PCIE_MSI_GIC_MODE,
93
94 /*
95 * IPROC_PCIE_MSI_BASE_ADDR and IPROC_PCIE_MSI_WINDOW_SIZE define the
96 * window where the MSI posted writes are written, for the writes to be
97 * interpreted as MSI writes.
98 */
99 IPROC_PCIE_MSI_BASE_ADDR,
100 IPROC_PCIE_MSI_WINDOW_SIZE,
101
102 /*
103 * To hold the address of the register where the MSI writes are
104 * programed. When ARM GICv3 ITS is used, this should be programmed
105 * with the address of the GITS_TRANSLATER register.
106 */
107 IPROC_PCIE_MSI_ADDR_LO,
108 IPROC_PCIE_MSI_ADDR_HI,
109
110 /* enable MSI */
111 IPROC_PCIE_MSI_EN_CFG,
112
113 /* allow access to root complex configuration space */
114 IPROC_PCIE_CFG_IND_ADDR,
115 IPROC_PCIE_CFG_IND_DATA,
116
117 /* allow access to device configuration space */
118 IPROC_PCIE_CFG_ADDR,
119 IPROC_PCIE_CFG_DATA,
120
121 /* enable INTx */
122 IPROC_PCIE_INTX_EN,
123 IPROC_PCIE_INTX_CSR,
124
125 /* outbound address mapping */
126 IPROC_PCIE_OARR0,
127 IPROC_PCIE_OMAP0,
128 IPROC_PCIE_OARR1,
129 IPROC_PCIE_OMAP1,
130 IPROC_PCIE_OARR2,
131 IPROC_PCIE_OMAP2,
132 IPROC_PCIE_OARR3,
133 IPROC_PCIE_OMAP3,
134
135 /* inbound address mapping */
136 IPROC_PCIE_IARR0,
137 IPROC_PCIE_IMAP0,
138 IPROC_PCIE_IARR1,
139 IPROC_PCIE_IMAP1,
140 IPROC_PCIE_IARR2,
141 IPROC_PCIE_IMAP2,
142 IPROC_PCIE_IARR3,
143 IPROC_PCIE_IMAP3,
144 IPROC_PCIE_IARR4,
145 IPROC_PCIE_IMAP4,
146
147 /* config read status */
148 IPROC_PCIE_CFG_RD_STATUS,
149
150 /* link status */
151 IPROC_PCIE_LINK_STATUS,
152
153 /* enable APB error for unsupported requests */
154 IPROC_PCIE_APB_ERR_EN,
155
156 /* Ordering Mode configuration registers */
157 IPROC_PCIE_ORDERING_CFG,
158 IPROC_PCIE_IMAP0_RO_CONTROL,
159 IPROC_PCIE_IMAP1_RO_CONTROL,
160 IPROC_PCIE_IMAP2_RO_CONTROL,
161 IPROC_PCIE_IMAP3_RO_CONTROL,
162 IPROC_PCIE_IMAP4_RO_CONTROL,
163
164 /* total number of core registers */
165 IPROC_PCIE_MAX_NUM_REG,
166 };
167
168 /* iProc PCIe PAXB v2 registers */
169 static const u16 iproc_pcie_reg_paxb_v2[] = {
170 [IPROC_PCIE_CLK_CTRL] = 0x000,
171 [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
172 [IPROC_PCIE_CFG_IND_DATA] = 0x124,
173 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
174 [IPROC_PCIE_CFG_DATA] = 0x1fc,
175 [IPROC_PCIE_INTX_EN] = 0x330,
176 [IPROC_PCIE_INTX_CSR] = 0x334,
177 [IPROC_PCIE_OARR0] = 0xd20,
178 [IPROC_PCIE_OMAP0] = 0xd40,
179 [IPROC_PCIE_OARR1] = 0xd28,
180 [IPROC_PCIE_OMAP1] = 0xd48,
181 [IPROC_PCIE_OARR2] = 0xd60,
182 [IPROC_PCIE_OMAP2] = 0xd68,
183 [IPROC_PCIE_OARR3] = 0xdf0,
184 [IPROC_PCIE_OMAP3] = 0xdf8,
185 [IPROC_PCIE_IARR0] = 0xd00,
186 [IPROC_PCIE_IMAP0] = 0xc00,
187 [IPROC_PCIE_IARR2] = 0xd10,
188 [IPROC_PCIE_IMAP2] = 0xcc0,
189 [IPROC_PCIE_IARR3] = 0xe00,
190 [IPROC_PCIE_IMAP3] = 0xe08,
191 [IPROC_PCIE_IARR4] = 0xe68,
192 [IPROC_PCIE_IMAP4] = 0xe70,
193 [IPROC_PCIE_CFG_RD_STATUS] = 0xee0,
194 [IPROC_PCIE_LINK_STATUS] = 0xf0c,
195 [IPROC_PCIE_APB_ERR_EN] = 0xf40,
196 [IPROC_PCIE_ORDERING_CFG] = 0x2000,
197 [IPROC_PCIE_IMAP0_RO_CONTROL] = 0x201c,
198 [IPROC_PCIE_IMAP1_RO_CONTROL] = 0x2020,
199 [IPROC_PCIE_IMAP2_RO_CONTROL] = 0x2024,
200 [IPROC_PCIE_IMAP3_RO_CONTROL] = 0x2028,
201 [IPROC_PCIE_IMAP4_RO_CONTROL] = 0x202c,
202 };
203
204 /* iProc PCIe PAXC v2 registers */
205 static const u16 iproc_pcie_reg_paxc_v2[] = {
206 [IPROC_PCIE_MSI_GIC_MODE] = 0x050,
207 [IPROC_PCIE_MSI_BASE_ADDR] = 0x074,
208 [IPROC_PCIE_MSI_WINDOW_SIZE] = 0x078,
209 [IPROC_PCIE_MSI_ADDR_LO] = 0x07c,
210 [IPROC_PCIE_MSI_ADDR_HI] = 0x080,
211 [IPROC_PCIE_MSI_EN_CFG] = 0x09c,
212 [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
213 [IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
214 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
215 [IPROC_PCIE_CFG_DATA] = 0x1fc,
216 };
217
218 /**
219 * List of device IDs of controllers that have corrupted
220 * capability list that require SW fixup
221 */
222 static const u16 iproc_pcie_corrupt_cap_did[] = {
223 0x16cd,
224 0x16f0,
225 0xd802,
226 0xd804
227 };
228
229 enum iproc_pcie_type {
230 IPROC_PCIE_PAXB_V2,
231 IPROC_PCIE_PAXC,
232 IPROC_PCIE_PAXC_V2,
233 };
234
235 /**
236 * struct iproc_pcie_ob - iProc PCIe outbound mapping
237 *
238 * @axi_offset: offset from the AXI address to the internal address used by
239 * the iProc PCIe core
240 * @nr_windows: total number of supported outbound mapping windows
241 */
242 struct iproc_pcie_ob {
243 resource_size_t axi_offset;
244 unsigned int nr_windows;
245 };
246
247 /**
248 * struct iproc_pcie_ib - iProc PCIe inbound mapping
249 *
250 * @nr_regions: total number of supported inbound mapping regions
251 */
252 struct iproc_pcie_ib {
253 unsigned int nr_regions;
254 };
255
256 /**
257 * struct iproc_pcie_ob_map - outbound mapping controller specific parameters
258 *
259 * @window_sizes: list of supported outbound mapping window sizes in MB
260 * @nr_sizes: number of supported outbound mapping window sizes
261 */
262 struct iproc_pcie_ob_map {
263 resource_size_t window_sizes[MAX_NUM_OB_WINDOW_SIZES];
264 unsigned int nr_sizes;
265 };
266
267 static const struct iproc_pcie_ob_map paxb_v2_ob_map[] = {
268 {
269 /* OARR0/OMAP0 */
270 .window_sizes = { 128, 256 },
271 .nr_sizes = 2,
272 },
273 {
274 /* OARR1/OMAP1 */
275 .window_sizes = { 128, 256 },
276 .nr_sizes = 2,
277 },
278 {
279 /* OARR2/OMAP2 */
280 .window_sizes = { 128, 256, 512, 1024 },
281 .nr_sizes = 4,
282 },
283 {
284 /* OARR3/OMAP3 */
285 .window_sizes = { 128, 256, 512, 1024 },
286 .nr_sizes = 4,
287 },
288 };
289
290 /**
291 * iProc PCIe inbound mapping type
292 */
293 enum iproc_pcie_ib_map_type {
294 /* for DDR memory */
295 IPROC_PCIE_IB_MAP_MEM = 0,
296
297 /* for device I/O memory */
298 IPROC_PCIE_IB_MAP_IO,
299
300 /* invalid or unused */
301 IPROC_PCIE_IB_MAP_INVALID
302 };
303
304 /**
305 * struct iproc_pcie_ib_map - inbound mapping controller specific parameters
306 *
307 * @type: inbound mapping region type
308 * @size_unit: inbound mapping region size unit, could be SZ_1K, SZ_1M, or SZ_1G
309 * @region_sizes: list of supported inbound mapping region sizes in KB, MB, or
310 * GB, depedning on the size unit
311 * @nr_sizes: number of supported inbound mapping region sizes
312 * @nr_windows: number of supported inbound mapping windows for the region
313 * @imap_addr_offset: register offset between the upper and lower 32-bit
314 * IMAP address registers
315 * @imap_window_offset: register offset between each IMAP window
316 */
317 struct iproc_pcie_ib_map {
318 enum iproc_pcie_ib_map_type type;
319 unsigned int size_unit;
320 resource_size_t region_sizes[MAX_NUM_IB_REGION_SIZES];
321 unsigned int nr_sizes;
322 unsigned int nr_windows;
323 u16 imap_addr_offset;
324 u16 imap_window_offset;
325 };
326
327 static const struct iproc_pcie_ib_map paxb_v2_ib_map[] = {
328 {
329 /* IARR0/IMAP0 */
330 .type = IPROC_PCIE_IB_MAP_IO,
331 .size_unit = SZ_1K,
332 .region_sizes = { 32 },
333 .nr_sizes = 1,
334 .nr_windows = 8,
335 .imap_addr_offset = 0x40,
336 .imap_window_offset = 0x4,
337 },
338 {
339 /* IARR1/IMAP1 (currently unused) */
340 .type = IPROC_PCIE_IB_MAP_INVALID,
341 },
342 {
343 /* IARR2/IMAP2 */
344 .type = IPROC_PCIE_IB_MAP_MEM,
345 .size_unit = SZ_1M,
346 .region_sizes = { 64, 128, 256, 512, 1024, 2048, 4096, 8192,
347 16384 },
348 .nr_sizes = 9,
349 .nr_windows = 1,
350 .imap_addr_offset = 0x4,
351 .imap_window_offset = 0x8,
352 },
353 {
354 /* IARR3/IMAP3 */
355 .type = IPROC_PCIE_IB_MAP_MEM,
356 .size_unit = SZ_1G,
357 .region_sizes = { 1, 2, 4, 8, 16, 32 },
358 .nr_sizes = 6,
359 .nr_windows = 8,
360 .imap_addr_offset = 0x4,
361 .imap_window_offset = 0x8,
362 },
363 {
364 /* IARR4/IMAP4 */
365 .type = IPROC_PCIE_IB_MAP_MEM,
366 .size_unit = SZ_1G,
367 .region_sizes = { 32, 64, 128, 256, 512 },
368 .nr_sizes = 5,
369 .nr_windows = 8,
370 .imap_addr_offset = 0x4,
371 .imap_window_offset = 0x8,
372 },
373 };
374
375 /**
376 * struct iproc_pcie - iproc pcie device instance
377 *
378 * @dev: pointer to pcie udevice
379 * @base: device I/O base address
380 * @type: pci device type, PAXC or PAXB
381 * @reg_offsets: pointer to pcie host register
382 * @fix_paxc_cap: paxc capability
383 * @need_ob_cfg: outbound mapping status
384 * @ob: pcie outbound mapping
385 * @ob_map: pointer to outbound mapping parameters
386 * @need_ib_cfg: inbound mapping status
387 * @ib: pcie inbound mapping
388 * @ib_map: pointer to inbound mapping parameters
389 * @ep_is_internal: ep status
390 * @phy: phy device
391 * @link_is_active: link up status
392 * @has_apb_err_disable: apb error status
393 */
394 struct iproc_pcie {
395 struct udevice *dev;
396 void __iomem *base;
397 enum iproc_pcie_type type;
398 u16 *reg_offsets;
399 bool fix_paxc_cap;
400 bool need_ob_cfg;
401 struct iproc_pcie_ob ob;
402 const struct iproc_pcie_ob_map *ob_map;
403 bool need_ib_cfg;
404 struct iproc_pcie_ib ib;
405 const struct iproc_pcie_ib_map *ib_map;
406 bool ep_is_internal;
407 struct phy phy;
408 bool link_is_active;
409 bool has_apb_err_disable;
410 };
411
iproc_pcie_reg_is_invalid(u16 reg_offset)412 static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset)
413 {
414 return !!(reg_offset == IPROC_PCIE_REG_INVALID);
415 }
416
iproc_pcie_reg_offset(struct iproc_pcie * pcie,enum iproc_pcie_reg reg)417 static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie,
418 enum iproc_pcie_reg reg)
419 {
420 return pcie->reg_offsets[reg];
421 }
422
iproc_pcie_read_reg(struct iproc_pcie * pcie,enum iproc_pcie_reg reg)423 static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie,
424 enum iproc_pcie_reg reg)
425 {
426 u16 offset = iproc_pcie_reg_offset(pcie, reg);
427
428 if (iproc_pcie_reg_is_invalid(offset))
429 return 0;
430
431 return readl(pcie->base + offset);
432 }
433
iproc_pcie_write_reg(struct iproc_pcie * pcie,enum iproc_pcie_reg reg,u32 val)434 static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie,
435 enum iproc_pcie_reg reg, u32 val)
436 {
437 u16 offset = iproc_pcie_reg_offset(pcie, reg);
438
439 if (iproc_pcie_reg_is_invalid(offset))
440 return;
441
442 writel(val, pcie->base + offset);
443 }
444
iproc_pcie_map_ep_cfg_reg(const struct udevice * udev,pci_dev_t bdf,uint where,void ** paddress)445 static int iproc_pcie_map_ep_cfg_reg(const struct udevice *udev, pci_dev_t bdf,
446 uint where, void **paddress)
447 {
448 struct iproc_pcie *pcie = dev_get_priv(udev);
449 unsigned int busno = PCI_BUS(bdf);
450 unsigned int slot = PCI_DEV(bdf);
451 unsigned int fn = PCI_FUNC(bdf);
452
453 u16 offset;
454 u32 val;
455
456 /* root complex access */
457 if (busno == 0) {
458 if (slot > 0 || fn > 0)
459 return -ENODEV;
460
461 iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR,
462 where & CFG_IND_ADDR_MASK);
463 offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA);
464 if (iproc_pcie_reg_is_invalid(offset))
465 return -ENODEV;
466
467 *paddress = (pcie->base + offset);
468 return 0;
469 }
470
471 if (!pcie->link_is_active)
472 return -ENODEV;
473
474 /* EP device access */
475 val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
476 (slot << CFG_ADDR_DEV_NUM_SHIFT) |
477 (fn << CFG_ADDR_FUNC_NUM_SHIFT) |
478 (where & CFG_ADDR_REG_NUM_MASK) |
479 (1 & CFG_ADDR_CFG_TYPE_MASK);
480
481 iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val);
482 offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA);
483
484 if (iproc_pcie_reg_is_invalid(offset))
485 return -ENODEV;
486
487 *paddress = (pcie->base + offset);
488
489 return 0;
490 }
491
iproc_pcie_fix_cap(struct iproc_pcie * pcie,int where,ulong * val)492 static void iproc_pcie_fix_cap(struct iproc_pcie *pcie, int where, ulong *val)
493 {
494 u32 i, dev_id;
495
496 switch (where & ~0x3) {
497 case PCI_VENDOR_ID:
498 dev_id = *val >> 16;
499
500 /*
501 * Activate fixup for those controllers that have corrupted
502 * capability list registers
503 */
504 for (i = 0; i < ARRAY_SIZE(iproc_pcie_corrupt_cap_did); i++)
505 if (dev_id == iproc_pcie_corrupt_cap_did[i])
506 pcie->fix_paxc_cap = true;
507 break;
508
509 case IPROC_PCI_PM_CAP:
510 if (pcie->fix_paxc_cap) {
511 /* advertise PM, force next capability to PCIe */
512 *val &= ~IPROC_PCI_PM_CAP_MASK;
513 *val |= IPROC_PCI_EXP_CAP << 8 | PCI_CAP_ID_PM;
514 }
515 break;
516
517 case IPROC_PCI_EXP_CAP:
518 if (pcie->fix_paxc_cap) {
519 /* advertise root port, version 2, terminate here */
520 *val = (PCI_EXP_TYPE_ROOT_PORT << 4 | 2) << 16 |
521 PCI_CAP_ID_EXP;
522 }
523 break;
524
525 case IPROC_PCI_EXP_CAP + PCI_EXP_RTCTL:
526 /* Don't advertise CRS SV support */
527 *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
528 break;
529
530 default:
531 break;
532 }
533 }
534
iproc_pci_raw_config_read32(struct iproc_pcie * pcie,unsigned int devfn,int where,int size,u32 * val)535 static int iproc_pci_raw_config_read32(struct iproc_pcie *pcie,
536 unsigned int devfn, int where,
537 int size, u32 *val)
538 {
539 void __iomem *addr;
540 int ret;
541
542 ret = iproc_pcie_map_ep_cfg_reg(pcie->dev, devfn, where & ~0x3, &addr);
543 if (ret) {
544 *val = ~0;
545 return -EINVAL;
546 }
547
548 *val = readl(addr);
549
550 if (size <= 2)
551 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
552
553 return 0;
554 }
555
iproc_pci_raw_config_write32(struct iproc_pcie * pcie,unsigned int devfn,int where,int size,u32 val)556 static int iproc_pci_raw_config_write32(struct iproc_pcie *pcie,
557 unsigned int devfn, int where,
558 int size, u32 val)
559 {
560 void __iomem *addr;
561 int ret;
562 u32 mask, tmp;
563
564 ret = iproc_pcie_map_ep_cfg_reg(pcie->dev, devfn, where & ~0x3, &addr);
565 if (ret)
566 return -EINVAL;
567
568 if (size == 4) {
569 writel(val, addr);
570 return 0;
571 }
572
573 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
574 tmp = readl(addr) & mask;
575 tmp |= val << ((where & 0x3) * 8);
576 writel(tmp, addr);
577 return 0;
578 }
579
580 /**
581 * iproc_pcie_apb_err_disable() - configure apb error
582 *
583 * APB error forwarding can be disabled during access of configuration
584 * registers of the endpoint device, to prevent unsupported requests
585 * (typically seen during enumeration with multi-function devices) from
586 * triggering a system exception.
587 *
588 * @bus: pcie udevice
589 * @bdf: pdf value
590 * @disabled: flag to enable/disabled apb error
591 */
iproc_pcie_apb_err_disable(const struct udevice * bus,pci_dev_t bdf,bool disable)592 static inline void iproc_pcie_apb_err_disable(const struct udevice *bus,
593 pci_dev_t bdf, bool disable)
594 {
595 struct iproc_pcie *pcie = dev_get_priv(bus);
596 u32 val;
597
598 if (PCI_BUS(bdf) && pcie->has_apb_err_disable) {
599 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_APB_ERR_EN);
600 if (disable)
601 val &= ~APB_ERR_EN;
602 else
603 val |= APB_ERR_EN;
604 iproc_pcie_write_reg(pcie, IPROC_PCIE_APB_ERR_EN, val);
605 }
606 }
607
iproc_pcie_config_read32(const struct udevice * bus,pci_dev_t bdf,uint offset,ulong * valuep,enum pci_size_t size)608 static int iproc_pcie_config_read32(const struct udevice *bus, pci_dev_t bdf,
609 uint offset, ulong *valuep,
610 enum pci_size_t size)
611 {
612 struct iproc_pcie *pcie = dev_get_priv(bus);
613 int ret;
614 ulong data;
615
616 iproc_pcie_apb_err_disable(bus, bdf, true);
617 ret = pci_generic_mmap_read_config(bus, iproc_pcie_map_ep_cfg_reg,
618 bdf, offset, &data, PCI_SIZE_32);
619 iproc_pcie_apb_err_disable(bus, bdf, false);
620 if (size <= PCI_SIZE_16)
621 *valuep = (data >> (8 * (offset & 3))) &
622 ((1 << (BIT(size) * 8)) - 1);
623 else
624 *valuep = data;
625
626 if (!ret && PCI_BUS(bdf) == 0)
627 iproc_pcie_fix_cap(pcie, offset, valuep);
628
629 return ret;
630 }
631
iproc_pcie_config_write32(struct udevice * bus,pci_dev_t bdf,uint offset,ulong value,enum pci_size_t size)632 static int iproc_pcie_config_write32(struct udevice *bus, pci_dev_t bdf,
633 uint offset, ulong value,
634 enum pci_size_t size)
635 {
636 void *addr;
637 ulong mask, tmp;
638 int ret;
639
640 ret = iproc_pcie_map_ep_cfg_reg(bus, bdf, offset, &addr);
641 if (ret)
642 return ret;
643
644 if (size == PCI_SIZE_32) {
645 writel(value, addr);
646 return ret;
647 }
648
649 iproc_pcie_apb_err_disable(bus, bdf, true);
650 mask = ~(((1 << (BIT(size) * 8)) - 1) << ((offset & 0x3) * 8));
651 tmp = readl(addr) & mask;
652 tmp |= (value << ((offset & 0x3) * 8));
653 writel(tmp, addr);
654 iproc_pcie_apb_err_disable(bus, bdf, false);
655
656 return ret;
657 }
658
659 const static struct dm_pci_ops iproc_pcie_ops = {
660 .read_config = iproc_pcie_config_read32,
661 .write_config = iproc_pcie_config_write32,
662 };
663
iproc_pcie_rev_init(struct iproc_pcie * pcie)664 static int iproc_pcie_rev_init(struct iproc_pcie *pcie)
665 {
666 unsigned int reg_idx;
667 const u16 *regs;
668 u16 num_elements;
669
670 switch (pcie->type) {
671 case IPROC_PCIE_PAXC_V2:
672 pcie->ep_is_internal = true;
673 regs = iproc_pcie_reg_paxc_v2;
674 num_elements = ARRAY_SIZE(iproc_pcie_reg_paxc_v2);
675 break;
676 case IPROC_PCIE_PAXB_V2:
677 regs = iproc_pcie_reg_paxb_v2;
678 num_elements = ARRAY_SIZE(iproc_pcie_reg_paxb_v2);
679 pcie->has_apb_err_disable = true;
680 if (pcie->need_ob_cfg) {
681 pcie->ob.axi_offset = 0;
682 pcie->ob_map = paxb_v2_ob_map;
683 pcie->ob.nr_windows = ARRAY_SIZE(paxb_v2_ob_map);
684 }
685 pcie->need_ib_cfg = true;
686 pcie->ib.nr_regions = ARRAY_SIZE(paxb_v2_ib_map);
687 pcie->ib_map = paxb_v2_ib_map;
688 break;
689 default:
690 dev_dbg(pcie->dev, "incompatible iProc PCIe interface\n");
691 return -EINVAL;
692 }
693
694 pcie->reg_offsets = calloc(IPROC_PCIE_MAX_NUM_REG,
695 sizeof(*pcie->reg_offsets));
696 if (!pcie->reg_offsets)
697 return -ENOMEM;
698
699 /* go through the register table and populate all valid registers */
700 pcie->reg_offsets[0] = (pcie->type == IPROC_PCIE_PAXC_V2) ?
701 IPROC_PCIE_REG_INVALID : regs[0];
702 for (reg_idx = 1; reg_idx < num_elements; reg_idx++)
703 pcie->reg_offsets[reg_idx] = regs[reg_idx] ?
704 regs[reg_idx] : IPROC_PCIE_REG_INVALID;
705
706 return 0;
707 }
708
iproc_pcie_ob_is_valid(struct iproc_pcie * pcie,int window_idx)709 static inline bool iproc_pcie_ob_is_valid(struct iproc_pcie *pcie,
710 int window_idx)
711 {
712 u32 val;
713
714 val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_OARR0, window_idx));
715
716 return !!(val & OARR_VALID);
717 }
718
iproc_pcie_ob_write(struct iproc_pcie * pcie,int window_idx,int size_idx,u64 axi_addr,u64 pci_addr)719 static inline int iproc_pcie_ob_write(struct iproc_pcie *pcie, int window_idx,
720 int size_idx, u64 axi_addr, u64 pci_addr)
721 {
722 u16 oarr_offset, omap_offset;
723
724 /*
725 * Derive the OARR/OMAP offset from the first pair (OARR0/OMAP0) based
726 * on window index.
727 */
728 oarr_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OARR0,
729 window_idx));
730 omap_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OMAP0,
731 window_idx));
732 if (iproc_pcie_reg_is_invalid(oarr_offset) ||
733 iproc_pcie_reg_is_invalid(omap_offset))
734 return -EINVAL;
735
736 /*
737 * Program the OARR registers. The upper 32-bit OARR register is
738 * always right after the lower 32-bit OARR register.
739 */
740 writel(lower_32_bits(axi_addr) | (size_idx << OARR_SIZE_CFG_SHIFT) |
741 OARR_VALID, pcie->base + oarr_offset);
742 writel(upper_32_bits(axi_addr), pcie->base + oarr_offset + 4);
743
744 /* now program the OMAP registers */
745 writel(lower_32_bits(pci_addr), pcie->base + omap_offset);
746 writel(upper_32_bits(pci_addr), pcie->base + omap_offset + 4);
747
748 debug("ob window [%d]: offset 0x%x axi %pap pci %pap\n",
749 window_idx, oarr_offset, &axi_addr, &pci_addr);
750 debug("oarr lo 0x%x oarr hi 0x%x\n",
751 readl(pcie->base + oarr_offset),
752 readl(pcie->base + oarr_offset + 4));
753 debug("omap lo 0x%x omap hi 0x%x\n",
754 readl(pcie->base + omap_offset),
755 readl(pcie->base + omap_offset + 4));
756
757 return 0;
758 }
759
760 /**
761 * iproc_pcie_setup_ob() - setup outbound address mapping
762 *
763 * Some iProc SoCs require the SW to configure the outbound address mapping
764 * Outbound address translation:
765 *
766 * iproc_pcie_address = axi_address - axi_offset
767 * OARR = iproc_pcie_address
768 * OMAP = pci_addr
769 * axi_addr -> iproc_pcie_address -> OARR -> OMAP -> pci_address
770 *
771 * @pcie: pcie device
772 * @axi_addr: axi address to be translated
773 * @pci_addr: pci address
774 * @size: window size
775 *
776 * @return: 0 on success and -ve on failure
777 */
iproc_pcie_setup_ob(struct iproc_pcie * pcie,u64 axi_addr,u64 pci_addr,resource_size_t size)778 static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr,
779 u64 pci_addr, resource_size_t size)
780 {
781 struct iproc_pcie_ob *ob = &pcie->ob;
782 int ret = -EINVAL, window_idx, size_idx;
783
784 if (axi_addr < ob->axi_offset) {
785 pr_err("axi address %pap less than offset %pap\n",
786 &axi_addr, &ob->axi_offset);
787 return -EINVAL;
788 }
789
790 /*
791 * Translate the AXI address to the internal address used by the iProc
792 * PCIe core before programming the OARR
793 */
794 axi_addr -= ob->axi_offset;
795
796 /* iterate through all OARR/OMAP mapping windows */
797 for (window_idx = ob->nr_windows - 1; window_idx >= 0; window_idx--) {
798 const struct iproc_pcie_ob_map *ob_map =
799 &pcie->ob_map[window_idx];
800
801 /*
802 * If current outbound window is already in use, move on to the
803 * next one.
804 */
805 if (iproc_pcie_ob_is_valid(pcie, window_idx))
806 continue;
807
808 /*
809 * Iterate through all supported window sizes within the
810 * OARR/OMAP pair to find a match. Go through the window sizes
811 * in a descending order.
812 */
813 for (size_idx = ob_map->nr_sizes - 1; size_idx >= 0;
814 size_idx--) {
815 resource_size_t window_size =
816 ob_map->window_sizes[size_idx] * SZ_1M;
817
818 /*
819 * Keep iterating until we reach the last window and
820 * with the minimal window size at index zero. In this
821 * case, we take a compromise by mapping it using the
822 * minimum window size that can be supported
823 */
824 if (size < window_size) {
825 if (size_idx > 0 || window_idx > 0)
826 continue;
827
828 /*
829 * For the corner case of reaching the minimal
830 * window size that can be supported on the
831 * last window
832 */
833 axi_addr = ALIGN_DOWN(axi_addr, window_size);
834 pci_addr = ALIGN_DOWN(pci_addr, window_size);
835 size = window_size;
836 }
837
838 if (!IS_ALIGNED(axi_addr, window_size) ||
839 !IS_ALIGNED(pci_addr, window_size)) {
840 pr_err("axi %pap or pci %pap not aligned\n",
841 &axi_addr, &pci_addr);
842 return -EINVAL;
843 }
844
845 /*
846 * Match found! Program both OARR and OMAP and mark
847 * them as a valid entry.
848 */
849 ret = iproc_pcie_ob_write(pcie, window_idx, size_idx,
850 axi_addr, pci_addr);
851 if (ret)
852 goto err_ob;
853
854 size -= window_size;
855 if (size == 0)
856 return 0;
857
858 /*
859 * If we are here, we are done with the current window,
860 * but not yet finished all mappings. Need to move on
861 * to the next window.
862 */
863 axi_addr += window_size;
864 pci_addr += window_size;
865 break;
866 }
867 }
868
869 err_ob:
870 pr_err("unable to configure outbound mapping\n");
871 pr_err("axi %pap, axi offset %pap, pci %pap, res size %pap\n",
872 &axi_addr, &ob->axi_offset, &pci_addr, &size);
873
874 return ret;
875 }
876
iproc_pcie_map_ranges(struct udevice * dev)877 static int iproc_pcie_map_ranges(struct udevice *dev)
878 {
879 struct iproc_pcie *pcie = dev_get_priv(dev);
880 struct udevice *bus = pci_get_controller(dev);
881 struct pci_controller *hose = dev_get_uclass_priv(bus);
882 int i, ret;
883
884 for (i = 0; i < hose->region_count; i++) {
885 if (hose->regions[i].flags == PCI_REGION_MEM ||
886 hose->regions[i].flags == PCI_REGION_PREFETCH) {
887 debug("%d: bus_addr %p, axi_addr %p, size 0x%lx\n",
888 i, &hose->regions[i].bus_start,
889 &hose->regions[i].phys_start,
890 hose->regions[i].size);
891 ret = iproc_pcie_setup_ob(pcie,
892 hose->regions[i].phys_start,
893 hose->regions[i].bus_start,
894 hose->regions[i].size);
895 if (ret)
896 return ret;
897 }
898 }
899
900 return 0;
901 }
902
iproc_pcie_ib_is_in_use(struct iproc_pcie * pcie,int region_idx)903 static inline bool iproc_pcie_ib_is_in_use(struct iproc_pcie *pcie,
904 int region_idx)
905 {
906 const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx];
907 u32 val;
908
909 val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_IARR0, region_idx));
910
911 return !!(val & (BIT(ib_map->nr_sizes) - 1));
912 }
913
914 static inline bool
iproc_pcie_ib_check_type(const struct iproc_pcie_ib_map * ib_map,enum iproc_pcie_ib_map_type type)915 iproc_pcie_ib_check_type(const struct iproc_pcie_ib_map *ib_map,
916 enum iproc_pcie_ib_map_type type)
917 {
918 return !!(ib_map->type == type);
919 }
920
iproc_pcie_ib_write(struct iproc_pcie * pcie,int region_idx,int size_idx,int nr_windows,u64 axi_addr,u64 pci_addr,resource_size_t size)921 static int iproc_pcie_ib_write(struct iproc_pcie *pcie, int region_idx,
922 int size_idx, int nr_windows, u64 axi_addr,
923 u64 pci_addr, resource_size_t size)
924 {
925 const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx];
926 u16 iarr_offset, imap_offset;
927 u32 val;
928 int window_idx;
929
930 iarr_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_IARR0,
931 region_idx));
932 imap_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_IMAP0,
933 region_idx));
934 if (iproc_pcie_reg_is_invalid(iarr_offset) ||
935 iproc_pcie_reg_is_invalid(imap_offset))
936 return -EINVAL;
937
938 debug("ib region [%d]: offset 0x%x axi %pap pci %pap\n",
939 region_idx, iarr_offset, &axi_addr, &pci_addr);
940
941 /*
942 * Program the IARR registers. The upper 32-bit IARR register is
943 * always right after the lower 32-bit IARR register.
944 */
945 writel(lower_32_bits(pci_addr) | BIT(size_idx),
946 pcie->base + iarr_offset);
947 writel(upper_32_bits(pci_addr), pcie->base + iarr_offset + 4);
948
949 debug("iarr lo 0x%x iarr hi 0x%x\n",
950 readl(pcie->base + iarr_offset),
951 readl(pcie->base + iarr_offset + 4));
952
953 /*
954 * Now program the IMAP registers. Each IARR region may have one or
955 * more IMAP windows.
956 */
957 size >>= ilog2(nr_windows);
958 for (window_idx = 0; window_idx < nr_windows; window_idx++) {
959 val = readl(pcie->base + imap_offset);
960 val |= lower_32_bits(axi_addr) | IMAP_VALID;
961 writel(val, pcie->base + imap_offset);
962 writel(upper_32_bits(axi_addr),
963 pcie->base + imap_offset + ib_map->imap_addr_offset);
964
965 debug("imap window [%d] lo 0x%x hi 0x%x\n",
966 window_idx, readl(pcie->base + imap_offset),
967 readl(pcie->base + imap_offset +
968 ib_map->imap_addr_offset));
969
970 imap_offset += ib_map->imap_window_offset;
971 axi_addr += size;
972 }
973
974 return 0;
975 }
976
977 /**
978 * iproc_pcie_setup_ib() - setup inbound address mapping
979 *
980 * @pcie: pcie device
981 * @axi_addr: axi address to be translated
982 * @pci_addr: pci address
983 * @size: window size
984 * @type: inbound mapping type
985 *
986 * @return: 0 on success and -ve on failure
987 */
iproc_pcie_setup_ib(struct iproc_pcie * pcie,u64 axi_addr,u64 pci_addr,resource_size_t size,enum iproc_pcie_ib_map_type type)988 static int iproc_pcie_setup_ib(struct iproc_pcie *pcie, u64 axi_addr,
989 u64 pci_addr, resource_size_t size,
990 enum iproc_pcie_ib_map_type type)
991 {
992 struct iproc_pcie_ib *ib = &pcie->ib;
993 int ret;
994 unsigned int region_idx, size_idx;
995
996 /* iterate through all IARR mapping regions */
997 for (region_idx = 0; region_idx < ib->nr_regions; region_idx++) {
998 const struct iproc_pcie_ib_map *ib_map =
999 &pcie->ib_map[region_idx];
1000
1001 /*
1002 * If current inbound region is already in use or not a
1003 * compatible type, move on to the next.
1004 */
1005 if (iproc_pcie_ib_is_in_use(pcie, region_idx) ||
1006 !iproc_pcie_ib_check_type(ib_map, type))
1007 continue;
1008
1009 /* iterate through all supported region sizes to find a match */
1010 for (size_idx = 0; size_idx < ib_map->nr_sizes; size_idx++) {
1011 resource_size_t region_size =
1012 ib_map->region_sizes[size_idx] * ib_map->size_unit;
1013
1014 if (size != region_size)
1015 continue;
1016
1017 if (!IS_ALIGNED(axi_addr, region_size) ||
1018 !IS_ALIGNED(pci_addr, region_size)) {
1019 pr_err("axi %pap or pci %pap not aligned\n",
1020 &axi_addr, &pci_addr);
1021 return -EINVAL;
1022 }
1023
1024 /* Match found! Program IARR and all IMAP windows. */
1025 ret = iproc_pcie_ib_write(pcie, region_idx, size_idx,
1026 ib_map->nr_windows, axi_addr,
1027 pci_addr, size);
1028 if (ret)
1029 goto err_ib;
1030 else
1031 return 0;
1032 }
1033 }
1034 ret = -EINVAL;
1035
1036 err_ib:
1037 pr_err("unable to configure inbound mapping\n");
1038 pr_err("axi %pap, pci %pap, res size %pap\n",
1039 &axi_addr, &pci_addr, &size);
1040
1041 return ret;
1042 }
1043
iproc_pcie_map_dma_ranges(struct iproc_pcie * pcie)1044 static int iproc_pcie_map_dma_ranges(struct iproc_pcie *pcie)
1045 {
1046 int ret;
1047 struct pci_region regions;
1048 int i = 0;
1049
1050 while (!pci_get_dma_regions(pcie->dev, ®ions, i)) {
1051 dev_dbg(pcie->dev,
1052 "dma %d: bus_addr %#lx, axi_addr %#llx, size %#lx\n",
1053 i, regions.bus_start, regions.phys_start, regions.size);
1054
1055 /* Each range entry corresponds to an inbound mapping region */
1056 ret = iproc_pcie_setup_ib(pcie, regions.phys_start,
1057 regions.bus_start,
1058 regions.size,
1059 IPROC_PCIE_IB_MAP_MEM);
1060 if (ret)
1061 return ret;
1062 i++;
1063 }
1064 return 0;
1065 }
1066
iproc_pcie_reset_map_regs(struct iproc_pcie * pcie)1067 static void iproc_pcie_reset_map_regs(struct iproc_pcie *pcie)
1068 {
1069 struct iproc_pcie_ib *ib = &pcie->ib;
1070 struct iproc_pcie_ob *ob = &pcie->ob;
1071 int window_idx, region_idx;
1072
1073 if (pcie->ep_is_internal)
1074 return;
1075
1076 /* iterate through all OARR mapping regions */
1077 for (window_idx = ob->nr_windows - 1; window_idx >= 0; window_idx--) {
1078 iproc_pcie_write_reg(pcie, MAP_REG(IPROC_PCIE_OARR0,
1079 window_idx), 0);
1080 }
1081
1082 /* iterate through all IARR mapping regions */
1083 for (region_idx = 0; region_idx < ib->nr_regions; region_idx++) {
1084 iproc_pcie_write_reg(pcie, MAP_REG(IPROC_PCIE_IARR0,
1085 region_idx), 0);
1086 }
1087 }
1088
iproc_pcie_reset(struct iproc_pcie * pcie)1089 static void iproc_pcie_reset(struct iproc_pcie *pcie)
1090 {
1091 u32 val;
1092
1093 /*
1094 * PAXC and the internal emulated endpoint device downstream should not
1095 * be reset. If firmware has been loaded on the endpoint device at an
1096 * earlier boot stage, reset here causes issues.
1097 */
1098 if (pcie->ep_is_internal)
1099 return;
1100
1101 /*
1102 * Select perst_b signal as reset source. Put the device into reset,
1103 * and then bring it out of reset
1104 */
1105 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
1106 val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST &
1107 ~RC_PCIE_RST_OUTPUT;
1108 iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
1109 udelay(250);
1110
1111 val |= RC_PCIE_RST_OUTPUT;
1112 iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
1113 mdelay(100);
1114 }
1115
iproc_pcie_link_is_active(struct iproc_pcie * pcie)1116 static inline bool iproc_pcie_link_is_active(struct iproc_pcie *pcie)
1117 {
1118 u32 val;
1119
1120 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS);
1121 return !!((val & PCIE_PHYLINKUP) && (val & PCIE_DL_ACTIVE));
1122 }
1123
iproc_pcie_check_link(struct iproc_pcie * pcie)1124 static int iproc_pcie_check_link(struct iproc_pcie *pcie)
1125 {
1126 u32 link_status, class;
1127
1128 pcie->link_is_active = false;
1129 /* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */
1130 #define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c
1131 #define PCI_CLASS_BRIDGE_MASK 0xffff00
1132 #define PCI_CLASS_BRIDGE_SHIFT 8
1133 iproc_pci_raw_config_read32(pcie, 0,
1134 PCI_BRIDGE_CTRL_REG_OFFSET,
1135 4, &class);
1136 class &= ~PCI_CLASS_BRIDGE_MASK;
1137 class |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT);
1138 iproc_pci_raw_config_write32(pcie, 0,
1139 PCI_BRIDGE_CTRL_REG_OFFSET,
1140 4, class);
1141
1142 /*
1143 * PAXC connects to emulated endpoint devices directly and does not
1144 * have a Serdes. Therefore skip the link detection logic here.
1145 */
1146 if (pcie->ep_is_internal) {
1147 pcie->link_is_active = true;
1148 return 0;
1149 }
1150
1151 if (!iproc_pcie_link_is_active(pcie)) {
1152 pr_err("PHY or data link is INACTIVE!\n");
1153 return -ENODEV;
1154 }
1155
1156 #define PCI_TARGET_LINK_SPEED_MASK 0xf
1157 #define PCI_TARGET_LINK_WIDTH_MASK 0x3f
1158 #define PCI_TARGET_LINK_WIDTH_OFFSET 0x4
1159
1160 /* check link status to see if link is active */
1161 iproc_pci_raw_config_read32(pcie, 0,
1162 IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA,
1163 2, &link_status);
1164 if (link_status & PCI_EXP_LNKSTA_NLW)
1165 pcie->link_is_active = true;
1166
1167 if (pcie->link_is_active)
1168 pr_info("link UP @ Speed Gen-%d and width-x%d\n",
1169 link_status & PCI_TARGET_LINK_SPEED_MASK,
1170 (link_status >> PCI_TARGET_LINK_WIDTH_OFFSET) &
1171 PCI_TARGET_LINK_WIDTH_MASK);
1172 else
1173 pr_info("link DOWN\n");
1174
1175 return 0;
1176 }
1177
iproc_pcie_probe(struct udevice * dev)1178 static int iproc_pcie_probe(struct udevice *dev)
1179 {
1180 struct iproc_pcie *pcie = dev_get_priv(dev);
1181 int ret;
1182
1183 pcie->type = (enum iproc_pcie_type)dev_get_driver_data(dev);
1184 debug("PAX type %d\n", pcie->type);
1185 pcie->base = dev_read_addr_ptr(dev);
1186 debug("PAX reg base %p\n", pcie->base);
1187
1188 if (!pcie->base)
1189 return -ENODEV;
1190
1191 if (dev_read_bool(dev, "brcm,pcie-ob"))
1192 pcie->need_ob_cfg = true;
1193
1194 pcie->dev = dev;
1195 ret = iproc_pcie_rev_init(pcie);
1196 if (ret)
1197 return ret;
1198
1199 if (!pcie->ep_is_internal) {
1200 ret = generic_phy_get_by_name(dev, "pcie-phy", &pcie->phy);
1201 if (!ret) {
1202 ret = generic_phy_init(&pcie->phy);
1203 if (ret) {
1204 pr_err("failed to init %s PHY\n", dev->name);
1205 return ret;
1206 }
1207
1208 ret = generic_phy_power_on(&pcie->phy);
1209 if (ret) {
1210 pr_err("power on %s PHY failed\n", dev->name);
1211 goto err_exit_phy;
1212 }
1213 }
1214 }
1215
1216 iproc_pcie_reset(pcie);
1217
1218 if (pcie->need_ob_cfg) {
1219 ret = iproc_pcie_map_ranges(dev);
1220 if (ret) {
1221 pr_err("outbound map failed\n");
1222 goto err_power_off_phy;
1223 }
1224 }
1225
1226 if (pcie->need_ib_cfg) {
1227 ret = iproc_pcie_map_dma_ranges(pcie);
1228 if (ret) {
1229 pr_err("inbound map failed\n");
1230 goto err_power_off_phy;
1231 }
1232 }
1233
1234 if (iproc_pcie_check_link(pcie))
1235 pr_info("no PCIe EP device detected\n");
1236
1237 return 0;
1238
1239 err_power_off_phy:
1240 generic_phy_power_off(&pcie->phy);
1241 err_exit_phy:
1242 generic_phy_exit(&pcie->phy);
1243 return ret;
1244 }
1245
iproc_pcie_remove(struct udevice * dev)1246 static int iproc_pcie_remove(struct udevice *dev)
1247 {
1248 struct iproc_pcie *pcie = dev_get_priv(dev);
1249 int ret;
1250
1251 iproc_pcie_reset_map_regs(pcie);
1252
1253 if (generic_phy_valid(&pcie->phy)) {
1254 ret = generic_phy_power_off(&pcie->phy);
1255 if (ret) {
1256 pr_err("failed to power off PCIe phy\n");
1257 return ret;
1258 }
1259
1260 ret = generic_phy_exit(&pcie->phy);
1261 if (ret) {
1262 pr_err("failed to power off PCIe phy\n");
1263 return ret;
1264 }
1265 }
1266
1267 return 0;
1268 }
1269
1270 static const struct udevice_id pci_iproc_ids[] = {
1271 { .compatible = "brcm,iproc-pcie-paxb-v2",
1272 .data = IPROC_PCIE_PAXB_V2 },
1273 { .compatible = "brcm,iproc-pcie-paxc-v2",
1274 .data = IPROC_PCIE_PAXC_V2 },
1275 { }
1276 };
1277
1278 U_BOOT_DRIVER(pci_iproc) = {
1279 .name = "pci_iproc",
1280 .id = UCLASS_PCI,
1281 .of_match = pci_iproc_ids,
1282 .ops = &iproc_pcie_ops,
1283 .probe = iproc_pcie_probe,
1284 .remove = iproc_pcie_remove,
1285 .priv_auto = sizeof(struct iproc_pcie),
1286 .flags = DM_FLAG_OS_PREPARE,
1287 };
1288