1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2019
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
5 */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <dm.h>
10 #include <asm/clk.h>
11 #include <dm/test.h>
12 #include <dm/uclass.h>
13 #include <linux/err.h>
14 #include <test/test.h>
15 #include <test/ut.h>
16 #include <sandbox-clk.h>
17
18 /* Tests for Common Clock Framework driver */
dm_test_clk_ccf(struct unit_test_state * uts)19 static int dm_test_clk_ccf(struct unit_test_state *uts)
20 {
21 struct clk *clk, *pclk;
22 struct udevice *dev;
23 long long rate;
24 int ret;
25 #if CONFIG_IS_ENABLED(CLK_CCF)
26 const char *clkname;
27 int clkid, i;
28 #endif
29
30 /* Get the device using the clk device */
31 ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-ccf", &dev));
32
33 /* Test for clk_get_by_id() */
34 ret = clk_get_by_id(SANDBOX_CLK_ECSPI_ROOT, &clk);
35 ut_assertok(ret);
36 ut_asserteq_str("ecspi_root", clk->dev->name);
37 ut_asserteq(CLK_SET_RATE_PARENT, clk->flags);
38
39 /* Test for clk_get_parent_rate() */
40 ret = clk_get_by_id(SANDBOX_CLK_ECSPI1, &clk);
41 ut_assertok(ret);
42 ut_asserteq_str("ecspi1", clk->dev->name);
43 ut_asserteq(CLK_SET_RATE_PARENT, clk->flags);
44
45 rate = clk_get_parent_rate(clk);
46 ut_asserteq(rate, 20000000);
47
48 /* test the gate of CCF */
49 ret = clk_get_by_id(SANDBOX_CLK_ECSPI0, &clk);
50 ut_assertok(ret);
51 ut_asserteq_str("ecspi0", clk->dev->name);
52 ut_asserteq(CLK_SET_RATE_PARENT, clk->flags);
53
54 rate = clk_get_parent_rate(clk);
55 ut_asserteq(rate, 20000000);
56
57 /* Test the mux of CCF */
58 ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk);
59 ut_assertok(ret);
60 ut_asserteq_str("usdhc1_sel", clk->dev->name);
61 ut_asserteq(CLK_SET_RATE_NO_REPARENT, clk->flags);
62
63 rate = clk_get_parent_rate(clk);
64 ut_asserteq(rate, 60000000);
65
66 rate = clk_get_rate(clk);
67 ut_asserteq(rate, 60000000);
68
69 ret = clk_get_by_id(SANDBOX_CLK_PLL3_80M, &pclk);
70 ut_assertok(ret);
71
72 ret = clk_set_parent(clk, pclk);
73 ut_assertok(ret);
74
75 rate = clk_get_rate(clk);
76 ut_asserteq(rate, 80000000);
77
78 ret = clk_get_by_id(SANDBOX_CLK_USDHC2_SEL, &clk);
79 ut_assertok(ret);
80 ut_asserteq_str("usdhc2_sel", clk->dev->name);
81 ut_asserteq(CLK_SET_RATE_NO_REPARENT, clk->flags);
82
83 rate = clk_get_parent_rate(clk);
84 ut_asserteq(rate, 80000000);
85
86 pclk = clk_get_parent(clk);
87 ut_asserteq_str("pll3_80m", pclk->dev->name);
88 ut_asserteq(CLK_SET_RATE_PARENT, pclk->flags);
89
90 rate = clk_get_rate(clk);
91 ut_asserteq(rate, 80000000);
92
93 ret = clk_get_by_id(SANDBOX_CLK_PLL3_60M, &pclk);
94 ut_assertok(ret);
95
96 ret = clk_set_parent(clk, pclk);
97 ut_assertok(ret);
98
99 rate = clk_get_rate(clk);
100 ut_asserteq(rate, 60000000);
101
102 /* Test the composite of CCF */
103 ret = clk_get_by_id(SANDBOX_CLK_I2C, &clk);
104 ut_assertok(ret);
105 ut_asserteq_str("i2c", clk->dev->name);
106 ut_asserteq(CLK_SET_RATE_UNGATE, clk->flags);
107
108 rate = clk_get_rate(clk);
109 ut_asserteq(rate, 60000000);
110
111 #if CONFIG_IS_ENABLED(CLK_CCF)
112 /* Test clk tree enable/disable */
113 ret = clk_get_by_id(SANDBOX_CLK_I2C_ROOT, &clk);
114 ut_assertok(ret);
115 ut_asserteq_str("i2c_root", clk->dev->name);
116
117 ret = clk_enable(clk);
118 ut_assertok(ret);
119
120 ret = sandbox_clk_enable_count(clk);
121 ut_asserteq(ret, 1);
122
123 ret = clk_get_by_id(SANDBOX_CLK_I2C, &pclk);
124 ut_assertok(ret);
125
126 ret = sandbox_clk_enable_count(pclk);
127 ut_asserteq(ret, 1);
128
129 ret = clk_disable(clk);
130 ut_assertok(ret);
131
132 ret = sandbox_clk_enable_count(clk);
133 ut_asserteq(ret, 0);
134
135 ret = sandbox_clk_enable_count(pclk);
136 ut_asserteq(ret, 0);
137
138 /* Test clock re-parenting. */
139 ret = clk_get_by_id(SANDBOX_CLK_USDHC1_SEL, &clk);
140 ut_assertok(ret);
141 ut_asserteq_str("usdhc1_sel", clk->dev->name);
142
143 pclk = clk_get_parent(clk);
144 ut_assertok_ptr(pclk);
145 if (!strcmp(pclk->dev->name, "pll3_60m")) {
146 clkname = "pll3_80m";
147 clkid = SANDBOX_CLK_PLL3_80M;
148 } else {
149 clkname = "pll3_60m";
150 clkid = SANDBOX_CLK_PLL3_60M;
151 }
152
153 ret = clk_get_by_id(clkid, &pclk);
154 ut_assertok(ret);
155 ret = clk_set_parent(clk, pclk);
156 ut_assertok(ret);
157 pclk = clk_get_parent(clk);
158 ut_assertok_ptr(pclk);
159 ut_asserteq_str(clkname, pclk->dev->name);
160
161 /* Test disabling critical clock. */
162 ret = clk_get_by_id(SANDBOX_CLK_I2C_ROOT, &clk);
163 ut_assertok(ret);
164 ut_asserteq_str("i2c_root", clk->dev->name);
165
166 /* Disable it, if any. */
167 ret = sandbox_clk_enable_count(clk);
168 for (i = 0; i < ret; i++) {
169 ret = clk_disable(clk);
170 ut_assertok(ret);
171 }
172
173 ret = sandbox_clk_enable_count(clk);
174 ut_asserteq(ret, 0);
175
176 clk->flags = CLK_IS_CRITICAL;
177 ret = clk_enable(clk);
178 ut_assertok(ret);
179
180 ret = clk_disable(clk);
181 ut_assertok(ret);
182 ret = sandbox_clk_enable_count(clk);
183 ut_asserteq(ret, 1);
184 clk->flags &= ~CLK_IS_CRITICAL;
185
186 ret = clk_disable(clk);
187 ut_assertok(ret);
188 ret = sandbox_clk_enable_count(clk);
189 ut_asserteq(ret, 0);
190 #endif
191
192 return 1;
193 }
194
195 DM_TEST(dm_test_clk_ccf, UT_TESTF_SCAN_FDT);
196