1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com>
4 * (C) Copyright 2018 Neil Armstrong <narmstrong@baylibre.com>
5 */
6
7 #include <common.h>
8 #include <init.h>
9 #include <net.h>
10 #include <asm/arch/boot.h>
11 #include <asm/arch/eth.h>
12 #include <asm/arch/axg.h>
13 #include <asm/arch/mem.h>
14 #include <asm/global_data.h>
15 #include <asm/io.h>
16 #include <asm/armv8/mmu.h>
17 #include <linux/sizes.h>
18 #include <usb.h>
19 #include <linux/usb/otg.h>
20 #include <asm/arch/usb-gx.h>
21 #include <usb/dwc2_udc.h>
22 #include <clk.h>
23 #include <phy.h>
24
25 DECLARE_GLOBAL_DATA_PTR;
26
meson_get_boot_device(void)27 int meson_get_boot_device(void)
28 {
29 return readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_BOOT_DEVICE;
30 }
31
32 /* Configure the reserved memory zones exported by the secure registers
33 * into EFI and DTB reserved memory entries.
34 */
meson_init_reserved_memory(void * fdt)35 void meson_init_reserved_memory(void *fdt)
36 {
37 u64 bl31_size, bl31_start;
38 u64 bl32_size, bl32_start;
39 u32 reg;
40
41 /*
42 * Get ARM Trusted Firmware reserved memory zones in :
43 * - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
44 * - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
45 * - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
46 */
47 reg = readl(AXG_AO_SEC_GP_CFG3);
48
49 bl31_size = ((reg & AXG_AO_BL31_RSVMEM_SIZE_MASK)
50 >> AXG_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
51 bl32_size = (reg & AXG_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
52
53 bl31_start = readl(AXG_AO_SEC_GP_CFG5);
54 bl32_start = readl(AXG_AO_SEC_GP_CFG4);
55
56 /* Add BL31 reserved zone */
57 if (bl31_start && bl31_size)
58 meson_board_add_reserved_memory(fdt, bl31_start, bl31_size);
59
60 /* Add BL32 reserved zone */
61 if (bl32_start && bl32_size)
62 meson_board_add_reserved_memory(fdt, bl32_start, bl32_size);
63 }
64
get_effective_memsize(void)65 phys_size_t get_effective_memsize(void)
66 {
67 /* Size is reported in MiB, convert it in bytes */
68 return ((readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_MEM_SIZE_MASK)
69 >> AXG_AO_MEM_SIZE_SHIFT) * SZ_1M;
70 }
71
72 static struct mm_region axg_mem_map[] = {
73 {
74 .virt = 0x0UL,
75 .phys = 0x0UL,
76 .size = 0x80000000UL,
77 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
78 PTE_BLOCK_INNER_SHARE
79 }, {
80 .virt = 0xf0000000UL,
81 .phys = 0xf0000000UL,
82 .size = 0x10000000UL,
83 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
84 PTE_BLOCK_NON_SHARE |
85 PTE_BLOCK_PXN | PTE_BLOCK_UXN
86 }, {
87 /* List terminator */
88 0,
89 }
90 };
91
92 struct mm_region *mem_map = axg_mem_map;
93
94 #if CONFIG_IS_ENABLED(USB_DWC3_MESON_GXL) && \
95 CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
96 static struct dwc2_plat_otg_data meson_gx_dwc2_data;
97
board_usb_init(int index,enum usb_init_type init)98 int board_usb_init(int index, enum usb_init_type init)
99 {
100 struct fdtdec_phandle_args args;
101 const void *blob = gd->fdt_blob;
102 int node, dwc2_node;
103 struct udevice *dev, *clk_dev;
104 struct clk clk;
105 int ret;
106
107 /* find the usb glue node */
108 node = fdt_node_offset_by_compatible(blob, -1,
109 "amlogic,meson-gxl-usb-ctrl");
110 if (node < 0) {
111 debug("Not found usb-control node\n");
112 return -ENODEV;
113 }
114
115 if (!fdtdec_get_is_enabled(blob, node)) {
116 debug("usb is disabled in the device tree\n");
117 return -ENODEV;
118 }
119
120 ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
121 if (ret) {
122 debug("Not found usb-control device\n");
123 return ret;
124 }
125
126 /* find the dwc2 node */
127 dwc2_node = fdt_node_offset_by_compatible(blob, node,
128 "amlogic,meson-g12a-usb");
129 if (dwc2_node < 0) {
130 debug("Not found dwc2 node\n");
131 return -ENODEV;
132 }
133
134 if (!fdtdec_get_is_enabled(blob, dwc2_node)) {
135 debug("dwc2 is disabled in the device tree\n");
136 return -ENODEV;
137 }
138
139 meson_gx_dwc2_data.regs_otg = fdtdec_get_addr(blob, dwc2_node, "reg");
140 if (meson_gx_dwc2_data.regs_otg == FDT_ADDR_T_NONE) {
141 debug("usbotg: can't get base address\n");
142 return -ENODATA;
143 }
144
145 /* Enable clock */
146 ret = fdtdec_parse_phandle_with_args(blob, dwc2_node, "clocks",
147 "#clock-cells", 0, 0, &args);
148 if (ret) {
149 debug("usbotg has no clocks defined in the device tree\n");
150 return ret;
151 }
152
153 ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &clk_dev);
154 if (ret)
155 return ret;
156
157 if (args.args_count != 1) {
158 debug("Can't find clock ID in the device tree\n");
159 return -ENODATA;
160 }
161
162 clk.dev = clk_dev;
163 clk.id = args.args[0];
164
165 ret = clk_enable(&clk);
166 if (ret) {
167 debug("Failed to enable usbotg clock\n");
168 return ret;
169 }
170
171 meson_gx_dwc2_data.rx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
172 "g-rx-fifo-size", 0);
173 meson_gx_dwc2_data.np_tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
174 "g-np-tx-fifo-size", 0);
175 meson_gx_dwc2_data.tx_fifo_sz = fdtdec_get_int(blob, dwc2_node,
176 "g-tx-fifo-size", 0);
177
178 /* Switch to peripheral mode */
179 ret = dwc3_meson_gxl_force_mode(dev, USB_DR_MODE_PERIPHERAL);
180 if (ret)
181 return ret;
182
183 return dwc2_udc_probe(&meson_gx_dwc2_data);
184 }
185
board_usb_cleanup(int index,enum usb_init_type init)186 int board_usb_cleanup(int index, enum usb_init_type init)
187 {
188 const void *blob = gd->fdt_blob;
189 struct udevice *dev;
190 int node;
191 int ret;
192
193 /* find the usb glue node */
194 node = fdt_node_offset_by_compatible(blob, -1,
195 "amlogic,meson-gxl-usb-ctrl");
196 if (node < 0) {
197 debug("Not found usb-control node\n");
198 return -ENODEV;
199 }
200
201 if (!fdtdec_get_is_enabled(blob, node))
202 return -ENODEV;
203
204 ret = uclass_get_device_by_of_offset(UCLASS_SIMPLE_BUS, node, &dev);
205 if (ret)
206 return ret;
207
208 /* Switch to OTG mode */
209 ret = dwc3_meson_gxl_force_mode(dev, USB_DR_MODE_HOST);
210 if (ret)
211 return ret;
212
213 return 0;
214 }
215 #endif
216