1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2011
4 * Logic Product Development <www.logicpd.com>
5 *
6 * Author :
7 * Peter Barada <peter.barada@logicpd.com>
8 *
9 * Derived from Beagle Board and 3430 SDP code by
10 * Richard Woodruff <r-woodruff2@ti.com>
11 * Syed Mohammed Khasim <khasim@ti.com>
12 */
13 #include <common.h>
14 #include <dm.h>
15 #include <init.h>
16 #include <net.h>
17 #include <ns16550.h>
18 #include <flash.h>
19 #include <nand.h>
20 #include <i2c.h>
21 #include <serial.h>
22 #include <twl4030.h>
23 #include <asm/global_data.h>
24 #include <asm/io.h>
25 #include <asm/arch/mmc_host_def.h>
26 #include <asm/arch/mux.h>
27 #include <asm/arch/mem.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/gpio.h>
30 #include <asm/omap_mmc.h>
31 #include <asm/mach-types.h>
32 #include <linux/mtd/rawnand.h>
33 #include <asm/omap_musb.h>
34 #include <linux/errno.h>
35 #include <linux/usb/ch9.h>
36 #include <linux/usb/gadget.h>
37 #include <linux/usb/musb.h>
38 #include "omap3logic.h"
39 #ifdef CONFIG_USB_EHCI_HCD
40 #include <usb.h>
41 #include <asm/ehci-omap.h>
42 #endif
43
44 DECLARE_GLOBAL_DATA_PTR;
45
46 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1 0x00011203
47 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2 0x000A1302
48 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3 0x000F1302
49 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4 0x0A021303
50 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5 0x00120F18
51 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6 0x0A030000
52 #define LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7 0x00000C50
53
54 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1 0x00011203
55 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2 0x00091102
56 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3 0x000D1102
57 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4 0x09021103
58 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5 0x00100D15
59 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6 0x09030000
60 #define LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7 0x00000C50
61
62 #define CONFIG_SMC911X_BASE 0x08000000
63
64 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)65 int spl_start_uboot(void)
66 {
67 /* break into full u-boot on 'c' */
68 return serial_tstc() && serial_getc() == 'c';
69 }
70 #endif
71
72 #if defined(CONFIG_SPL_BUILD)
73 /*
74 * Routine: get_board_mem_timings
75 * Description: If we use SPL then there is no x-loader nor config header
76 * so we have to setup the DDR timings ourself on the first bank. This
77 * provides the timing values back to the function that configures
78 * the memory.
79 */
get_board_mem_timings(struct board_sdrc_timings * timings)80 void get_board_mem_timings(struct board_sdrc_timings *timings)
81 {
82 timings->mr = MICRON_V_MR_165;
83
84 if (get_cpu_family() == CPU_OMAP36XX) {
85 /* 200 MHz works for OMAP36/DM37 */
86 /* 256MB DDR */
87 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
88 timings->ctrla = MICRON_V_ACTIMA_200;
89 timings->ctrlb = MICRON_V_ACTIMB_200;
90 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
91 } else {
92 /* 165 MHz works for OMAP35 */
93 timings->mcfg = MICRON_V_MCFG_165(256 << 20);
94 timings->ctrla = MICRON_V_ACTIMA_165;
95 timings->ctrlb = MICRON_V_ACTIMB_165;
96 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
97 }
98 }
99
100 #define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c)
101 #define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84)
102 #define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80)
103
spl_board_prepare_for_linux(void)104 void spl_board_prepare_for_linux(void)
105 {
106 /* The Micron NAND starts locked which
107 * prohibits mounting the NAND as RW
108 * The following commands are what unlocks
109 * the NAND to become RW Falcon Mode does not
110 * have as many smarts as U-Boot, but Logic PD
111 * only makes NAND with 512MB so these hard coded
112 * values should work for all current models
113 */
114
115 writeb(0x70, GPMC_NAND_COMMAND_0);
116 writeb(-1, GPMC_NAND_DATA_0);
117 writeb(0x7a, GPMC_NAND_COMMAND_0);
118 writeb(0x00, GPMC_NAND_ADDRESS_0);
119 writeb(0x00, GPMC_NAND_ADDRESS_0);
120 writeb(0x00, GPMC_NAND_ADDRESS_0);
121 writeb(-1, GPMC_NAND_COMMAND_0);
122
123 /* Begin address 0 */
124 writeb(NAND_CMD_UNLOCK1, 0x6e00007c);
125 writeb(0x00, GPMC_NAND_ADDRESS_0);
126 writeb(0x00, GPMC_NAND_ADDRESS_0);
127 writeb(0x00, GPMC_NAND_ADDRESS_0);
128 writeb(-1, GPMC_NAND_DATA_0);
129
130 /* Ending address at the end of Flash */
131 writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0);
132 writeb(0xc0, GPMC_NAND_ADDRESS_0);
133 writeb(0xff, GPMC_NAND_ADDRESS_0);
134 writeb(0x03, GPMC_NAND_ADDRESS_0);
135 writeb(-1, GPMC_NAND_DATA_0);
136 writeb(0x79, GPMC_NAND_COMMAND_0);
137 writeb(-1, GPMC_NAND_DATA_0);
138 writeb(-1, GPMC_NAND_DATA_0);
139 }
140 #endif
141
142 /*
143 * Routine: misc_init_r
144 * Description: Configure board specific parts
145 */
misc_init_r(void)146 int misc_init_r(void)
147 {
148 twl4030_power_init();
149 twl4030_power_mmc_init(0);
150 omap_die_id_display();
151 return 0;
152 }
153
154 #if defined(CONFIG_FLASH_CFI_DRIVER)
155 static const u32 gpmc_dm37_c2nor_config[] = {
156 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG1,
157 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG2,
158 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG3,
159 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG4,
160 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG5,
161 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG6,
162 LOGIC_MT28_DM37_ASYNC_GPMC_CONFIG7
163 };
164
165 static const u32 gpmc_omap35_c2nor_config[] = {
166 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG1,
167 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG2,
168 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG3,
169 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG4,
170 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG5,
171 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG6,
172 LOGIC_MT28_OMAP35_ASYNC_GPMC_CONFIG7
173 };
174 #endif
175
176 /*
177 * Routine: board_init
178 * Description: Early hardware init.
179 */
board_init(void)180 int board_init(void)
181 {
182 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
183
184 /* boot param addr */
185 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
186 #if defined(CONFIG_FLASH_CFI_DRIVER)
187 if (get_cpu_family() == CPU_OMAP36XX) {
188 /* Enable CS2 for NOR Flash */
189 enable_gpmc_cs_config(gpmc_dm37_c2nor_config, &gpmc_cfg->cs[2],
190 0x10000000, GPMC_SIZE_64M);
191 } else {
192 enable_gpmc_cs_config(gpmc_omap35_c2nor_config, &gpmc_cfg->cs[2],
193 0x10000000, GPMC_SIZE_64M);
194 }
195 #endif
196 return 0;
197 }
198
199 #ifdef CONFIG_BOARD_LATE_INIT
200
unlock_nand(void)201 static void unlock_nand(void)
202 {
203 int dev = nand_curr_device;
204 struct mtd_info *mtd;
205
206 mtd = get_nand_dev_by_index(dev);
207 nand_unlock(mtd, 0, mtd->size, 0);
208 }
209
210 #ifdef CONFIG_SMC911X
211 /* GPMC CS1 settings for Logic SOM LV/Torpedo LAN92xx Ethernet chip */
212 static const u32 gpmc_lan92xx_config[] = {
213 NET_LAN92XX_GPMC_CONFIG1,
214 NET_LAN92XX_GPMC_CONFIG2,
215 NET_LAN92XX_GPMC_CONFIG3,
216 NET_LAN92XX_GPMC_CONFIG4,
217 NET_LAN92XX_GPMC_CONFIG5,
218 NET_LAN92XX_GPMC_CONFIG6,
219 };
220 #endif
221
board_late_init(void)222 int board_late_init(void)
223 {
224 #ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
225 unlock_nand();
226 #endif
227
228 #ifdef CONFIG_SMC911X
229 enable_gpmc_cs_config(gpmc_lan92xx_config, &gpmc_cfg->cs[1],
230 CONFIG_SMC911X_BASE, GPMC_SIZE_16M);
231 #endif
232 return 0;
233 }
234 #endif
235
236 #if defined(CONFIG_MMC)
board_mmc_power_init(void)237 void board_mmc_power_init(void)
238 {
239 twl4030_power_mmc_init(0);
240 }
241 #endif
242