1 /*
2 * Lowlevel setup for EXYNOS5 based board
3 *
4 * Copyright (C) 2013 Samsung Electronics
5 * Rajeshwari Shinde <rajeshwari.s@samsung.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26 #include <common.h>
27 #include <config.h>
28 #include <debug_uart.h>
29 #include <asm/system.h>
30 #include <init.h>
31 #include <asm/arch/cpu.h>
32 #include <asm/arch/dmc.h>
33 #include <asm/arch/power.h>
34 #include <asm/arch/tzpc.h>
35 #include <asm/arch/periph.h>
36 #include <asm/arch/pinmux.h>
37 #include <asm/arch/system.h>
38 #include <asm/armv7.h>
39 #include "common_setup.h"
40 #include "exynos5_setup.h"
41
42 /* These are the things we can do during low-level init */
43 enum {
44 DO_WAKEUP = 1 << 0,
45 DO_CLOCKS = 1 << 1,
46 DO_MEM_RESET = 1 << 2,
47 DO_UART = 1 << 3,
48 DO_POWER = 1 << 4,
49 };
50
51 #ifdef CONFIG_EXYNOS5420
52 /*
53 * Power up secondary CPUs.
54 */
secondary_cpu_start(void)55 static void secondary_cpu_start(void)
56 {
57 v7_enable_smp(EXYNOS5420_INFORM_BASE);
58 svc32_mode_en();
59 branch_bx(CONFIG_EXYNOS_RELOCATE_CODE_BASE);
60 }
61
62 /*
63 * This is the entry point of hotplug-in and
64 * cluster switching.
65 */
low_power_start(void)66 static void low_power_start(void)
67 {
68 uint32_t val, reg_val;
69
70 reg_val = readl(EXYNOS5420_SPARE_BASE);
71 if (reg_val != CPU_RST_FLAG_VAL) {
72 writel(0x0, CONFIG_LOWPOWER_FLAG);
73 branch_bx(0x0);
74 }
75
76 reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4);
77 if (reg_val != (uint32_t)&low_power_start) {
78 /* Store jump address as low_power_start if not present */
79 writel((uint32_t)&low_power_start, CONFIG_PHY_IRAM_BASE + 0x4);
80 dsb();
81 sev();
82 }
83
84 /* Set the CPU to SVC32 mode */
85 svc32_mode_en();
86
87 #ifndef CONFIG_SYS_L2CACHE_OFF
88 /* Read MIDR for Primary Part Number */
89 mrc_midr(val);
90 val = (val >> 4);
91 val &= 0xf;
92
93 if (val == 0xf) {
94 configure_l2_ctlr();
95 configure_l2_actlr();
96 v7_enable_l2_hazard_detect();
97 }
98 #endif
99
100 /* Invalidate L1 & TLB */
101 val = 0x0;
102 mcr_tlb(val);
103 mcr_icache(val);
104
105 /* Disable MMU stuff and caches */
106 mrc_sctlr(val);
107
108 val &= ~((0x2 << 12) | 0x7);
109 val |= ((0x1 << 12) | (0x8 << 8) | 0x2);
110 mcr_sctlr(val);
111
112 /* CPU state is hotplug or reset */
113 secondary_cpu_start();
114
115 /* Core should not enter into WFI here */
116 wfi();
117 }
118
119 /*
120 * Pointer to this function is stored in iRam which is used
121 * for jump and power down of a specific core.
122 */
power_down_core(void)123 static void power_down_core(void)
124 {
125 uint32_t tmp, core_id, core_config;
126
127 /* Get the unique core id */
128 /*
129 * Multiprocessor Affinity Register
130 * [11:8] Cluster ID
131 * [1:0] CPU ID
132 */
133 mrc_mpafr(core_id);
134 tmp = core_id & 0x3;
135 core_id = (core_id >> 6) & ~3;
136 core_id |= tmp;
137 core_id &= 0x3f;
138
139 /* Set the status of the core to low */
140 core_config = (core_id * CPU_CONFIG_STATUS_OFFSET);
141 core_config += EXYNOS5420_CPU_CONFIG_BASE;
142 writel(0x0, core_config);
143
144 /* Core enter WFI */
145 wfi();
146 }
147
148 /*
149 * Configurations for secondary cores are inapt at this stage.
150 * Reconfigure secondary cores. Shutdown and change the status
151 * of all cores except the primary core.
152 */
secondary_cores_configure(void)153 static void secondary_cores_configure(void)
154 {
155 /* Clear secondary boot iRAM base */
156 writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C));
157
158 /* set lowpower flag and address */
159 writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG);
160 writel((uint32_t)&low_power_start, CONFIG_LOWPOWER_ADDR);
161 writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE);
162 /* Store jump address for power down */
163 writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4);
164
165 /* Need all core power down check */
166 dsb();
167 sev();
168 }
169
170 extern void relocate_wait_code(void);
171 #endif
172
do_lowlevel_init(void)173 int do_lowlevel_init(void)
174 {
175 uint32_t reset_status;
176 int actions = 0;
177
178 arch_cpu_init();
179
180 #if !defined(CONFIG_SYS_L2CACHE_OFF) && defined(CONFIG_EXYNOS5420)
181 /*
182 * Init L2 cache parameters here for use by boot and resume
183 *
184 * These are here instead of in v7_outer_cache_enable() so that the
185 * L2 cache settings get properly set even at resume time or if we're
186 * running U-Boot with the cache off. The kernel still needs us to
187 * set these for it.
188 */
189 configure_l2_ctlr();
190 configure_l2_actlr();
191 dsb();
192 isb();
193
194 relocate_wait_code();
195
196 /* Reconfigure secondary cores */
197 secondary_cores_configure();
198 #endif
199
200 reset_status = get_reset_status();
201
202 switch (reset_status) {
203 case S5P_CHECK_SLEEP:
204 actions = DO_CLOCKS | DO_WAKEUP;
205 break;
206 case S5P_CHECK_DIDLE:
207 case S5P_CHECK_LPA:
208 actions = DO_WAKEUP;
209 break;
210 default:
211 /* This is a normal boot (not a wake from sleep) */
212 actions = DO_CLOCKS | DO_MEM_RESET | DO_POWER;
213 }
214
215 if (actions & DO_POWER)
216 set_ps_hold_ctrl();
217
218 if (actions & DO_CLOCKS) {
219 system_clock_init();
220 #ifdef CONFIG_DEBUG_UART
221 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)) || \
222 !defined(CONFIG_SPL_BUILD)
223 exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
224 debug_uart_init();
225 #endif
226 #endif
227 mem_ctrl_init(actions & DO_MEM_RESET);
228 tzpc_init();
229 }
230
231 return actions & DO_WAKEUP;
232 }
233