1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2017 Intel Corporation.
4 * Copyright 2019 Google LLC
5 *
6 * Modified from coreboot pmclib.c, pmc.c and pmutil.c
7 */
8
9 #define LOG_CATEGORY UCLASS_ACPI_PMC
10
11 #include <common.h>
12 #include <dm.h>
13 #include <dt-structs.h>
14 #include <log.h>
15 #include <spl.h>
16 #include <acpi/acpi_s3.h>
17 #include <asm/io.h>
18 #include <asm/pci.h>
19 #include <asm/arch/pmc.h>
20 #include <linux/bitops.h>
21 #include <power/acpi_pmc.h>
22
23 #define GPIO_GPE_CFG 0x1050
24
25 /* Memory mapped IO registers behind PMC_BASE_ADDRESS */
26 #define PRSTS 0x1000
27 #define GEN_PMCON1 0x1020
28 #define COLD_BOOT_STS BIT(27)
29 #define COLD_RESET_STS BIT(26)
30 #define WARM_RESET_STS BIT(25)
31 #define GLOBAL_RESET_STS BIT(24)
32 #define SRS BIT(20)
33 #define MS4V BIT(18)
34 #define RPS BIT(2)
35 #define GEN_PMCON1_CLR1_BITS (COLD_BOOT_STS | COLD_RESET_STS | \
36 WARM_RESET_STS | GLOBAL_RESET_STS | \
37 SRS | MS4V)
38 #define GEN_PMCON2 0x1024
39 #define GEN_PMCON3 0x1028
40
41 /* Offset of TCO registers from ACPI base I/O address */
42 #define TCO_REG_OFFSET 0x60
43 #define TCO1_STS 0x64
44 #define DMISCI_STS BIT(9)
45 #define BOOT_STS BIT(18)
46 #define TCO2_STS 0x66
47 #define TCO1_CNT 0x68
48 #define TCO_LOCK BIT(12)
49 #define TCO2_CNT 0x6a
50
51 enum {
52 ETR = 0x1048,
53 CF9_LOCK = 1UL << 31,
54 CF9_GLB_RST = 1 << 20,
55 };
56
apl_pmc_fill_power_state(struct udevice * dev)57 static int apl_pmc_fill_power_state(struct udevice *dev)
58 {
59 struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
60
61 upriv->tco1_sts = inw(upriv->acpi_base + TCO1_STS);
62 upriv->tco2_sts = inw(upriv->acpi_base + TCO2_STS);
63
64 upriv->prsts = readl(upriv->pmc_bar0 + PRSTS);
65 upriv->gen_pmcon1 = readl(upriv->pmc_bar0 + GEN_PMCON1);
66 upriv->gen_pmcon2 = readl(upriv->pmc_bar0 + GEN_PMCON2);
67 upriv->gen_pmcon3 = readl(upriv->pmc_bar0 + GEN_PMCON3);
68
69 return 0;
70 }
71
apl_prev_sleep_state(struct udevice * dev,int prev_sleep_state)72 static int apl_prev_sleep_state(struct udevice *dev, int prev_sleep_state)
73 {
74 struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
75
76 /* WAK_STS bit will not be set when waking from G3 state */
77 if (!(upriv->pm1_sts & WAK_STS) &&
78 (upriv->gen_pmcon1 & COLD_BOOT_STS))
79 prev_sleep_state = ACPI_S5;
80
81 return prev_sleep_state;
82 }
83
apl_disable_tco(struct udevice * dev)84 static int apl_disable_tco(struct udevice *dev)
85 {
86 struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
87
88 pmc_disable_tco_base(upriv->acpi_base + TCO_REG_OFFSET);
89
90 return 0;
91 }
92
apl_global_reset_set_enable(struct udevice * dev,bool enable)93 static int apl_global_reset_set_enable(struct udevice *dev, bool enable)
94 {
95 struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
96
97 if (enable)
98 setbits_le32(upriv->pmc_bar0 + ETR, CF9_GLB_RST);
99 else
100 clrbits_le32(upriv->pmc_bar0 + ETR, CF9_GLB_RST);
101
102 return 0;
103 }
104
apl_pmc_ofdata_to_uc_plat(struct udevice * dev)105 int apl_pmc_ofdata_to_uc_plat(struct udevice *dev)
106 {
107 struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
108 struct apl_pmc_plat *plat = dev_get_plat(dev);
109
110 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
111 u32 base[6];
112 int size;
113 int ret;
114
115 ret = dev_read_u32_array(dev, "early-regs", base,
116 ARRAY_SIZE(base));
117 if (ret)
118 return log_msg_ret("Missing/short early-regs", ret);
119 if (spl_phase() == PHASE_TPL) {
120 upriv->pmc_bar0 = (void *)base[0];
121 upriv->pmc_bar2 = (void *)base[2];
122
123 /* Since PCI is not enabled, we must get the BDF manually */
124 plat->bdf = pci_get_devfn(dev);
125 if (plat->bdf < 0)
126 return log_msg_ret("Cannot get PMC PCI address",
127 plat->bdf);
128 }
129 upriv->acpi_base = base[4];
130
131 /* Get the dwX values for pmc gpe settings */
132 size = dev_read_size(dev, "gpe0-dw");
133 if (size < 0)
134 return log_msg_ret("Cannot read gpe0-dm", size);
135 upriv->gpe0_count = size / sizeof(u32);
136 ret = dev_read_u32_array(dev, "gpe0-dw", upriv->gpe0_dw,
137 upriv->gpe0_count);
138 if (ret)
139 return log_msg_ret("Bad gpe0-dw", ret);
140
141 return pmc_ofdata_to_uc_plat(dev);
142 #else
143 struct dtd_intel_apl_pmc *dtplat = &plat->dtplat;
144
145 plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]);
146 upriv->pmc_bar0 = (void *)dtplat->early_regs[0];
147 upriv->pmc_bar2 = (void *)dtplat->early_regs[2];
148 upriv->acpi_base = dtplat->early_regs[4];
149 upriv->gpe0_dwx_mask = dtplat->gpe0_dwx_mask;
150 upriv->gpe0_dwx_shift_base = dtplat->gpe0_dwx_shift_base;
151 upriv->gpe0_sts_reg = dtplat->gpe0_sts;
152 upriv->gpe0_sts_reg += upriv->acpi_base;
153 upriv->gpe0_en_reg = dtplat->gpe0_en;
154 upriv->gpe0_en_reg += upriv->acpi_base;
155 upriv->gpe0_count = min((int)ARRAY_SIZE(dtplat->gpe0_dw), GPE0_REG_MAX);
156 memcpy(upriv->gpe0_dw, dtplat->gpe0_dw, sizeof(dtplat->gpe0_dw));
157 #endif
158 upriv->gpe_cfg = (u32 *)(upriv->pmc_bar0 + GPIO_GPE_CFG);
159
160 return 0;
161 }
162
enable_pmcbar(struct udevice * dev)163 static int enable_pmcbar(struct udevice *dev)
164 {
165 struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
166 struct apl_pmc_plat *priv = dev_get_plat(dev);
167 pci_dev_t pmc = priv->bdf;
168
169 /*
170 * Set PMC base addresses and enable decoding. BARs 1 and 3 are 64-bit
171 * BARs.
172 */
173 pci_x86_write_config(pmc, PCI_BASE_ADDRESS_0, (ulong)upriv->pmc_bar0,
174 PCI_SIZE_32);
175 pci_x86_write_config(pmc, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
176 pci_x86_write_config(pmc, PCI_BASE_ADDRESS_2, (ulong)upriv->pmc_bar2,
177 PCI_SIZE_32);
178 pci_x86_write_config(pmc, PCI_BASE_ADDRESS_3, 0, PCI_SIZE_32);
179 pci_x86_write_config(pmc, PCI_BASE_ADDRESS_4, upriv->acpi_base,
180 PCI_SIZE_16);
181 pci_x86_write_config(pmc, PCI_COMMAND, PCI_COMMAND_IO |
182 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
183 PCI_SIZE_16);
184
185 return 0;
186 }
187
apl_pmc_probe(struct udevice * dev)188 static int apl_pmc_probe(struct udevice *dev)
189 {
190 if (spl_phase() == PHASE_TPL) {
191 return enable_pmcbar(dev);
192 } else {
193 struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
194
195 upriv->pmc_bar0 = (void *)dm_pci_read_bar32(dev, 0);
196 upriv->pmc_bar2 = (void *)dm_pci_read_bar32(dev, 2);
197 }
198
199 return 0;
200 }
201
202 static const struct acpi_pmc_ops apl_pmc_ops = {
203 .init = apl_pmc_fill_power_state,
204 .prev_sleep_state = apl_prev_sleep_state,
205 .disable_tco = apl_disable_tco,
206 .global_reset_set_enable = apl_global_reset_set_enable,
207 };
208
209 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
210 static const struct udevice_id apl_pmc_ids[] = {
211 { .compatible = "intel,apl-pmc" },
212 { }
213 };
214 #endif
215
216 U_BOOT_DRIVER(intel_apl_pmc) = {
217 .name = "intel_apl_pmc",
218 .id = UCLASS_ACPI_PMC,
219 .of_match = of_match_ptr(apl_pmc_ids),
220 .of_to_plat = apl_pmc_ofdata_to_uc_plat,
221 .probe = apl_pmc_probe,
222 .ops = &apl_pmc_ops,
223 .plat_auto = sizeof(struct apl_pmc_plat),
224 };
225