1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 * Copyright 2019 NXP 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 11 12 #define CONFIG_SYS_FSL_CLK 13 14 #define CONFIG_SKIP_LOWLEVEL_INIT 15 #define CONFIG_DEEP_SLEEP 16 17 /* 18 * Size of malloc() pool 19 */ 20 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 21 22 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 23 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 24 25 #define CONFIG_SYS_CLK_FREQ 100000000 26 #define CONFIG_DDR_CLK_FREQ 100000000 27 28 #define DDR_SDRAM_CFG 0x470c0008 29 #define DDR_CS0_BNDS 0x008000bf 30 #define DDR_CS0_CONFIG 0x80014302 31 #define DDR_TIMING_CFG_0 0x50550004 32 #define DDR_TIMING_CFG_1 0xbcb38c56 33 #define DDR_TIMING_CFG_2 0x0040d120 34 #define DDR_TIMING_CFG_3 0x010e1000 35 #define DDR_TIMING_CFG_4 0x00000001 36 #define DDR_TIMING_CFG_5 0x03401400 37 #define DDR_SDRAM_CFG_2 0x00401010 38 #define DDR_SDRAM_MODE 0x00061c60 39 #define DDR_SDRAM_MODE_2 0x00180000 40 #define DDR_SDRAM_INTERVAL 0x18600618 41 #define DDR_DDR_WRLVL_CNTL 0x8655f605 42 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 43 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 44 #define DDR_DDR_CDR1 0x80040000 45 #define DDR_DDR_CDR2 0x00000001 46 #define DDR_SDRAM_CLK_CNTL 0x02000000 47 #define DDR_DDR_ZQ_CNTL 0x89080600 48 #define DDR_CS0_CONFIG_2 0 49 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 50 #define SDRAM_CFG2_D_INIT 0x00000010 51 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 52 #define SDRAM_CFG2_FRC_SR 0x80000000 53 #define SDRAM_CFG_BI 0x00000001 54 55 #ifdef CONFIG_RAMBOOT_PBL 56 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg 57 #endif 58 59 #ifdef CONFIG_SD_BOOT 60 #ifdef CONFIG_SD_BOOT_QSPI 61 #define CONFIG_SYS_FSL_PBL_RCW \ 62 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg 63 #else 64 #define CONFIG_SYS_FSL_PBL_RCW \ 65 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg 66 #endif 67 68 #ifdef CONFIG_NXP_ESBC 69 /* 70 * HDR would be appended at end of image and copied to DDR along 71 * with U-Boot image. 72 */ 73 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 74 #endif /* ifdef CONFIG_NXP_ESBC */ 75 76 #define CONFIG_SPL_MAX_SIZE 0x1a000 77 #define CONFIG_SPL_STACK 0x1001d000 78 #define CONFIG_SPL_PAD_TO 0x1c000 79 80 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 81 CONFIG_SYS_MONITOR_LEN) 82 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 83 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 84 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 85 86 #ifdef CONFIG_U_BOOT_HDR_SIZE 87 /* 88 * HDR would be appended at end of image and copied to DDR along 89 * with U-Boot image. Here u-boot max. size is 512K. So if binary 90 * size increases then increase this size in case of secure boot as 91 * it uses raw u-boot image instead of fit image. 92 */ 93 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 94 #else 95 #define CONFIG_SYS_MONITOR_LEN 0x100000 96 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ 97 #endif 98 99 #define PHYS_SDRAM 0x80000000 100 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 101 102 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 103 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 104 105 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 106 107 /* 108 * IFC Definitions 109 */ 110 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 111 #define CONFIG_FSL_IFC 112 #define CONFIG_SYS_FLASH_BASE 0x60000000 113 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 114 115 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 116 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 117 CSPR_PORT_SIZE_16 | \ 118 CSPR_MSEL_NOR | \ 119 CSPR_V) 120 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 121 122 /* NOR Flash Timing Params */ 123 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 124 CSOR_NOR_TRHZ_80) 125 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 126 FTIM0_NOR_TEADC(0x5) | \ 127 FTIM0_NOR_TAVDS(0x0) | \ 128 FTIM0_NOR_TEAHC(0x5)) 129 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 130 FTIM1_NOR_TRAD_NOR(0x1A) | \ 131 FTIM1_NOR_TSEQRAD_NOR(0x13)) 132 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 133 FTIM2_NOR_TCH(0x4) | \ 134 FTIM2_NOR_TWP(0x1c) | \ 135 FTIM2_NOR_TWPH(0x0e)) 136 #define CONFIG_SYS_NOR_FTIM3 0 137 138 #define CONFIG_SYS_FLASH_QUIET_TEST 139 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 140 141 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 142 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 143 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 144 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 145 146 #define CONFIG_SYS_FLASH_EMPTY_INFO 147 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 148 149 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 150 #define CONFIG_SYS_WRITE_SWAPPED_DATA 151 #endif 152 153 /* CPLD */ 154 155 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 156 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 157 158 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 159 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 160 CSPR_PORT_SIZE_8 | \ 161 CSPR_MSEL_GPCM | \ 162 CSPR_V) 163 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 164 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 165 CSOR_NOR_NOR_MODE_AVD_NOR | \ 166 CSOR_NOR_TRHZ_80) 167 168 /* CPLD Timing parameters for IFC GPCM */ 169 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 170 FTIM0_GPCM_TEADC(0xf) | \ 171 FTIM0_GPCM_TEAHC(0xf)) 172 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 173 FTIM1_GPCM_TRAD(0x3f)) 174 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 175 FTIM2_GPCM_TCH(0xf) | \ 176 FTIM2_GPCM_TWP(0xff)) 177 #define CONFIG_SYS_FPGA_FTIM3 0x0 178 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 179 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 180 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 181 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 182 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 183 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 184 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 185 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 186 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT 187 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR 188 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK 189 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR 190 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 191 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 192 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 193 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 194 195 /* 196 * Serial Port 197 */ 198 #ifdef CONFIG_LPUART 199 #define CONFIG_LPUART_32B_REG 200 #else 201 #define CONFIG_SYS_NS16550_SERIAL 202 #ifndef CONFIG_DM_SERIAL 203 #define CONFIG_SYS_NS16550_REG_SIZE 1 204 #endif 205 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 206 #endif 207 208 /* 209 * I2C 210 */ 211 #if !CONFIG_IS_ENABLED(DM_I2C) 212 #define CONFIG_SYS_I2C 213 #else 214 #define CONFIG_I2C_SET_DEFAULT_BUS_NUM 215 #define CONFIG_I2C_DEFAULT_BUS_NUMBER 0 216 #endif 217 #define CONFIG_SYS_I2C_MXC 218 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 219 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 220 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 221 222 /* GPIO */ 223 #ifdef CONFIG_DM_GPIO 224 #ifndef CONFIG_MPC8XXX_GPIO 225 #define CONFIG_MPC8XXX_GPIO 226 #endif 227 #endif 228 229 /* EEPROM */ 230 #define CONFIG_ID_EEPROM 231 #define CONFIG_SYS_I2C_EEPROM_NXID 232 #define CONFIG_SYS_EEPROM_BUS_NUM 1 233 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 234 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 235 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 236 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 237 238 /* 239 * MMC 240 */ 241 242 /* 243 * Video 244 */ 245 #ifdef CONFIG_VIDEO_FSL_DCU_FB 246 #define CONFIG_VIDEO_LOGO 247 #define CONFIG_VIDEO_BMP_LOGO 248 249 #define CONFIG_FSL_DCU_SII9022A 250 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 251 #define CONFIG_SYS_I2C_DVI_ADDR 0x39 252 #endif 253 254 /* 255 * eTSEC 256 */ 257 258 #ifdef CONFIG_TSEC_ENET 259 #define CONFIG_ETHPRIME "ethernet@2d10000" 260 #endif 261 262 /* PCIe */ 263 #define CONFIG_PCIE1 /* PCIE controller 1 */ 264 #define CONFIG_PCIE2 /* PCIE controller 2 */ 265 266 #ifdef CONFIG_PCI 267 #define CONFIG_PCI_SCAN_SHOW 268 #endif 269 270 #define CONFIG_CMDLINE_TAG 271 272 #define CONFIG_PEN_ADDR_BIG_ENDIAN 273 #define CONFIG_LAYERSCAPE_NS_ACCESS 274 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 275 #define COUNTER_FREQUENCY 12500000 276 277 #define CONFIG_HWCONFIG 278 #define HWCONFIG_BUFFER_SIZE 256 279 280 #define CONFIG_FSL_DEVICE_DISABLE 281 282 #define BOOT_TARGET_DEVICES(func) \ 283 func(MMC, mmc, 0) \ 284 func(USB, usb, 0) \ 285 func(DHCP, dhcp, na) 286 #include <config_distro_bootcmd.h> 287 288 #ifdef CONFIG_LPUART 289 #define CONFIG_EXTRA_ENV_SETTINGS \ 290 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \ 291 "cma=64M@0x0-0xb0000000\0" \ 292 "initrd_high=0xffffffff\0" \ 293 "fdt_addr=0x64f00000\0" \ 294 "kernel_addr=0x65000000\0" \ 295 "scriptaddr=0x80000000\0" \ 296 "scripthdraddr=0x80080000\0" \ 297 "fdtheader_addr_r=0x80100000\0" \ 298 "kernelheader_addr_r=0x80200000\0" \ 299 "kernel_addr_r=0x81000000\0" \ 300 "fdt_addr_r=0x90000000\0" \ 301 "ramdisk_addr_r=0xa0000000\0" \ 302 "load_addr=0xa0000000\0" \ 303 "kernel_size=0x2800000\0" \ 304 "kernel_addr_sd=0x8000\0" \ 305 "kernel_size_sd=0x14000\0" \ 306 "othbootargs=cma=64M@0x0-0xb0000000\0" \ 307 BOOTENV \ 308 "boot_scripts=ls1021atwr_boot.scr\0" \ 309 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ 310 "scan_dev_for_boot_part=" \ 311 "part list ${devtype} ${devnum} devplist; " \ 312 "env exists devplist || setenv devplist 1; " \ 313 "for distro_bootpart in ${devplist}; do " \ 314 "if fstype ${devtype} " \ 315 "${devnum}:${distro_bootpart} " \ 316 "bootfstype; then " \ 317 "run scan_dev_for_boot; " \ 318 "fi; " \ 319 "done\0" \ 320 "scan_dev_for_boot=" \ 321 "echo Scanning ${devtype} " \ 322 "${devnum}:${distro_bootpart}...; " \ 323 "for prefix in ${boot_prefixes}; do " \ 324 "run scan_dev_for_scripts; " \ 325 "done;" \ 326 "\0" \ 327 "boot_a_script=" \ 328 "load ${devtype} ${devnum}:${distro_bootpart} " \ 329 "${scriptaddr} ${prefix}${script}; " \ 330 "env exists secureboot && load ${devtype} " \ 331 "${devnum}:${distro_bootpart} " \ 332 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ 333 "env exists secureboot " \ 334 "&& esbc_validate ${scripthdraddr};" \ 335 "source ${scriptaddr}\0" \ 336 "installer=load mmc 0:2 $load_addr " \ 337 "/flex_installer_arm32.itb; " \ 338 "bootm $load_addr#ls1021atwr\0" \ 339 "qspi_bootcmd=echo Trying load from qspi..;" \ 340 "sf probe && sf read $load_addr " \ 341 "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \ 342 "nor_bootcmd=echo Trying load from nor..;" \ 343 "cp.b $kernel_addr $load_addr " \ 344 "$kernel_size && bootm $load_addr#$board\0" 345 #else 346 #define CONFIG_EXTRA_ENV_SETTINGS \ 347 "bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \ 348 "cma=64M@0x0-0xb0000000\0" \ 349 "initrd_high=0xffffffff\0" \ 350 "fdt_addr=0x64f00000\0" \ 351 "kernel_addr=0x61000000\0" \ 352 "kernelheader_addr=0x60800000\0" \ 353 "scriptaddr=0x80000000\0" \ 354 "scripthdraddr=0x80080000\0" \ 355 "fdtheader_addr_r=0x80100000\0" \ 356 "kernelheader_addr_r=0x80200000\0" \ 357 "kernel_addr_r=0x81000000\0" \ 358 "kernelheader_size=0x40000\0" \ 359 "fdt_addr_r=0x90000000\0" \ 360 "ramdisk_addr_r=0xa0000000\0" \ 361 "load_addr=0xa0000000\0" \ 362 "kernel_size=0x2800000\0" \ 363 "kernel_addr_sd=0x8000\0" \ 364 "kernel_size_sd=0x14000\0" \ 365 "kernelhdr_addr_sd=0x4000\0" \ 366 "kernelhdr_size_sd=0x10\0" \ 367 "othbootargs=cma=64M@0x0-0xb0000000\0" \ 368 BOOTENV \ 369 "boot_scripts=ls1021atwr_boot.scr\0" \ 370 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ 371 "scan_dev_for_boot_part=" \ 372 "part list ${devtype} ${devnum} devplist; " \ 373 "env exists devplist || setenv devplist 1; " \ 374 "for distro_bootpart in ${devplist}; do " \ 375 "if fstype ${devtype} " \ 376 "${devnum}:${distro_bootpart} " \ 377 "bootfstype; then " \ 378 "run scan_dev_for_boot; " \ 379 "fi; " \ 380 "done\0" \ 381 "scan_dev_for_boot=" \ 382 "echo Scanning ${devtype} " \ 383 "${devnum}:${distro_bootpart}...; " \ 384 "for prefix in ${boot_prefixes}; do " \ 385 "run scan_dev_for_scripts; " \ 386 "done;" \ 387 "\0" \ 388 "boot_a_script=" \ 389 "load ${devtype} ${devnum}:${distro_bootpart} " \ 390 "${scriptaddr} ${prefix}${script}; " \ 391 "env exists secureboot && load ${devtype} " \ 392 "${devnum}:${distro_bootpart} " \ 393 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 394 "&& esbc_validate ${scripthdraddr};" \ 395 "source ${scriptaddr}\0" \ 396 "qspi_bootcmd=echo Trying load from qspi..;" \ 397 "sf probe && sf read $load_addr " \ 398 "$kernel_addr $kernel_size; env exists secureboot " \ 399 "&& sf read $kernelheader_addr_r $kernelheader_addr " \ 400 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 401 "bootm $load_addr#$board\0" \ 402 "nor_bootcmd=echo Trying load from nor..;" \ 403 "cp.b $kernel_addr $load_addr " \ 404 "$kernel_size; env exists secureboot " \ 405 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ 406 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 407 "bootm $load_addr#$board\0" \ 408 "sd_bootcmd=echo Trying load from SD ..;" \ 409 "mmcinfo && mmc read $load_addr " \ 410 "$kernel_addr_sd $kernel_size_sd && " \ 411 "env exists secureboot && mmc read $kernelheader_addr_r " \ 412 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 413 " && esbc_validate ${kernelheader_addr_r};" \ 414 "bootm $load_addr#$board\0" 415 #endif 416 417 #undef CONFIG_BOOTCOMMAND 418 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 419 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ 420 "env exists secureboot && esbc_halt" 421 #elif defined(CONFIG_SD_BOOT) 422 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ 423 "env exists secureboot && esbc_halt;" 424 #else 425 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;" \ 426 "env exists secureboot && esbc_halt;" 427 #endif 428 429 /* 430 * Miscellaneous configurable options 431 */ 432 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) 433 434 #define CONFIG_SYS_LOAD_ADDR 0x82000000 435 436 #define CONFIG_LS102XA_STREAM_ID 437 438 #define CONFIG_SYS_INIT_SP_OFFSET \ 439 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 440 #define CONFIG_SYS_INIT_SP_ADDR \ 441 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 442 443 #ifdef CONFIG_SPL_BUILD 444 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 445 #else 446 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 447 #endif 448 449 #define CONFIG_SYS_QE_FW_ADDR 0x60940000 450 451 /* 452 * Environment 453 */ 454 455 #include <asm/fsl_secure_boot.h> 456 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 457 458 #endif 459