1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #define MXC_CPU_MX23 0x23 7 #define MXC_CPU_MX25 0x25 8 #define MXC_CPU_MX27 0x27 9 #define MXC_CPU_MX28 0x28 10 #define MXC_CPU_MX31 0x31 11 #define MXC_CPU_MX35 0x35 12 #define MXC_CPU_MX51 0x51 13 #define MXC_CPU_MX53 0x53 14 #define MXC_CPU_MX6SL 0x60 15 #define MXC_CPU_MX6DL 0x61 16 #define MXC_CPU_MX6SX 0x62 17 #define MXC_CPU_MX6Q 0x63 18 #define MXC_CPU_MX6UL 0x64 19 #define MXC_CPU_MX6ULL 0x65 20 #define MXC_CPU_MX6ULZ 0x6B 21 #define MXC_CPU_MX6SOLO 0x66 /* dummy */ 22 #define MXC_CPU_MX6SLL 0x67 23 #define MXC_CPU_MX6D 0x6A 24 #define MXC_CPU_MX6DP 0x68 25 #define MXC_CPU_MX6QP 0x69 26 #define MXC_CPU_MX7S 0x71 /* dummy ID */ 27 #define MXC_CPU_MX7D 0x72 28 #define MXC_CPU_IMX8MQ 0x82 29 #define MXC_CPU_IMX8MD 0x83 /* dummy ID */ 30 #define MXC_CPU_IMX8MQL 0x84 /* dummy ID */ 31 #define MXC_CPU_IMX8MM 0x85 /* dummy ID */ 32 #define MXC_CPU_IMX8MML 0x86 /* dummy ID */ 33 #define MXC_CPU_IMX8MMD 0x87 /* dummy ID */ 34 #define MXC_CPU_IMX8MMDL 0x88 /* dummy ID */ 35 #define MXC_CPU_IMX8MMS 0x89 /* dummy ID */ 36 #define MXC_CPU_IMX8MMSL 0x8a /* dummy ID */ 37 #define MXC_CPU_IMX8MN 0x8b /* dummy ID */ 38 #define MXC_CPU_IMX8MND 0x8c /* dummy ID */ 39 #define MXC_CPU_IMX8MNS 0x8d /* dummy ID */ 40 #define MXC_CPU_IMX8MNL 0x8e /* dummy ID */ 41 #define MXC_CPU_IMX8MNDL 0x8f /* dummy ID */ 42 #define MXC_CPU_IMX8MNSL 0x181 /* dummy ID */ 43 #define MXC_CPU_IMX8MNUQ 0x182 /* dummy ID */ 44 #define MXC_CPU_IMX8MNUD 0x183 /* dummy ID */ 45 #define MXC_CPU_IMX8MNUS 0x184 /* dummy ID */ 46 #define MXC_CPU_IMX8MP 0x185/* dummy ID */ 47 #define MXC_CPU_IMX8MP6 0x186 /* dummy ID */ 48 #define MXC_CPU_IMX8MPL 0x187 /* dummy ID */ 49 #define MXC_CPU_IMX8MPD 0x188 /* dummy ID */ 50 #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ 51 #define MXC_CPU_IMX8QM 0x91 /* dummy ID */ 52 #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ 53 #define MXC_CPU_IMXRT1020 0xB4 /* dummy ID */ 54 #define MXC_CPU_IMXRT1050 0xB6 /* dummy ID */ 55 #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ 56 #define MXC_CPU_VF610 0xF6 /* dummy ID */ 57 58 #define MXC_SOC_MX6 0x60 59 #define MXC_SOC_MX7 0x70 60 #define MXC_SOC_IMX8M 0x80 61 #define MXC_SOC_IMX8 0x90 /* dummy */ 62 #define MXC_SOC_IMXRT 0xB0 /* dummy */ 63 #define MXC_SOC_MX7ULP 0xE0 /* dummy */ 64 65 #define CHIP_REV_1_0 0x10 66 #define CHIP_REV_1_1 0x11 67 #define CHIP_REV_1_2 0x12 68 #define CHIP_REV_1_3 0x13 69 #define CHIP_REV_1_5 0x15 70 #define CHIP_REV_2_0 0x20 71 #define CHIP_REV_2_1 0x21 72 #define CHIP_REV_2_2 0x22 73 #define CHIP_REV_2_5 0x25 74 #define CHIP_REV_3_0 0x30 75 76 #define CHIP_REV_A 0x0 77 #define CHIP_REV_B 0x1 78 #define CHIP_REV_C 0x2 79 80 #define BOARD_REV_1_0 0x0 81 #define BOARD_REV_2_0 0x1 82 #define BOARD_VER_OFFSET 0x8 83 84 #define CS0_128 0 85 #define CS0_64M_CS1_64M 1 86 #define CS0_64M_CS1_32M_CS2_32M 2 87 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3 88 89 u32 get_imx_reset_cause(void); 90 ulong get_systemPLLCLK(void); 91 ulong get_FCLK(void); 92 ulong get_HCLK(void); 93 ulong get_BCLK(void); 94 ulong get_PERCLK1(void); 95 ulong get_PERCLK2(void); 96 ulong get_PERCLK3(void); 97