1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 *
4 * Common board functions for OMAP3 based boards.
5 *
6 * (C) Copyright 2004-2008
7 * Texas Instruments, <www.ti.com>
8 *
9 * Author :
10 * Sunil Kumar <sunilsaini05@gmail.com>
11 * Shashi Ranjan <shashiranjanmca05@gmail.com>
12 *
13 * Derived from Beagle Board and 3430 SDP code by
14 * Richard Woodruff <r-woodruff2@ti.com>
15 * Syed Mohammed Khasim <khasim@ti.com>
16 *
17 */
18 #include <common.h>
19 #include <command.h>
20 #include <dm.h>
21 #include <init.h>
22 #include <spl.h>
23 #include <asm/io.h>
24 #include <asm/arch/sys_proto.h>
25 #include <asm/arch/mem.h>
26 #include <asm/cache.h>
27 #include <asm/armv7.h>
28 #include <asm/gpio.h>
29 #include <asm/omap_common.h>
30 #include <linux/compiler.h>
31
32 /* Declarations */
33 extern omap3_sysinfo sysinfo;
34 #ifndef CONFIG_SYS_L2CACHE_OFF
35 static void omap3_invalidate_l2_cache_secure(void);
36 #endif
37
38 #if CONFIG_IS_ENABLED(DM_GPIO)
39 #if !CONFIG_IS_ENABLED(OF_CONTROL)
40 /* Manually initialize GPIO banks when OF_CONTROL doesn't */
41 static const struct omap_gpio_plat omap34xx_gpio[] = {
42 { 0, OMAP34XX_GPIO1_BASE },
43 { 1, OMAP34XX_GPIO2_BASE },
44 { 2, OMAP34XX_GPIO3_BASE },
45 { 3, OMAP34XX_GPIO4_BASE },
46 { 4, OMAP34XX_GPIO5_BASE },
47 { 5, OMAP34XX_GPIO6_BASE },
48 };
49
50 U_BOOT_DRVINFOS(omap34xx_gpios) = {
51 { "gpio_omap", &omap34xx_gpio[0] },
52 { "gpio_omap", &omap34xx_gpio[1] },
53 { "gpio_omap", &omap34xx_gpio[2] },
54 { "gpio_omap", &omap34xx_gpio[3] },
55 { "gpio_omap", &omap34xx_gpio[4] },
56 { "gpio_omap", &omap34xx_gpio[5] },
57 };
58 #endif
59 #else
60
61 static const struct gpio_bank gpio_bank_34xx[6] = {
62 { (void *)OMAP34XX_GPIO1_BASE },
63 { (void *)OMAP34XX_GPIO2_BASE },
64 { (void *)OMAP34XX_GPIO3_BASE },
65 { (void *)OMAP34XX_GPIO4_BASE },
66 { (void *)OMAP34XX_GPIO5_BASE },
67 { (void *)OMAP34XX_GPIO6_BASE },
68 };
69
70 const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
71
72 #endif
73
74 /******************************************************************************
75 * Routine: secure_unlock
76 * Description: Setup security registers for access
77 * (GP Device only)
78 *****************************************************************************/
secure_unlock_mem(void)79 void secure_unlock_mem(void)
80 {
81 struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
82 struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
83 struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
84 struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
85 struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
86
87 /* Protection Module Register Target APE (PM_RT) */
88 writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
89 writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
90 writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
91 writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
92
93 writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
94 writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
95 writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
96
97 writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
98 writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
99 writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
100 writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
101
102 /* IVA Changes */
103 writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
104 writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
105 writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
106
107 /* SDRC region 0 public */
108 writel(UNLOCK_1, &sms_base->rg_att0);
109 }
110
111 /******************************************************************************
112 * Routine: secureworld_exit()
113 * Description: If chip is EMU and boot type is external
114 * configure secure registers and exit secure world
115 * general use.
116 *****************************************************************************/
secureworld_exit(void)117 void secureworld_exit(void)
118 {
119 unsigned long i;
120
121 /* configure non-secure access control register */
122 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
123 /* enabling co-processor CP10 and CP11 accesses in NS world */
124 __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
125 /*
126 * allow allocation of locked TLBs and L2 lines in NS world
127 * allow use of PLE registers in NS world also
128 */
129 __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
130 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
131
132 /* Enable ASA in ACR register */
133 __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
134 __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
135 __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
136
137 /* Exiting secure world */
138 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
139 __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
140 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
141 }
142
143 /******************************************************************************
144 * Routine: try_unlock_sram()
145 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
146 * general use.
147 *****************************************************************************/
try_unlock_memory(void)148 void try_unlock_memory(void)
149 {
150 int mode;
151 int in_sdram = is_running_in_sdram();
152
153 /*
154 * if GP device unlock device SRAM for general use
155 * secure code breaks for Secure/Emulation device - HS/E/T
156 */
157 mode = get_device_type();
158 if (mode == GP_DEVICE)
159 secure_unlock_mem();
160
161 /*
162 * If device is EMU and boot is XIP external booting
163 * Unlock firewalls and disable L2 and put chip
164 * out of secure world
165 *
166 * Assuming memories are unlocked by the demon who put us in SDRAM
167 */
168 if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
169 && (!in_sdram)) {
170 secure_unlock_mem();
171 secureworld_exit();
172 }
173
174 return;
175 }
176
early_system_init(void)177 void early_system_init(void)
178 {
179 hw_data_init();
180 }
181
182 #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
183 !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
184 /******************************************************************************
185 * Routine: s_init
186 * Description: Does early system init of muxing and clocks.
187 * - Called path is with SRAM stack.
188 *****************************************************************************/
s_init(void)189 void s_init(void)
190 {
191 watchdog_init();
192 early_system_init();
193
194 try_unlock_memory();
195
196 #ifndef CONFIG_SYS_L2CACHE_OFF
197 /* Invalidate L2-cache from secure mode */
198 omap3_invalidate_l2_cache_secure();
199 #endif
200
201 set_muxconf_regs();
202 sdelay(100);
203
204 prcm_init();
205
206 per_clocks_enable();
207
208 #ifdef CONFIG_USB_EHCI_OMAP
209 ehci_clocks_enable();
210 #endif
211 }
212 #endif
213
214 #ifdef CONFIG_SPL_BUILD
board_init_f(ulong dummy)215 void board_init_f(ulong dummy)
216 {
217 early_system_init();
218 mem_init();
219 /*
220 * Save the boot parameters passed from romcode.
221 * We cannot delay the saving further than this,
222 * to prevent overwrites.
223 */
224 save_omap_boot_params();
225 }
226 #endif
227
228 /*
229 * Routine: misc_init_r
230 * Description: A basic misc_init_r that just displays the die ID
231 */
misc_init_r(void)232 int __weak misc_init_r(void)
233 {
234 omap_die_id_display();
235
236 return 0;
237 }
238
239 /******************************************************************************
240 * Routine: wait_for_command_complete
241 * Description: Wait for posting to finish on watchdog
242 *****************************************************************************/
wait_for_command_complete(struct watchdog * wd_base)243 static void wait_for_command_complete(struct watchdog *wd_base)
244 {
245 int pending = 1;
246 do {
247 pending = readl(&wd_base->wwps);
248 } while (pending);
249 }
250
251 /******************************************************************************
252 * Routine: watchdog_init
253 * Description: Shut down watch dogs
254 *****************************************************************************/
watchdog_init(void)255 void watchdog_init(void)
256 {
257 struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
258 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
259
260 /*
261 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
262 * either taken care of by ROM (HS/EMU) or not accessible (GP).
263 * We need to take care of WD2-MPU or take a PRCM reset. WD3
264 * should not be running and does not generate a PRCM reset.
265 */
266
267 setbits_le32(&prcm_base->fclken_wkup, 0x20);
268 setbits_le32(&prcm_base->iclken_wkup, 0x20);
269 wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
270
271 writel(WD_UNLOCK1, &wd2_base->wspr);
272 wait_for_command_complete(wd2_base);
273 writel(WD_UNLOCK2, &wd2_base->wspr);
274 }
275
276 /******************************************************************************
277 * Dummy function to handle errors for EABI incompatibility
278 *****************************************************************************/
abort(void)279 void abort(void)
280 {
281 }
282
283 #if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
284 /******************************************************************************
285 * OMAP3 specific command to switch between NAND HW and SW ecc
286 *****************************************************************************/
do_switch_ecc(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])287 static int do_switch_ecc(struct cmd_tbl *cmdtp, int flag, int argc,
288 char *const argv[])
289 {
290 int hw, strength = 1;
291
292 if (argc < 2 || argc > 3)
293 goto usage;
294
295 if (strncmp(argv[1], "hw", 2) == 0) {
296 hw = 1;
297 if (argc == 3) {
298 if (strncmp(argv[2], "bch8", 4) == 0)
299 strength = 8;
300 else if (strncmp(argv[2], "bch16", 5) == 0)
301 strength = 16;
302 else if (strncmp(argv[2], "hamming", 7) != 0)
303 goto usage;
304 }
305 } else if (strncmp(argv[1], "sw", 2) == 0) {
306 hw = 0;
307 if (argc == 3) {
308 if (strncmp(argv[2], "bch8", 4) == 0)
309 strength = 8;
310 else if (strncmp(argv[2], "hamming", 7) != 0)
311 goto usage;
312 }
313 } else {
314 goto usage;
315 }
316
317 return -omap_nand_switch_ecc(hw, strength);
318
319 usage:
320 printf ("Usage: nandecc %s\n", cmdtp->usage);
321 return 1;
322 }
323
324 U_BOOT_CMD(
325 nandecc, 3, 1, do_switch_ecc,
326 "switch OMAP3 NAND ECC calculation algorithm",
327 "hw [hamming|bch8|bch16] - Switch between NAND hardware 1-bit hamming"
328 " and 8-bit/16-bit BCH\n"
329 " ecc calculation (second parameter may"
330 " be omitted).\n"
331 "nandecc sw - Switch to NAND software ecc algorithm."
332 );
333
334 #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
335
336 #ifdef CONFIG_DISPLAY_BOARDINFO
337 /**
338 * Print board information
339 */
checkboard(void)340 int checkboard (void)
341 {
342 char *mem_s ;
343
344 if (is_mem_sdr())
345 mem_s = "mSDR";
346 else
347 mem_s = "LPDDR";
348
349 printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
350 sysinfo.nand_string);
351
352 return 0;
353 }
354 #endif /* CONFIG_DISPLAY_BOARDINFO */
355
omap3_emu_romcode_call(u32 service_id,u32 * parameters)356 static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
357 {
358 u32 i, num_params = *parameters;
359 u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
360
361 /*
362 * copy the parameters to an un-cached area to avoid coherency
363 * issues
364 */
365 for (i = 0; i < num_params; i++) {
366 __raw_writel(*parameters, sram_scratch_space);
367 parameters++;
368 sram_scratch_space++;
369 }
370
371 /* Now make the PPA call */
372 do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
373 }
374
omap3_set_aux_cr_secure(u32 acr)375 void __weak omap3_set_aux_cr_secure(u32 acr)
376 {
377 struct emu_hal_params emu_romcode_params;
378
379 emu_romcode_params.num_params = 1;
380 emu_romcode_params.param1 = acr;
381 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
382 (u32 *)&emu_romcode_params);
383 }
384
v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl,u32 cpu_midr,u32 cpu_rev_comb,u32 cpu_variant,u32 cpu_rev)385 void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
386 u32 cpu_rev_comb, u32 cpu_variant,
387 u32 cpu_rev)
388 {
389 if (get_device_type() == GP_DEVICE)
390 omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_L2ACR, l2auxctrl);
391
392 /* L2 Cache Auxiliary Control Register is not banked */
393 }
394
v7_arch_cp15_set_acr(u32 acr,u32 cpu_midr,u32 cpu_rev_comb,u32 cpu_variant,u32 cpu_rev)395 void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
396 u32 cpu_variant, u32 cpu_rev)
397 {
398 /* Write ACR - affects secure banked bits */
399 if (get_device_type() == GP_DEVICE)
400 omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
401 else
402 omap3_set_aux_cr_secure(acr);
403
404 /* Write ACR - affects non-secure banked bits - some erratas need it */
405 asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
406 }
407
408
409 #ifndef CONFIG_SYS_L2CACHE_OFF
omap3_update_aux_cr(u32 set_bits,u32 clear_bits)410 static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
411 {
412 u32 acr;
413
414 /* Read ACR */
415 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
416 acr &= ~clear_bits;
417 acr |= set_bits;
418 v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
419
420 }
421
422 /* Invalidate the entire L2 cache from secure mode */
omap3_invalidate_l2_cache_secure(void)423 static void omap3_invalidate_l2_cache_secure(void)
424 {
425 if (get_device_type() == GP_DEVICE) {
426 omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
427 } else {
428 struct emu_hal_params emu_romcode_params;
429 emu_romcode_params.num_params = 1;
430 emu_romcode_params.param1 = 0;
431 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
432 (u32 *)&emu_romcode_params);
433 }
434 }
435
v7_outer_cache_enable(void)436 void v7_outer_cache_enable(void)
437 {
438
439 /*
440 * Set L2EN
441 * On some revisions L2EN bit is banked on some revisions it's not
442 * No harm in setting both banked bits(in fact this is required
443 * by an erratum)
444 */
445 omap3_update_aux_cr(0x2, 0);
446 }
447
omap3_outer_cache_disable(void)448 void omap3_outer_cache_disable(void)
449 {
450 /*
451 * Clear L2EN
452 * On some revisions L2EN bit is banked on some revisions it's not
453 * No harm in clearing both banked bits(in fact this is required
454 * by an erratum)
455 */
456 omap3_update_aux_cr(0, 0x2);
457 }
458 #endif /* !CONFIG_SYS_L2CACHE_OFF */
459