1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Cortina SPI-FLASH Controller
4 *
5 * Copyright (C) 2020 Cortina Access Inc. All Rights Reserved.
6 *
7 * Author: PengPeng Chen <pengpeng.chen@cortina-access.com>
8 */
9
10 #include <common.h>
11 #include <malloc.h>
12 #include <clk.h>
13 #include <dm.h>
14 #include <errno.h>
15 #include <fdtdec.h>
16 #include <linux/compat.h>
17 #include <linux/io.h>
18 #include <linux/iopoll.h>
19 #include <linux/ioport.h>
20 #include <linux/sizes.h>
21 #include <spi.h>
22 #include <spi-mem.h>
23 #include <reset.h>
24 #include <asm/global_data.h>
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 struct ca_sflash_regs {
29 u32 idr; /* 0x00:Flash word ID Register */
30 u32 tc; /* 0x04:Flash Timeout Counter Register */
31 u32 sr; /* 0x08:Flash Status Register */
32 u32 tr; /* 0x0C:Flash Type Register */
33 u32 asr; /* 0x10:Flash ACCESS START/BUSY Register */
34 u32 isr; /* 0x14:Flash Interrupt Status Register */
35 u32 imr; /* 0x18:Flash Interrupt Mask Register */
36 u32 fcr; /* 0x1C:NAND Flash FIFO Control Register */
37 u32 ffsr; /* 0x20:Flash FIFO Status Register */
38 u32 ffar; /* 0x24:Flash FIFO ADDRESS Register */
39 u32 ffmar; /* 0x28:Flash FIFO MATCHING ADDRESS Register */
40 u32 ffdr; /* 0x2C:Flash FIFO Data Register */
41 u32 ar; /* 0x30:Serial Flash Access Register */
42 u32 ear; /* 0x34:Serial Flash Extend Access Register */
43 u32 adr; /* 0x38:Serial Flash ADdress Register */
44 u32 dr; /* 0x3C:Serial Flash Data Register */
45 u32 tmr; /* 0x40:Serial Flash Timing Register */
46 };
47
48 /*
49 * FLASH_TYPE
50 */
51 #define CA_FLASH_TR_PIN BIT(15)
52 #define CA_FLASH_TR_TYPE_MSK GENMASK(14, 12)
53 #define CA_FLASH_TR_TYPE(tp) (((tp) << 12) & CA_FLASH_TR_TYPE_MSK)
54 #define CA_FLASH_TR_WIDTH BIT(11)
55 #define CA_FLASH_TR_SIZE_MSK GENMASK(10, 9)
56 #define CA_FLASH_TR_SIZE(sz) (((sz) << 9) & CA_FLASH_TR_SIZE_MSK)
57
58 /*
59 * FLASH_FLASH_ACCESS_START
60 */
61 #define CA_FLASH_ASR_IND_START_EN BIT(1)
62 #define CA_FLASH_ASR_DMA_START_EN BIT(3)
63 #define CA_FLASH_ASR_WR_ACCESS_EN BIT(9)
64
65 /*
66 * FLASH_FLASH_INTERRUPT
67 */
68 #define CA_FLASH_ISR_REG_IRQ BIT(1)
69 #define CA_FLASH_ISR_FIFO_IRQ BIT(2)
70
71 /*
72 * FLASH_SF_ACCESS
73 */
74 #define CA_SF_AR_OP_MSK GENMASK(7, 0)
75 #define CA_SF_AR_OP(op) ((op) << 0 & CA_SF_AR_OP_MSK)
76 #define CA_SF_AR_ACCODE_MSK GENMASK(11, 8)
77 #define CA_SF_AR_ACCODE(ac) (((ac) << 8) & CA_SF_AR_ACCODE_MSK)
78 #define CA_SF_AR_FORCE_TERM BIT(12)
79 #define CA_SF_AR_FORCE_BURST BIT(13)
80 #define CA_SF_AR_AUTO_MODE_EN BIT(15)
81 #define CA_SF_AR_CHIP_EN_ALT BIT(16)
82 #define CA_SF_AR_HI_SPEED_RD BIT(17)
83 #define CA_SF_AR_MIO_INF_DC BIT(24)
84 #define CA_SF_AR_MIO_INF_AC BIT(25)
85 #define CA_SF_AR_MIO_INF_CC BIT(26)
86 #define CA_SF_AR_DDR_MSK GENMASK(29, 28)
87 #define CA_SF_AR_DDR(ddr) (((ddr) << 28) & CA_SF_AR_DDR_MSK)
88 #define CA_SF_AR_MIO_INF_MSK GENMASK(31, 30)
89 #define CA_SF_AR_MIO_INF(io) (((io) << 30) & CA_SF_AR_MIO_INF_MSK)
90
91 /*
92 * FLASH_SF_EXT_ACCESS
93 */
94 #define CA_SF_EAR_OP_MSK GENMASK(7, 0)
95 #define CA_SF_EAR_OP(op) (((op) << 0) & CA_SF_EAR_OP_MSK)
96 #define CA_SF_EAR_DATA_CNT_MSK GENMASK(20, 8)
97 #define CA_SF_EAR_DATA_CNT(cnt) (((cnt) << 8) & CA_SF_EAR_DATA_CNT_MSK)
98 #define CA_SF_EAR_DATA_CNT_MAX (4096)
99 #define CA_SF_EAR_ADDR_CNT_MSK GENMASK(23, 21)
100 #define CA_SF_EAR_ADDR_CNT(cnt) (((cnt) << 21) & CA_SF_EAR_ADDR_CNT_MSK)
101 #define CA_SF_EAR_ADDR_CNT_MAX (5)
102 #define CA_SF_EAR_DUMY_CNT_MSK GENMASK(29, 24)
103 #define CA_SF_EAR_DUMY_CNT(cnt) (((cnt) << 24) & CA_SF_EAR_DUMY_CNT_MSK)
104 #define CA_SF_EAR_DUMY_CNT_MAX (32)
105 #define CA_SF_EAR_DRD_CMD_EN BIT(31)
106
107 /*
108 * FLASH_SF_ADDRESS
109 */
110 #define CA_SF_ADR_REG_MSK GENMASK(31, 0)
111 #define CA_SF_ADR_REG(addr) (((addr) << 0) & CA_SF_ADR_REG_MSK)
112
113 /*
114 * FLASH_SF_DATA
115 */
116 #define CA_SF_DR_REG_MSK GENMASK(31, 0)
117 #define CA_SF_DR_REG(addr) (((addr) << 0) & CA_SF_DR_REG_MSK)
118
119 /*
120 * FLASH_SF_TIMING
121 */
122 #define CA_SF_TMR_IDLE_MSK GENMASK(7, 0)
123 #define CA_SF_TMR_IDLE(idle) (((idle) << 0) & CA_SF_TMR_IDLE_MSK)
124 #define CA_SF_TMR_HOLD_MSK GENMASK(15, 8)
125 #define CA_SF_TMR_HOLD(hold) (((hold) << 8) & CA_SF_TMR_HOLD_MSK)
126 #define CA_SF_TMR_SETUP_MSK GENMASK(23, 16)
127 #define CA_SF_TMR_SETUP(setup) (((setup) << 16) & CA_SF_TMR_SETUP_MSK)
128 #define CA_SF_TMR_CLK_MSK GENMASK(26, 24)
129 #define CA_SF_TMR_CLK(clk) (((clk) << 24) & CA_SF_TMR_CLK_MSK)
130
131 #define CA_SFLASH_IND_WRITE 0
132 #define CA_SFLASH_IND_READ 1
133 #define CA_SFLASH_MEM_MAP 3
134 #define CA_SFLASH_FIFO_TIMEOUT_US 30000
135 #define CA_SFLASH_BUSY_TIMEOUT_US 40000
136
137 #define CA_SF_AC_OP 0x00
138 #define CA_SF_AC_OP_1_DATA 0x01
139 #define CA_SF_AC_OP_2_DATA 0x02
140 #define CA_SF_AC_OP_3_DATA 0x03
141 #define CA_SF_AC_OP_4_DATA 0x04
142 #define CA_SF_AC_OP_3_ADDR 0x05
143 #define CA_SF_AC_OP_4_ADDR (CA_SF_AC_OP_3_ADDR)
144 #define CA_SF_AC_OP_3_ADDR_1_DATA 0x06
145 #define CA_SF_AC_OP_4_ADDR_1_DATA (CA_SF_AC_OP_3_ADDR_1_DATA << 2)
146 #define CA_SF_AC_OP_3_ADDR_2_DATA 0x07
147 #define CA_SF_AC_OP_4_ADDR_2_DATA (CA_SF_AC_OP_3_ADDR_2_DATA << 2)
148 #define CA_SF_AC_OP_3_ADDR_3_DATA 0x08
149 #define CA_SF_AC_OP_4_ADDR_3_DATA (CA_SF_AC_OP_3_ADDR_3_DATA << 2)
150 #define CA_SF_AC_OP_3_ADDR_4_DATA 0x09
151 #define CA_SF_AC_OP_4_ADDR_4_DATA (CA_SF_AC_OP_3_ADDR_4_DATA << 2)
152 #define CA_SF_AC_OP_3_ADDR_X_1_DATA 0x0A
153 #define CA_SF_AC_OP_4_ADDR_X_1_DATA (CA_SF_AC_OP_3_ADDR_X_1_DATA << 2)
154 #define CA_SF_AC_OP_3_ADDR_X_2_DATA 0x0B
155 #define CA_SF_AC_OP_4_ADDR_X_2_DATA (CA_SF_AC_OP_3_ADDR_X_2_DATA << 2)
156 #define CA_SF_AC_OP_3_ADDR_X_3_DATA 0x0C
157 #define CA_SF_AC_OP_4_ADDR_X_3_DATA (CA_SF_AC_OP_3_ADDR_X_3_DATA << 2)
158 #define CA_SF_AC_OP_3_ADDR_X_4_DATA 0x0D
159 #define CA_SF_AC_OP_4_ADDR_X_4_DATA (CA_SF_AC_OP_3_ADDR_X_4_DATA << 2)
160 #define CA_SF_AC_OP_3_ADDR_4X_1_DATA 0x0E
161 #define CA_SF_AC_OP_4_ADDR_4X_1_DATA (CA_SF_AC_OP_3_ADDR_4X_1_DATA << 2)
162 #define CA_SF_AC_OP_EXTEND 0x0F
163
164 #define CA_SF_ACCESS_MIO_SINGLE 0
165 #define CA_SF_ACCESS_MIO_DUAL 1
166 #define CA_SF_ACCESS_MIO_QUARD 2
167
168 enum access_type {
169 RD_ACCESS,
170 WR_ACCESS,
171 };
172
173 struct ca_sflash_priv {
174 struct ca_sflash_regs *regs;
175 u8 rx_width;
176 u8 tx_width;
177 };
178
179 /*
180 * This function doesn't do anything except help with debugging
181 */
ca_sflash_claim_bus(struct udevice * dev)182 static int ca_sflash_claim_bus(struct udevice *dev)
183 {
184 debug("%s:\n", __func__);
185 return 0;
186 }
187
ca_sflash_release_bus(struct udevice * dev)188 static int ca_sflash_release_bus(struct udevice *dev)
189 {
190 debug("%s:\n", __func__);
191 return 0;
192 }
193
ca_sflash_set_speed(struct udevice * dev,uint speed)194 static int ca_sflash_set_speed(struct udevice *dev, uint speed)
195 {
196 debug("%s:\n", __func__);
197 return 0;
198 }
199
ca_sflash_set_mode(struct udevice * dev,uint mode)200 static int ca_sflash_set_mode(struct udevice *dev, uint mode)
201 {
202 struct ca_sflash_priv *priv = dev_get_priv(dev);
203
204 if (mode & SPI_RX_QUAD)
205 priv->rx_width = 4;
206 else if (mode & SPI_RX_DUAL)
207 priv->rx_width = 2;
208 else
209 priv->rx_width = 1;
210
211 if (mode & SPI_TX_QUAD)
212 priv->tx_width = 4;
213 else if (mode & SPI_TX_DUAL)
214 priv->tx_width = 2;
215 else
216 priv->tx_width = 1;
217
218 debug("%s: mode=%d, rx_width=%d, tx_width=%d\n",
219 __func__, mode, priv->rx_width, priv->tx_width);
220
221 return 0;
222 }
223
_ca_sflash_wait_for_not_busy(struct ca_sflash_priv * priv)224 static int _ca_sflash_wait_for_not_busy(struct ca_sflash_priv *priv)
225 {
226 u32 asr;
227
228 if (readl_poll_timeout(&priv->regs->asr, asr,
229 !(asr & CA_FLASH_ASR_IND_START_EN),
230 CA_SFLASH_BUSY_TIMEOUT_US)) {
231 pr_err("busy timeout (stat:%#x)\n", asr);
232 return -1;
233 }
234
235 return 0;
236 }
237
_ca_sflash_wait_cmd(struct ca_sflash_priv * priv,enum access_type type)238 static int _ca_sflash_wait_cmd(struct ca_sflash_priv *priv,
239 enum access_type type)
240 {
241 if (type == WR_ACCESS) {
242 /* Enable write access and start the sflash indirect access */
243 clrsetbits_le32(&priv->regs->asr, GENMASK(31, 0),
244 CA_FLASH_ASR_WR_ACCESS_EN
245 | CA_FLASH_ASR_IND_START_EN);
246 } else if (type == RD_ACCESS) {
247 /* Start the sflash indirect access */
248 clrsetbits_le32(&priv->regs->asr, GENMASK(31, 0),
249 CA_FLASH_ASR_IND_START_EN);
250 } else {
251 printf("%s: !error access type.\n", __func__);
252 return -1;
253 }
254
255 /* Wait til the action(rd/wr) completed */
256 return _ca_sflash_wait_for_not_busy(priv);
257 }
258
_ca_sflash_read(struct ca_sflash_priv * priv,u8 * buf,unsigned int data_len)259 static int _ca_sflash_read(struct ca_sflash_priv *priv,
260 u8 *buf, unsigned int data_len)
261 {
262 u32 reg_data;
263 int len;
264
265 len = data_len;
266 while (len >= 4) {
267 if (_ca_sflash_wait_cmd(priv, RD_ACCESS))
268 return -1;
269 reg_data = readl(&priv->regs->dr);
270 *buf++ = reg_data & 0xFF;
271 *buf++ = (reg_data >> 8) & 0xFF;
272 *buf++ = (reg_data >> 16) & 0xFF;
273 *buf++ = (reg_data >> 24) & 0xFF;
274 len -= 4;
275 debug("%s: reg_data=%#08x\n",
276 __func__, reg_data);
277 }
278
279 if (len > 0) {
280 if (_ca_sflash_wait_cmd(priv, RD_ACCESS))
281 return -1;
282 reg_data = readl(&priv->regs->dr);
283 debug("%s: reg_data=%#08x\n",
284 __func__, reg_data);
285 }
286
287 switch (len) {
288 case 3:
289 *buf++ = reg_data & 0xFF;
290 *buf++ = (reg_data >> 8) & 0xFF;
291 *buf++ = (reg_data >> 16) & 0xFF;
292 break;
293 case 2:
294 *buf++ = reg_data & 0xFF;
295 *buf++ = (reg_data >> 8) & 0xFF;
296 break;
297 case 1:
298 *buf++ = reg_data & 0xFF;
299 break;
300 case 0:
301 break;
302 default:
303 printf("%s: error data_length %d!\n", __func__, len);
304 }
305
306 return 0;
307 }
308
_ca_sflash_mio_set(struct ca_sflash_priv * priv,u8 width)309 static int _ca_sflash_mio_set(struct ca_sflash_priv *priv,
310 u8 width)
311 {
312 if (width == 4) {
313 setbits_le32(&priv->regs->ar,
314 CA_SF_AR_MIO_INF_DC
315 | CA_SF_AR_MIO_INF(CA_SF_ACCESS_MIO_QUARD)
316 | CA_SF_AR_FORCE_BURST);
317 } else if (width == 2) {
318 setbits_le32(&priv->regs->ar,
319 CA_SF_AR_MIO_INF_DC
320 | CA_SF_AR_MIO_INF(CA_SF_ACCESS_MIO_DUAL)
321 | CA_SF_AR_FORCE_BURST);
322 } else if (width == 1) {
323 setbits_le32(&priv->regs->ar,
324 CA_SF_AR_MIO_INF(CA_SF_ACCESS_MIO_SINGLE)
325 | CA_SF_AR_FORCE_BURST);
326 } else {
327 printf("%s: error rx/tx width %d!\n", __func__, width);
328 return -1;
329 }
330
331 return 0;
332 }
333
_ca_sflash_write(struct ca_sflash_priv * priv,u8 * buf,unsigned int data_len)334 static int _ca_sflash_write(struct ca_sflash_priv *priv,
335 u8 *buf, unsigned int data_len)
336 {
337 u32 reg_data;
338 int len;
339
340 len = data_len;
341 while (len > 0) {
342 reg_data = buf[0]
343 | (buf[1] << 8)
344 | (buf[2] << 16)
345 | (buf[3] << 24);
346
347 debug("%s: reg_data=%#08x\n",
348 __func__, reg_data);
349 /* Fill data */
350 clrsetbits_le32(&priv->regs->dr, GENMASK(31, 0), reg_data);
351
352 if (_ca_sflash_wait_cmd(priv, WR_ACCESS))
353 return -1;
354
355 len -= 4;
356 buf += 4;
357 }
358
359 return 0;
360 }
361
_ca_sflash_access_data(struct ca_sflash_priv * priv,struct spi_mem_op * op)362 static int _ca_sflash_access_data(struct ca_sflash_priv *priv,
363 struct spi_mem_op *op)
364 {
365 int total_cnt;
366 unsigned int len;
367 unsigned int data_cnt = op->data.nbytes;
368 u64 addr_offset = op->addr.val;
369 u8 addr_cnt = op->addr.nbytes;
370 u8 *data_buf = NULL;
371 u8 *buf = NULL;
372
373 if (op->data.dir == SPI_MEM_DATA_IN)
374 data_buf = (u8 *)op->data.buf.in;
375 else
376 data_buf = (u8 *)op->data.buf.out;
377
378 if (data_cnt > CA_SF_EAR_DATA_CNT_MAX)
379 buf = malloc(CA_SF_EAR_DATA_CNT_MAX);
380 else
381 buf = malloc(data_cnt);
382
383 total_cnt = data_cnt;
384 while (total_cnt > 0) {
385 /* Fill address */
386 if (addr_cnt > 0)
387 clrsetbits_le32(&priv->regs->adr,
388 GENMASK(31, 0), (u32)addr_offset);
389
390 if (total_cnt > CA_SF_EAR_DATA_CNT_MAX) {
391 len = CA_SF_EAR_DATA_CNT_MAX;
392 addr_offset += CA_SF_EAR_DATA_CNT_MAX;
393 /* Clear start bit before next bulk read */
394 clrbits_le32(&priv->regs->asr, GENMASK(31, 0));
395 } else {
396 len = total_cnt;
397 }
398
399 memset(buf, 0, len);
400 if (op->data.dir == SPI_MEM_DATA_IN) {
401 if (_ca_sflash_read(priv, buf, len))
402 break;
403 memcpy(data_buf, buf, len);
404 } else {
405 memcpy(buf, data_buf, len);
406 if (_ca_sflash_write(priv, buf, len))
407 break;
408 }
409
410 total_cnt -= len;
411 data_buf += len;
412 }
413 if (buf)
414 free(buf);
415
416 return total_cnt > 0 ? -1 : 0;
417 }
418
_ca_sflash_issue_cmd(struct ca_sflash_priv * priv,struct spi_mem_op * op,u8 opcode)419 static int _ca_sflash_issue_cmd(struct ca_sflash_priv *priv,
420 struct spi_mem_op *op, u8 opcode)
421 {
422 u8 dummy_cnt = op->dummy.nbytes;
423 u8 addr_cnt = op->addr.nbytes;
424 u8 mio_width;
425 unsigned int data_cnt = op->data.nbytes;
426 u64 addr_offset = op->addr.val;
427
428 /* Set the access register */
429 clrsetbits_le32(&priv->regs->ar,
430 GENMASK(31, 0), CA_SF_AR_ACCODE(opcode));
431
432 if (opcode == CA_SF_AC_OP_EXTEND) { /* read_data, write_data */
433 if (data_cnt > 6) {
434 if (op->data.dir == SPI_MEM_DATA_IN)
435 mio_width = priv->rx_width;
436 else
437 mio_width = priv->tx_width;
438 if (_ca_sflash_mio_set(priv, mio_width))
439 return -1;
440 }
441 debug("%s: FLASH ACCESS reg=%#08x\n",
442 __func__, readl(&priv->regs->ar));
443
444 /* Use command in extend_access register */
445 clrsetbits_le32(&priv->regs->ear,
446 GENMASK(31, 0), CA_SF_EAR_OP(op->cmd.opcode)
447 | CA_SF_EAR_DUMY_CNT(dummy_cnt * 8 - 1)
448 | CA_SF_EAR_ADDR_CNT(addr_cnt - 1)
449 | CA_SF_EAR_DATA_CNT(4 - 1)
450 | CA_SF_EAR_DRD_CMD_EN);
451 debug("%s: FLASH EXT ACCESS reg=%#08x\n",
452 __func__, readl(&priv->regs->ear));
453
454 if (_ca_sflash_access_data(priv, op))
455 return -1;
456 } else { /* reset_op, wr_enable, wr_disable */
457 setbits_le32(&priv->regs->ar,
458 CA_SF_AR_OP(op->cmd.opcode));
459 debug("%s: FLASH ACCESS reg=%#08x\n",
460 __func__, readl(&priv->regs->ar));
461
462 if (opcode == CA_SF_AC_OP_4_ADDR) { /* erase_op */
463 /* Configure address length */
464 if (addr_cnt > 3) /* 4 Bytes address */
465 setbits_le32(&priv->regs->tr,
466 CA_FLASH_TR_SIZE(2));
467 else /* 3 Bytes address */
468 clrbits_le32(&priv->regs->tr,
469 CA_FLASH_TR_SIZE_MSK);
470
471 /* Fill address */
472 if (addr_cnt > 0)
473 clrsetbits_le32(&priv->regs->adr,
474 GENMASK(31, 0),
475 (u32)addr_offset);
476 }
477
478 if (_ca_sflash_wait_cmd(priv, RD_ACCESS))
479 return -1;
480 }
481 /* elapse 10us before issuing any other command */
482 udelay(10);
483
484 return 0;
485 }
486
ca_sflash_exec_op(struct spi_slave * slave,const struct spi_mem_op * op)487 static int ca_sflash_exec_op(struct spi_slave *slave,
488 const struct spi_mem_op *op)
489 {
490 struct ca_sflash_priv *priv = dev_get_priv(slave->dev->parent);
491 u8 opcode;
492
493 debug("%s: cmd:%#02x addr.val:%#llx addr.len:%#x data.len:%#x data.dir:%#x\n",
494 __func__, op->cmd.opcode, op->addr.val,
495 op->addr.nbytes, op->data.nbytes, op->data.dir);
496
497 if (op->data.nbytes == 0 && op->addr.nbytes == 0) {
498 opcode = CA_SF_AC_OP;
499 } else if (op->data.nbytes == 0 && op->addr.nbytes > 0) {
500 opcode = CA_SF_AC_OP_4_ADDR;
501 } else if (op->data.nbytes > 0) {
502 opcode = CA_SF_AC_OP_EXTEND;
503 } else {
504 printf("%s: can't support cmd.opcode:(%#02x) type currently!\n",
505 __func__, op->cmd.opcode);
506 return -1;
507 }
508
509 return _ca_sflash_issue_cmd(priv, (struct spi_mem_op *)op, opcode);
510 }
511
ca_sflash_init(struct ca_sflash_priv * priv)512 static void ca_sflash_init(struct ca_sflash_priv *priv)
513 {
514 /* Set FLASH_TYPE as serial flash, value: 0x0400*/
515 clrsetbits_le32(&priv->regs->tr,
516 GENMASK(31, 0), CA_FLASH_TR_SIZE(2));
517 debug("%s: FLASH_TYPE reg=%#x\n",
518 __func__, readl(&priv->regs->tr));
519
520 /* Minimize flash timing, value: 0x07010101 */
521 clrsetbits_le32(&priv->regs->tmr,
522 GENMASK(31, 0),
523 CA_SF_TMR_CLK(0x07)
524 | CA_SF_TMR_SETUP(0x01)
525 | CA_SF_TMR_HOLD(0x01)
526 | CA_SF_TMR_IDLE(0x01));
527 debug("%s: FLASH_TIMING reg=%#x\n",
528 __func__, readl(&priv->regs->tmr));
529 }
530
ca_sflash_probe(struct udevice * dev)531 static int ca_sflash_probe(struct udevice *dev)
532 {
533 struct ca_sflash_priv *priv = dev_get_priv(dev);
534 struct resource res;
535 int ret;
536
537 /* Map the registers */
538 ret = dev_read_resource_byname(dev, "sflash-regs", &res);
539 if (ret) {
540 dev_err(dev, "can't get regs base addresses(ret = %d)!\n", ret);
541 return ret;
542 }
543 priv->regs = devm_ioremap(dev, res.start, resource_size(&res));
544 if (IS_ERR(priv->regs))
545 return PTR_ERR(priv->regs);
546
547 ca_sflash_init(priv);
548
549 printf("SFLASH: Controller probed ready\n");
550 return 0;
551 }
552
553 static const struct spi_controller_mem_ops ca_sflash_mem_ops = {
554 .exec_op = ca_sflash_exec_op,
555 };
556
557 static const struct dm_spi_ops ca_sflash_ops = {
558 .claim_bus = ca_sflash_claim_bus,
559 .release_bus = ca_sflash_release_bus,
560 .set_speed = ca_sflash_set_speed,
561 .set_mode = ca_sflash_set_mode,
562 .mem_ops = &ca_sflash_mem_ops,
563 };
564
565 static const struct udevice_id ca_sflash_ids[] = {
566 {.compatible = "cortina,ca-sflash"},
567 {}
568 };
569
570 U_BOOT_DRIVER(ca_sflash) = {
571 .name = "ca_sflash",
572 .id = UCLASS_SPI,
573 .of_match = ca_sflash_ids,
574 .ops = &ca_sflash_ops,
575 .priv_auto = sizeof(struct ca_sflash_priv),
576 .probe = ca_sflash_probe,
577 };
578