1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Author :
4 * Vaibhav Hiremath <hvaibhav@ti.com>
5 *
6 * Based on mem.c and sdrc.c
7 *
8 * Copyright (C) 2010
9 * Texas Instruments Incorporated - http://www.ti.com/
10 */
11
12 #include <common.h>
13 #include <init.h>
14 #include <asm/global_data.h>
15 #include <asm/io.h>
16 #include <asm/arch/mem.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/emif4.h>
19
20 DECLARE_GLOBAL_DATA_PTR;
21 extern omap3_sysinfo sysinfo;
22
23 static emif4_t *emif4_base = (emif4_t *)OMAP34XX_SDRC_BASE;
24
25 /*
26 * is_mem_sdr -
27 * - Return 1 if mem type in use is SDR
28 */
is_mem_sdr(void)29 u32 is_mem_sdr(void)
30 {
31 return 0;
32 }
33
34 /*
35 * get_sdr_cs_size -
36 * - Get size of chip select 0/1
37 */
get_sdr_cs_size(u32 cs)38 u32 get_sdr_cs_size(u32 cs)
39 {
40 u32 size = 0;
41
42 /* TODO: Calculate the size based on EMIF4 configuration */
43 if (cs == CS0)
44 size = CONFIG_SYS_CS0_SIZE;
45
46 return size;
47 }
48
49 /*
50 * get_sdr_cs_offset -
51 * - Get offset of cs from cs0 start
52 */
get_sdr_cs_offset(u32 cs)53 u32 get_sdr_cs_offset(u32 cs)
54 {
55 u32 offset = 0;
56
57 return offset;
58 }
59
60 /*
61 * do_emif4_init -
62 * - Init the emif4 module for DDR access
63 * - Early init routines, called from flash or SRAM.
64 */
do_emif4_init(void)65 static void do_emif4_init(void)
66 {
67 unsigned int regval;
68 /* Set the DDR PHY parameters in PHY ctrl registers */
69 regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS |
70 EMIF4_DDR1_EXT_STRB_DIS);
71 writel(regval, &emif4_base->ddr_phyctrl1);
72 writel(regval, &emif4_base->ddr_phyctrl1_shdw);
73 writel(0, &emif4_base->ddr_phyctrl2);
74
75 /* Reset the DDR PHY and wait till completed */
76 regval = readl(&emif4_base->sdram_iodft_tlgc);
77 regval |= (1<<10);
78 writel(regval, &emif4_base->sdram_iodft_tlgc);
79 /*Wait till that bit clears*/
80 while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) != 0x0);
81 /*Re-verify the DDR PHY status*/
82 while ((readl(&emif4_base->sdram_sts) & (1<<2)) == 0x0);
83
84 regval |= (1<<0);
85 writel(regval, &emif4_base->sdram_iodft_tlgc);
86 /* Set SDR timing registers */
87 regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD |
88 EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS |
89 EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD |
90 EMIF4_TIM1_T_RP);
91 writel(regval, &emif4_base->sdram_time1);
92 writel(regval, &emif4_base->sdram_time1_shdw);
93
94 regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP |
95 EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR |
96 EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP);
97 writel(regval, &emif4_base->sdram_time2);
98 writel(regval, &emif4_base->sdram_time2_shdw);
99
100 regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC);
101 writel(regval, &emif4_base->sdram_time3);
102 writel(regval, &emif4_base->sdram_time3_shdw);
103
104 /* Set the PWR control register */
105 regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE |
106 EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE);
107 writel(regval, &emif4_base->sdram_pwr_mgmt);
108 writel(regval, &emif4_base->sdram_pwr_mgmt_shdw);
109
110 /* Set the DDR refresh rate control register */
111 regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS);
112 writel(regval, &emif4_base->sdram_refresh_ctrl);
113 writel(regval, &emif4_base->sdram_refresh_ctrl_shdw);
114
115 /* set the SDRAM configuration register */
116 regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK |
117 EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE |
118 EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD |
119 EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL |
120 EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM |
121 EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP);
122 writel(regval, &emif4_base->sdram_config);
123 }
124
125 /*
126 * dram_init -
127 * - Sets uboots idea of sdram size
128 */
dram_init(void)129 int dram_init(void)
130 {
131 unsigned int size0 = 0, size1 = 0;
132
133 size0 = get_sdr_cs_size(CS0);
134 /*
135 * If a second bank of DDR is attached to CS1 this is
136 * where it can be started. Early init code will init
137 * memory on CS0.
138 */
139 if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED))
140 size1 = get_sdr_cs_size(CS1);
141
142 gd->ram_size = size0 + size1;
143 return 0;
144 }
145
dram_init_banksize(void)146 int dram_init_banksize(void)
147 {
148 unsigned int size0 = 0, size1 = 0;
149
150 size0 = get_sdr_cs_size(CS0);
151 size1 = get_sdr_cs_size(CS1);
152
153 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
154 gd->bd->bi_dram[0].size = size0;
155 gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
156 gd->bd->bi_dram[1].size = size1;
157
158 return 0;
159 }
160
161 /*
162 * mem_init() -
163 * - Initialize memory subsystem
164 */
mem_init(void)165 void mem_init(void)
166 {
167 do_emif4_init();
168 }
169