1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
4 *
5 */
6
7 #include <altera.h>
8 #include <common.h>
9 #include <env.h>
10 #include <errno.h>
11 #include <init.h>
12 #include <log.h>
13 #include <asm/global_data.h>
14 #include <asm/io.h>
15 #include <asm/arch/mailbox_s10.h>
16 #include <asm/arch/misc.h>
17 #include <asm/arch/reset_manager.h>
18 #include <asm/arch/system_manager.h>
19
20 DECLARE_GLOBAL_DATA_PTR;
21
22 /*
23 * FPGA programming support for SoC FPGA Stratix 10
24 */
25 static Altera_desc altera_fpga[] = {
26 {
27 /* Family */
28 Intel_FPGA_SDM_Mailbox,
29 /* Interface type */
30 secure_device_manager_mailbox,
31 /* No limitation as additional data will be ignored */
32 -1,
33 /* No device function table */
34 NULL,
35 /* Base interface address specified in driver */
36 NULL,
37 /* No cookie implementation */
38 0
39 },
40 };
41
42
43 /*
44 * Print CPU information
45 */
46 #if defined(CONFIG_DISPLAY_CPUINFO)
print_cpuinfo(void)47 int print_cpuinfo(void)
48 {
49 puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n");
50
51 return 0;
52 }
53 #endif
54
55 #ifdef CONFIG_ARCH_MISC_INIT
arch_misc_init(void)56 int arch_misc_init(void)
57 {
58 char qspi_string[13];
59
60 sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
61 env_set("qspi_clock", qspi_string);
62
63 return 0;
64 }
65 #endif
66
arch_early_init_r(void)67 int arch_early_init_r(void)
68 {
69 socfpga_fpga_add(&altera_fpga[0]);
70
71 return 0;
72 }
73
74 /* Return 1 if FPGA is ready otherwise return 0 */
is_fpga_config_ready(void)75 int is_fpga_config_ready(void)
76 {
77 return (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGA_CONFIG) &
78 SYSMGR_FPGACONFIG_READY_MASK) == SYSMGR_FPGACONFIG_READY_MASK;
79 }
80
do_bridge_reset(int enable,unsigned int mask)81 void do_bridge_reset(int enable, unsigned int mask)
82 {
83 /* Check FPGA status before bridge enable */
84 if (!is_fpga_config_ready()) {
85 puts("FPGA not ready. Bridge reset aborted!\n");
86 return;
87 }
88
89 socfpga_bridges_reset(enable);
90 }
91